PLL tricks

[John Larkin]

On Wed, 24 Sep 2014 14:08:52 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 09/24/2014 11:01 AM, John Larkin wrote:
On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin
jlarkin@highlandtechnology.com> wrote:



If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.


Cool. 523 posts to this thread so far.

This might work:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/PLL_Series_Gate.JPG

It still does the phase compare at 80 KHz, probably a mathematical
necessity in my situation. But the phase detector gain is way higher
than a classical 2-pi phase detector... 1944 times as high, to be
exact. Picoseconds of phase error now become parts-per-thousand turf,
not parts per million.

The advantage over a bangbang detector is that the phase detector
output is linear on phase error, so the loop could be analyzed as
such, and will be far less noisy.

That 6 ns series gate, stable to around 0.1%, is non-trivial.

Ooh, that suggests a phase ADC, in a digital loop. Or maybe a multbit
bang-bang phase detector. Maybe later.



Phase digitizers are fun. I did one as a grad student, back around
1986--it ran at 60 MHz, 50k samples/s, and was good to 13 bits over a
cycle. It used an old-fashioned SAR chip plus DAC plus varactor phase
shifter, with a Mini Circuits RPD-1 phase detector. (It was one of the
two instruments papers I ever published.)
(*)
1 LSB of that digitizer was about 2 picoseconds--I learned the horrible
truth about picosecond stability and bending coax cables.

The stability of just the digitizer and its associated calibrator (which
was several times more complicated) was about +- 0.05 degrees over a few
hours, which is about +- 2 ps.

Cheers

Phil Hobbs



Hobbs, P. C. D., "High?performance amplitude and phase digitizers at 60
MHz", Rev. Sci. Instrum. 58, 1518 (1987)

I don't think I have a copy any place, or I'd post a link.

If I shaped the rising edge of the 10 MHz square wave, and digitized
that with a wideband ADC triggered at 80 KHz, I'd get an ADC code that
was about linear on phase error with full-span of 50 ps or some such.
Even 8 bits would get the LSB into the sub-ps range. Then do a digital
PID loop driving a DAC into the VCO input. I do something vaguely
similar in my DDGs.

Even more radical, digitize the 10 MHz sine wave at 155.52 MHz sample
rate and do a monstrous amount of math.

Multibit bang-bang would use several flops staggered in time to make a
thermometer code of phase shift. That would improve my loop noise a
little.

Single flop bang-bang is looking pretty good!



--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Bill Sloman]

On Thursday, 25 September 2014 17:43:14 UTC+10, Gerhard Hoffmann wrote:

Am 25.09.2014 um 04:40 schrieb John Larkin:

If I shaped the rising edge of the 10 MHz square wave, and digitized
that with a wideband ADC triggered at 80 KHz, I'd get an ADC code that
was about linear on phase error with full-span of 50 ps or some such.
Even 8 bits would get the LSB into the sub-ps range. Then do a digital
PID loop driving a DAC into the VCO input. I do something vaguely
similar in my DDGs.

Even more radical, digitize the 10 MHz sine wave at 155.52 MHz sample
rate and do a monstrous amount of math.

I had proposed that already for the almost all digital solution.

The filter after the 10 MHz digitizer could be a FIR and you get
zero crossings given by 2 samples 7 ns apart, each with say 16 bits.
The monstrous math would be just interpolation between 2 samples,
maybe 3 samples if you want to remove corner cases.

The aperture jitter of a 200 MHz 16 bit ADCis abt. 50 fs just for
bragging rights 16/200.

Which 16-bit 200MHz ADC?

You could use every rising 10 MHz edge, and, if you want, every
falling, too, The statistics of rising vs. falling would indicate
if you filter enough or if the 10MHz ref has a stable duty cycle.

There also would be no DAC after the DDS sine table, just one
after the phase detector (aka 16*16 multiplier) + interpolator
that outputs >= 16 bit values for the VCO tuning voltage with
10, 20 or 155 MHz or submultiples thereof pre-averaged by a FIR.

None of these filters would drift in any way.

No, but to give ADC something meaningful to sample you'd have to low-pass filter the 10MHz edges before you fed them into the ADC, probably with something like a 7nsec single-pole Converting the edges into linear ramps would be nice, but tricky (particularly if you wanted a rock-solid time constant for eventual sub-picosecond accuracy).

That is just a corner in a small Spartan-6 or newer.

For the computational part.

--
Bill Sloman, Sydney

 

[Bill Sloman]

On Thursday, 25 September 2014 18:22:24 UTC+10, Gerhard Hoffmann wrote:

Am 25.09.2014 um 10:08 schrieb Bill Sloman:
On Thursday, 25 September 2014 17:43:14 UTC+10, Gerhard Hoffmann wrote:

The filter after the 10 MHz digitizer could be a FIR and you get
zero crossings given by 2 samples 7 ns apart, each with say 16 bits.
The monstrous math would be just interpolation between 2 samples,
maybe 3 samples if you want to remove corner cases.

The aperture jitter of a 200 MHz 16 bit ADC is abt. 50 fs just for
bragging rights 16/200.

Which 16-bit 200MHz ADC?

http://lmgtfy.com/?q=ADC+16+bit+200+MSPS

Now, that was hard!

But it doesn't answer my question. Are you prepared to guarantee that every
16-bit 200mHz ADC has the same - nominally 50fs - aperture jitter?

I'd feel more comfortable with an explicit example.

There also would be no DAC after the DDS sine table, just one
after the phase detector (aka 16*16 multiplier) + interpolator
that outputs >= 16 bit values for the VCO tuning voltage with
10, 20 or 155 MHz or submultiples thereof pre-averaged by a FIR.

None of these filters would drift in any way.

No, but to give ADC something meaningful to sample you'd have to low-pass filter the 10MHz edges before you fed them into the ADC, probably with something like a 7nsec single-pole. Converting the edges into linear ramps would be nice, but tricky (particularly if you wanted a rock-solid time constant for eventual sub-picosecond accuracy).

That would be a real problem with nearly 16 times oversampling.
For some.

16-times over-sampling doesn't help much if all the samples taken are either high or low.

This is where you have to find a way of dithering the signal you measure in order to get a least one sample that is neither high nor low.

Low-pass filtering the 10MHz edge to convert it into something that spends at least 6.43nsec moving from high to low means that your ADC sampling at 155.52MHz will have some idea when one edge started moving. Only one in seven or eight will offer any timing information, and you'll have to check the previous sample to find out whether the ramp started off from high or low.

Once you've got some idea of what's going on, you'll know which edges are going to be worth sampling, which may save you some processing.

Some A/D converters get shirty about digitising very rapidly moving edges - another reason for being explicit about the device you have in mind.

--
Bill Sloman, Sydney

 

[Gerhard Hoffmann]

Am 25.09.2014 um 04:40 schrieb John Larkin:

If I shaped the rising edge of the 10 MHz square wave, and digitized
that with a wideband ADC triggered at 80 KHz, I'd get an ADC code that
was about linear on phase error with full-span of 50 ps or some such.
Even 8 bits would get the LSB into the sub-ps range. Then do a digital
PID loop driving a DAC into the VCO input. I do something vaguely
similar in my DDGs.

Even more radical, digitize the 10 MHz sine wave at 155.52 MHz sample
rate and do a monstrous amount of math.

I had proposed that already for the almost all digital solution.
The filter after the 10 MHz digitizer could be a FIR and you get
zero crossings given by 2 samples 7 ns apart, each with say 16 bits.
The monstrous math would be just interpolation between 2 samples,
maybe 3 samples if you want to remove corner cases.

The aperture jitter of a 200 MHz 16 bit dac is abt. 50 fs just for
bragging rights 16/200.

You could use every rising 10 MHz edge, and, if you want, every
falling, too, The statistics of rising vs. falling would indicate
if you filter enough or if the 10MHz ref has a stable duty cycle.

There also would be no DAC after the DDS sine table, just one
after the phase detector (aka 16*16 multiplier) + interpolator
that outputs >= 16 bit values for the VCO tuning voltage with
10, 20 or 155 MHz or submultiples thereof pre-averaged by a FIR.

None of these filters would drift in any way.

That is just a corner in a small Spartan-6 or newer.

regards, Gerhard

p.s. do you really use 10K FFs or 100K series that has
temp. compensation?

 

[Jan Panteltje]

On a sunny day (Wed, 24 Sep 2014 10:32:41 -0700) it happened John Larkin
<jlarkin@highlandtechnology.com> wrote in
<krv52adkaqkgtf9n78bitlt5begcs7u117@4ax.com>:

This might work:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/PLL_Series_Gate.JPG

Yes John, I invented that back in 1984
http://panteltje.com/panteltje/z80/system14/diagrams/fdc-2.jpg
and discussed it here in detail too.


I suspect someone else invented it before either of us. I invented the
bang-bang phase detector ca 1972, ditto.

Yes, many of us probably invented the wheel at some time.

The trick would be to make that series switch work with roughly 0.1%
precision, given a 6 ns gate.

The reason I came up with this was quite different.
In those old days floppies were fully of dropouts.
That caused missing pulses, driving the common phase detectors way to a lower frequency.
This circuit opens the sample gate only when a signal is present,
else it will keep running at its last frequency.
It worked so well that you could break a floppy with your fingers to a slow speed and would still read the data correctly.
The 'gain' (proportional) is in the width of the pulse that opens the switch.
So in theory at least, you can, after frequency lock, change that pulse width to change the gain.
Was not needed in this circuit.

 

[Gerhard Hoffmann]

Am 25.09.2014 um 10:08 schrieb Bill Sloman:

On Thursday, 25 September 2014 17:43:14 UTC+10, Gerhard Hoffmann wrote:

The filter after the 10 MHz digitizer could be a FIR and you get
zero crossings given by 2 samples 7 ns apart, each with say 16 bits.
The monstrous math would be just interpolation between 2 samples,
maybe 3 samples if you want to remove corner cases.

The aperture jitter of a 200 MHz 16 bit ADCis abt. 50 fs just for
bragging rights 16/200.

Which 16-bit 200MHz ADC?

< http://lmgtfy.com/?q=ADC+16+bit+200+MSPS >

Now, that was hard!

There also would be no DAC after the DDS sine table, just one
after the phase detector (aka 16*16 multiplier) + interpolator
that outputs >= 16 bit values for the VCO tuning voltage with
10, 20 or 155 MHz or submultiples thereof pre-averaged by a FIR.

None of these filters would drift in any way.

No, but to give ADC something meaningful to sample you'd have to low-pass filter the 10MHz edges before you fed them into the ADC, probably with something like a 7nsec single-pole Converting the edges into linear ramps would be nice, but tricky (particularly if you wanted a rock-solid time constant for eventual sub-picosecond accuracy).

That would be a real problem with nearly 16 times oversampling.
For some.

Gerhard

 

[Bill Sloman]

On 25/09/2014 5:43 PM, Gerhard Hoffmann wrote:

Am 25.09.2014 um 04:40 schrieb John Larkin:

p.s. do you really use 10K FFs or 100K series that has
temp. compensation?

He's probably using MC100EP parts - 10K and 100K was around thirty years
ago, and ECLinPS is a whole lot quicker. The distinction between 10 and
100 series ECL from Motorola is that 100 series parts have a temperature
compensated logic levels and threshold (as you probably know - as I
should have deduced from your last sentence after reading it very carefully)

http://www.onsemi.com/pub_link/Collateral/MC10EP16VA-D.PDF

The logic levels specifications for the 10EP16VA and 100EP16VA parts
tell the story. I know John's fond of the ECLinPS parts - he tells us so
from time to time. I like the original 100EL parts when I could first
get my hands on them, back around 1995. There was publicity for them -
but no parts - back around 1990 when I really could have used them, but
had to settle for Gigabit Logic's GaAs parts.

--
Bill Sloman, Sydney

 

[Gerhard Hoffmann]

Am 25.09.2014 um 10:55 schrieb Bill Sloman:

The aperture jitter of a 200 MHz 16 bit ADC is abt. 50 fs just for
bragging rights 16/200.

Which 16-bit 200MHz ADC?

http://lmgtfy.com/?q=ADC+16+bit+200+MSPS

Now, that was hard!

But it doesn't answer my question. Are you prepared to guarantee that every
16-bit 200mHz ADC has the same - nominally 50fs - aperture jitter?

I'd feel more comfortable with an explicit example.

For me, it's enough that AD, LT, TI and others guarantee it.

You can calculate yourself what worst case aperture jitter is required
for 200MHz/16 bit. Take a full scale sine wave at fNyquist, consider
the steepest part in the middle: how much risetime does it take to
change the reading from 0 to 1 on a +-32K scale?

If you cannot fix your sample point better in time than that, you have
no real 16 bit / 200 MHz DAC.

Most fast 16 bit ADCs spec sth. like 65 fs, and there are other
errors like noise, drift etc. No one expects full 16 bit accuracy.

There also would be no DAC after the DDS sine table, just one
after the phase detector (aka 16*16 multiplier) + interpolator
that outputs >= 16 bit values for the VCO tuning voltage with
10, 20 or 155 MHz or submultiples thereof pre-averaged by a FIR.

None of these filters would drift in any way.

No, but to give ADC something meaningful to sample you'd have to low-pass filter the 10MHz edges before you fed them into the ADC, probably with something like a 7nsec single-pole. Converting the edges into linear ramps would be nice, but tricky (particularly if you wanted a rock-solid time constant for eventual sub-picosecond accuracy).

That would be a real problem with nearly 16 times oversampling.
For some.

16-times over-sampling doesn't help much if all the samples taken are either high or low.

This is where you have to find a way of dithering the signal you measure in order to get a least one sample that is neither high nor low.

Low-pass filtering the 10MHz edge to convert it into something that spends at least 6.43nsec moving from high to low means that your ADC sampling at 155.52MHz will have some idea when one edge started moving. Only one in seven or eight will offer any timing information, and you'll have to check the previous sample to find out whether the ramp started off from high or low.

Once you've got some idea of what's going on, you'll know which edges are going to be worth sampling, which may save you some processing.

Some A/D converters get shirty about digitising very rapidly moving edges - another reason for being explicit about the device you have in mind.

Nobody would ever want to dither that. One gets every 10 MHz transition
and the digital low/high pass makes a perfect sine from it, no offset,
harmonics, noise, just remove the mirror at 145, 165, 300 MHz with an
analog filter.

There won't be much to do. It does not matter if the 10MHz is a sine
or square wave. Time labs prefer sines because one does not have to
care about reflections of the harmonics.

After filtering, you have a 16 bit digital sine wave that you can
multiply with a 16 bit digital sine wave from the DDS in one of
these DSP-48 blocks at a 155 Mwords/s rate.

Low pass filter with a FIR or CIC and output it to dac with
your choice of sample rate and resolution. A slow 20 bit
would be cheapest, probably.


Gerhard

 

[Bill Sloman]

On Thursday, 25 September 2014 22:40:27 UTC+10, Phil Hobbs wrote:

On 9/24/2014 11:07 PM, Bill Sloman wrote:
On 25/09/2014 1:01 AM, John Larkin wrote:
On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin
jlarkin@highlandtechnology.com> wrote:

<snip>

The duty cycle and rise/fall symmetry are unlikely to be close enough to
put both edges within 1 ps of each other, even if the board layout was
that good. If they aren't, you'd get a dead zone in between them, which
would be A Bad Thing.

They wouldn't give you a dead zone - this is going into a linear phase-shift-to-voltage-out converter, not John's bang-bang detector, so they'd just give alternating slightly different offsets which you could happily add together and minimise the sum to fix the net phase shift.

John's not really into locking absolute phase - 1psec is 0.2mm of propagation delay and his laser factory is rather bigger than that - so locking relative phase is fine.

In reality, John doesn't start of with a 10MHz square wave, but a 10MHz sine wave - as he got around to telling us 5 days after he'd started the thread.

On Monday, 15 September 2014 04:59:14 UTC+10, John Larkin wrote:

"That's the scariest part of the problem. It will be a single-ended
(BNC, coax) 10 MHz sine wave from a GPS-disciplined source. I need to
bandpass filter it, to remove as much ground-loop-EMI crud as
possible, and zero-cross detect it with a fast ECL comparator."

That's his source, and he should be able to turn it into a perfectly symmetrical square wave. Since the process of doing that - the bandpass filter and the comparator - both add potentially drifty propagation delays into his synchronisation path, he probably shouldn't do more than use a balun to reference it to local ground, and take Gerhard Hoffmann's advice and digitise the sine wave at 155.52MHz with a 200MHz or better A/D converter - of which there seem to plenty of 16-bit examples - and do a digital phase-locked loop on this digital data.

Once the data has been sampled into the digital domain, he's done his sampling and his mixing and everything subsequent can be sorted out in the digital domain in parallel or whatever, and he should be home free.

This is exactly the kind of insight that he was looking for when he opened the thread, and it's taken an impressively long time - two weeks - to crystallise out. He may not notice that his problem has been solved - not-invented-here is pervasive.

--
Bill Sloman, Sydney

 

[Phil Hobbs]

On 9/24/2014 11:07 PM, Bill Sloman wrote:

On 25/09/2014 1:01 AM, John Larkin wrote:
On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin
jlarkin@highlandtechnology.com> wrote:



If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.


Cool. 523 posts to this thread so far.

This might work:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/PLL_Series_Gate.JPG


It still does the phase compare at 80 KHz, probably a mathematical
necessity in my situation. But the phase detector gain is way higher
than a classical 2-pi phase detector... 1944 times as high, to be
exact. Picoseconds of phase error now become parts-per-thousand turf,
not parts per million.

The advantage over a bangbang detector is that the phase detector
output is linear on phase error, so the loop could be analyzed as
such, and will be far less noisy.

That 6 ns series gate, stable to around 0.1%, is non-trivial.

Ooh, that suggests a phase ADC, in a digital loop. Or maybe a multbit
bang-bang phase detector. Maybe later.

A second 6.4nsec series gate, looking at the inverted 10MHz reference,
972 cycles of the 155.52MHz clock later, could give you twice a many
edges per per unit time.

The duty cycle and rise/fall symmetry are unlikely to be close enough to
put both edges within 1 ps of each other, even if the board layout was
that good. If they aren't, you'd get a dead zone in between them, which
would be A Bad Thing.

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Bill Sloman]

On 25/09/2014 8:14 PM, Gerhard Hoffmann wrote:
> Am 25.09.2014 um 10:55 schrieb Bill Sloman:

<snip>

That would be a real problem with nearly 16 times oversampling.
For some.

16-times over-sampling doesn't help much if all the samples taken are
either high or low.

This is where you have to find a way of dithering the signal you
measure in order to get a least one sample that is neither high nor low.

Low-pass filtering the 10MHz edge to convert it into something that
spends at least 6.43nsec moving from high to low means that your ADC
sampling at 155.52MHz will have some idea when one edge started
moving. Only one in seven or eight will offer any timing information,
and you'll have to check the previous sample to find out whether the
ramp started off from high or low.

Once you've got some idea of what's going on, you'll know which edges
are going to be worth sampling, which may save you some processing.

Some A/D converters get shirty about digitising very rapidly moving
edges - another reason for being explicit about the device you have in
mind.

Nobody would ever want to dither that. One gets every 10 MHz transition
and the digital low/high pass makes a perfect sine from it, no offset,
harmonics, noise, just remove the mirror at 145, 165, 300 MHz with an
analog filter.

I hadn't been thinking hard enough about what the A/D converter would
actually be sampling.

To quote from John Larkin's post on Monday, 15 September 2014 04:59:14
UTC+10

The 10MHz reference will be "a single-ended (BNC, coax) 10 MHz sine
wave from a GPS-disciplined source. I need to bandpass filter it, to
remove as much ground-loop-EMI crud as possible".

The bandpass filter introduces it's own delay. He then goes on about
planning to stick the filtered output into a fast comparator - with an
extra nanosecond or so of propagation delay - to turn it into the kind
of ECL square wave that his bang-bang phase detector can cope with.

Sampling the original sine wave - or a a version of it that has been put
through a balun to reference it to local ground - with an A/D converter
clocked at 155.52MHz would work much better. 15.52 samples per cycle is
quite enough to tightly characterise the sine wave vis-a-vis the
nominally 155.5.52MHz clock that is doing the sampling, and equally
obviously enough to characterise the 155.52MHz frequency vis-a-vis the
10MHz reference.

The number-crunching involved in setting up a digital multiplying phase
detector is a bit intimidating, but - as you say - it can all be fitted
into a decent-sized programmable logic device, and the result spat out
via 20-bit sigma-delta D/A converter to keep the 155.52MHz VCXO tightly
synched to the 10MHz sine wave.

There won't be much to do. It does not matter if the 10MHz is a sine
or square wave. Time labs prefer sines because one does not have to
care about reflections of the harmonics.

And the sine wave signal tells you stuff about itself throughout the
whole cycle. Square waves are only informative at the rising and falling
edges. In between you just know that there's been a rsing or a falling
edge recently.

After filtering, you have a 16 bit digital sine wave that you can
multiply with a 16 bit digital sine wave from the DDS in one of
these DSP-48 blocks at a 155 Mwords/s rate.

Low pass filter with a FIR or CIC and output it to dac with
your choice of sample rate and resolution. A slow 20 bit
would be cheapest, probably.

John doesn't want more than 500Hz bandwidth into the VCXO, so a
sigma-delta is the obvious choice.

I think you've cracked it. Whether your solution has been presented in a
form that John Larkin will find persuasive is a different question.

--
Bill Sloman, Sydney

 

[Lasse Langwadt Christense]

Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:

On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann

ghf@hoffmann-hochfrequenz.de> wrote:



Am 25.09.2014 um 04:40 schrieb John Larkin:



If I shaped the rising edge of the 10 MHz square wave, and digitized

that with a wideband ADC triggered at 80 KHz, I'd get an ADC code that

was about linear on phase error with full-span of 50 ps or some such.

Even 8 bits would get the LSB into the sub-ps range. Then do a digital

PID loop driving a DAC into the VCO input. I do something vaguely

similar in my DDGs.



Even more radical, digitize the 10 MHz sine wave at 155.52 MHz sample

rate and do a monstrous amount of math.



I had proposed that already for the almost all digital solution.

The filter after the 10 MHz digitizer could be a FIR and you get

zero crossings given by 2 samples 7 ns apart, each with say 16 bits.

The monstrous math would be just interpolation between 2 samples,

maybe 3 samples if you want to remove corner cases.



I didn't have in mind any filtering of the sampled 10 MHz sinewave

data; just an enormous amount of math. We'd expect the samples to have

a pattern, namely a 10M sine wave sampled at 155.52. Any deviation

from that would generate a loop error, into the VCO. I'm not sure what

the algorithm would be (maybe some sort of cross-correlation?) but it

wouldn't be edge oriented.

should be straight forward pretty much a variation of a costas loops I guess,

quadrature DDS, multipliers and filters

http://en.wikipedia.org/wiki/Costas_loop#mediaviewer/File:Costas_loop_general_siangls.svg


-Lasse

 

[John Larkin]

On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
<ghf@hoffmann-hochfrequenz.de> wrote:

Am 25.09.2014 um 04:40 schrieb John Larkin:

If I shaped the rising edge of the 10 MHz square wave, and digitized
that with a wideband ADC triggered at 80 KHz, I'd get an ADC code that
was about linear on phase error with full-span of 50 ps or some such.
Even 8 bits would get the LSB into the sub-ps range. Then do a digital
PID loop driving a DAC into the VCO input. I do something vaguely
similar in my DDGs.

Even more radical, digitize the 10 MHz sine wave at 155.52 MHz sample
rate and do a monstrous amount of math.

I had proposed that already for the almost all digital solution.
The filter after the 10 MHz digitizer could be a FIR and you get
zero crossings given by 2 samples 7 ns apart, each with say 16 bits.
The monstrous math would be just interpolation between 2 samples,
maybe 3 samples if you want to remove corner cases.

I didn't have in mind any filtering of the sampled 10 MHz sinewave
data; just an enormous amount of math. We'd expect the samples to have
a pattern, namely a 10M sine wave sampled at 155.52. Any deviation
from that would generate a loop error, into the VCO. I'm not sure what
the algorithm would be (maybe some sort of cross-correlation?) but it
wouldn't be edge oriented.

The aperture jitter of a 200 MHz 16 bit dac is abt. 50 fs just for
bragging rights 16/200.

You could use every rising 10 MHz edge, and, if you want, every
falling, too, The statistics of rising vs. falling would indicate
if you filter enough or if the 10MHz ref has a stable duty cycle.

There also would be no DAC after the DDS sine table, just one
after the phase detector (aka 16*16 multiplier) + interpolator
that outputs >= 16 bit values for the VCO tuning voltage with
10, 20 or 155 MHz or submultiples thereof pre-averaged by a FIR.

None of these filters would drift in any way.

That is just a corner in a small Spartan-6 or newer.

regards, Gerhard

p.s. do you really use 10K FFs or 100K series that has
temp. compensation?

I've used MC10EL and 10EP parts. Any critical stuff is done full
differential, where the threshold voltages are zero. Delay tempcos are
very low.




--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[rickman]

On 9/25/2014 12:10 PM, John Larkin wrote:

On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:

Am 25.09.2014 um 04:40 schrieb John Larkin:

If I shaped the rising edge of the 10 MHz square wave, and digitized
that with a wideband ADC triggered at 80 KHz, I'd get an ADC code that
was about linear on phase error with full-span of 50 ps or some such.
Even 8 bits would get the LSB into the sub-ps range. Then do a digital
PID loop driving a DAC into the VCO input. I do something vaguely
similar in my DDGs.

Even more radical, digitize the 10 MHz sine wave at 155.52 MHz sample
rate and do a monstrous amount of math.

I had proposed that already for the almost all digital solution.
The filter after the 10 MHz digitizer could be a FIR and you get
zero crossings given by 2 samples 7 ns apart, each with say 16 bits.
The monstrous math would be just interpolation between 2 samples,
maybe 3 samples if you want to remove corner cases.

I didn't have in mind any filtering of the sampled 10 MHz sinewave
data; just an enormous amount of math. We'd expect the samples to have
a pattern, namely a 10M sine wave sampled at 155.52. Any deviation
from that would generate a loop error, into the VCO. I'm not sure what
the algorithm would be (maybe some sort of cross-correlation?) but it
wouldn't be edge oriented.

You don't have any idea what algorithm you might use, but you know it
will take "an enormous amount of math"...

Ok, we'll get right on that...

Here is a suggestion. You can measure the phase of the reference sine
wave by correlating it with a 10 MHz sine and cosine from an NCO inside
the FPGA. This can be used to calculate the phase angle. You don't
need to use an integer number of 10 MHz cycles so the correlation length
can be anything you like. The shorter the correlation length the lower
your resolution in each result, but since many ADC measurements are
being averaged by the correlations it should give you good SNR and
resolution even for short correlation lengths.

Heck, you can even overlap the correlations and produce a result on
every 155.52 MHz clock with long correlation lengths. Treat the
correlations like a boxcar filter, add the new sample-coefficient
product in and take the old one out. You just need a buffer to hold the
old product data. Is 155.52 MHz a fast enough update rate for your
phase detector? You can make the correlation length very long and get a
nice slow response, rather like a filter.

Once you have the signal inside the FPGA the NCOs are easy, we've been
discussing that a lot, it's just the DDS without the DAC. Sine and
cosine are from the same phase accumulator and lookup table, you just
twiddle the upper two binary bits of the phase to offset the result by
90 degrees. Picture the phase accumulator as being two bits shorter and
counting a quarter of the total range. Then use a 2 bit binary counter
on the overflow from the lower portion to control the quadrant the look
up table maps into.

BTW, this is not really an "enormous" amount of math. It should fit in
a corner of most FPGAs, even a fairly small one. Heck, you could use a
low power device like an iCE40 or even a flash based device like the XP2.

--

Rick

 

[Ralph Barone]

Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann

ghf@hoffmann-hochfrequenz.de> wrote:



Am 25.09.2014 um 04:40 schrieb John Larkin:



If I shaped the rising edge of the 10 MHz square wave, and digitized

that with a wideband ADC triggered at 80 KHz, I'd get an ADC code that

was about linear on phase error with full-span of 50 ps or some such.

Even 8 bits would get the LSB into the sub-ps range. Then do a digital

PID loop driving a DAC into the VCO input. I do something vaguely

similar in my DDGs.



Even more radical, digitize the 10 MHz sine wave at 155.52 MHz sample

rate and do a monstrous amount of math.



I had proposed that already for the almost all digital solution.

The filter after the 10 MHz digitizer could be a FIR and you get

zero crossings given by 2 samples 7 ns apart, each with say 16 bits.

The monstrous math would be just interpolation between 2 samples,

maybe 3 samples if you want to remove corner cases.



I didn't have in mind any filtering of the sampled 10 MHz sinewave

data; just an enormous amount of math. We'd expect the samples to have

a pattern, namely a 10M sine wave sampled at 155.52. Any deviation

from that would generate a loop error, into the VCO. I'm not sure what

the algorithm would be (maybe some sort of cross-correlation?) but it

wouldn't be edge oriented.


should be straight forward pretty much a variation of a costas loops I guess,

quadrature DDS, multipliers and filters

http://en.wikipedia.org/wiki/Costas_loop#mediaviewer/File:Costas_loop_general_siangls.svg


-Lasse

How about "take 1944 samples, do a DFT, throw out the amplitude information
and run your VCXO from the phase information"?

 

[rickman]

On 9/25/2014 10:26 PM, Ralph Barone wrote:

Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann

ghf@hoffmann-hochfrequenz.de> wrote:



Am 25.09.2014 um 04:40 schrieb John Larkin:



If I shaped the rising edge of the 10 MHz square wave, and digitized

that with a wideband ADC triggered at 80 KHz, I'd get an ADC code that

was about linear on phase error with full-span of 50 ps or some such.

Even 8 bits would get the LSB into the sub-ps range. Then do a digital

PID loop driving a DAC into the VCO input. I do something vaguely

similar in my DDGs.



Even more radical, digitize the 10 MHz sine wave at 155.52 MHz sample

rate and do a monstrous amount of math.



I had proposed that already for the almost all digital solution.

The filter after the 10 MHz digitizer could be a FIR and you get

zero crossings given by 2 samples 7 ns apart, each with say 16 bits.

The monstrous math would be just interpolation between 2 samples,

maybe 3 samples if you want to remove corner cases.



I didn't have in mind any filtering of the sampled 10 MHz sinewave

data; just an enormous amount of math. We'd expect the samples to have

a pattern, namely a 10M sine wave sampled at 155.52. Any deviation

from that would generate a loop error, into the VCO. I'm not sure what

the algorithm would be (maybe some sort of cross-correlation?) but it

wouldn't be edge oriented.


should be straight forward pretty much a variation of a costas loops I guess,

quadrature DDS, multipliers and filters

http://en.wikipedia.org/wiki/Costas_loop#mediaviewer/File:Costas_loop_general_siangls.svg


-Lasse

How about "take 1944 samples, do a DFT, throw out the amplitude information
and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce overlapped
results (of any length) on every cycle of the 155.52 MHz clock. So no
need to wait 12.5 microseconds to close the loop.

--

Rick

 

[Lasse Langwadt Christense]

Den fredag den 26. september 2014 04.26.25 UTC+2 skrev Ralph Barone:

Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:

On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann



ghf@hoffmann-hochfrequenz.de> wrote:







Am 25.09.2014 um 04:40 schrieb John Larkin:







If I shaped the rising edge of the 10 MHz square wave, and digitized



that with a wideband ADC triggered at 80 KHz, I'd get an ADC code that



was about linear on phase error with full-span of 50 ps or some such.



Even 8 bits would get the LSB into the sub-ps range. Then do a digital



PID loop driving a DAC into the VCO input. I do something vaguely



similar in my DDGs.







Even more radical, digitize the 10 MHz sine wave at 155.52 MHz sample



rate and do a monstrous amount of math.







I had proposed that already for the almost all digital solution.



The filter after the 10 MHz digitizer could be a FIR and you get



zero crossings given by 2 samples 7 ns apart, each with say 16 bits.



The monstrous math would be just interpolation between 2 samples,



maybe 3 samples if you want to remove corner cases.







I didn't have in mind any filtering of the sampled 10 MHz sinewave



data; just an enormous amount of math. We'd expect the samples to have



a pattern, namely a 10M sine wave sampled at 155.52. Any deviation



from that would generate a loop error, into the VCO. I'm not sure what



the algorithm would be (maybe some sort of cross-correlation?) but it



wouldn't be edge oriented.





should be straight forward pretty much a variation of a costas loops I guess,



quadrature DDS, multipliers and filters



http://en.wikipedia.org/wiki/Costas_loop#mediaviewer/File:Costas_loop_general_siangls.svg





-Lasse



How about "take 1944 samples, do a DFT, throw out the amplitude information

and run your VCXO from the phase information"?

same thing really, dft is correlation with sin/cos

so the difference is basically comes down to continues output from filters vs.
integrate and dump and output every 1944 samples



-Lasse

 

[Phil Hobbs]

On 9/26/2014 3:02 AM, rickman wrote:

On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann

ghf@hoffmann-hochfrequenz.de> wrote:



Am 25.09.2014 um 04:40 schrieb John Larkin:



If I shaped the rising edge of the 10 MHz square wave, and digitized

that with a wideband ADC triggered at 80 KHz, I'd get an ADC code
that

was about linear on phase error with full-span of 50 ps or some such.

Even 8 bits would get the LSB into the sub-ps range. Then do a
digital

PID loop driving a DAC into the VCO input. I do something vaguely

similar in my DDGs.



Even more radical, digitize the 10 MHz sine wave at 155.52 MHz sample

rate and do a monstrous amount of math.



I had proposed that already for the almost all digital solution.

The filter after the 10 MHz digitizer could be a FIR and you get

zero crossings given by 2 samples 7 ns apart, each with say 16 bits.

The monstrous math would be just interpolation between 2 samples,

maybe 3 samples if you want to remove corner cases.



I didn't have in mind any filtering of the sampled 10 MHz sinewave

data; just an enormous amount of math. We'd expect the samples to have

a pattern, namely a 10M sine wave sampled at 155.52. Any deviation

from that would generate a loop error, into the VCO. I'm not sure what

the algorithm would be (maybe some sort of cross-correlation?) but it

wouldn't be edge oriented.


should be straight forward pretty much a variation of a costas loops
I guess,

quadrature DDS, multipliers and filters

http://en.wikipedia.org/wiki/Costas_loop#mediaviewer/File:Costas_loop_general_siangls.svg



-Lasse

How about "take 1944 samples, do a DFT, throw out the amplitude
information
and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce overlapped
results (of any length) on every cycle of the 155.52 MHz clock. So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

ISTM that the main issues with the B-B loop are: (1) gross PD ripple;
(b) the huge and poorly controlled gain of the phase detector, which
will depend critically on the residual wideband jitter of the two
clocks; and (c), that all the wideband jitter of the VCXO will be
aliased down into the fundamental interval.

Any metastability worries can be got round by reclocking the PD output
from either one of the oscillators, which won't cause significant extra
latency in an 80-kHz loop. Wrapping the VCXO inside a simple wideband
fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM none
will accomplish the required long-term timing stability.)

The residual drift and low-frequency crap could be removed afterwards,
using the bang-bang PD to control a varactor phase shifter on the 10 MHz
sine wave input. The combination ought to be pretty impressive.

Cheers

Phil Hobbs




--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Bill Sloman]

On 26/09/2014 11:08 PM, Phil Hobbs wrote:

On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

<snip>

How about "take 1944 samples, do a DFT, throw out the amplitude
information and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce overlapped
results (of any length) on every cycle of the 155.52 MHz clock. So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

There's no intrinsic 1944 sample latency if you are using an A/D
converter to sample the 10MHz reference sine wave at 155.52MHz.

With infinite computational resources you could do a non-linear
least-squares fit of a 10MHz-ish sine wave to anything more than about
four successive samples - since you can be pretty confident that you are
looking at a 10MHz sine wave. With a few as 16 samples - if there was
hardly any noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

The 10MHz sine wave would be described by four parameters - frequency,
absolute phase, amplitude and DC offset. The DC offset ought to be zero,
but A/D converters aren't perfect.

Since John actually wants only about 500Hz bandwidth in his PLL feedback
path, worrying about a 12.5usec latency implicit in the 1944 sample
repeat cycle is probably not a useful exercise, even if it were real.

ISTM that the main issues with the B-B loop are: (1) gross PD ripple;
(b) the huge and poorly controlled gain of the phase detector, which
will depend critically on the residual wideband jitter of the two
clocks; and (c), that all the wideband jitter of the VCXO will be
aliased down into the fundamental interval.

Any metastability worries can be got round by reclocking the PD output
from either one of the oscillators, which won't cause significant extra
latency in an 80-kHz loop. Wrapping the VCXO inside a simple wideband
fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM none
will accomplish the required long-term timing stability.)

The residual drift and low-frequency crap could be removed afterwards,
using the bang-bang PD to control a varactor phase shifter on the 10 MHz
sine wave input. The combination ought to be pretty impressive.

One would be impressed that he'd got it to work, less impressed by the
fact that he hadn't been able to recognise the superiority of any of the
better schemes that have been proposed here.

My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter sampling at
155.52MHz and feeding a number cruncher embedded in a reasonably big
programmable logic device. He mentioned a Xilinx Spartan-6

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/

I'm old-fashioned - I find anything more powerful than 22V10 a trifle
intimidating, though I did some useful stuff with the PA7024 (which is a
more powerful drop-in replacement for 22V10).

--
Bill Sloman, Sydney

 

[John Larkin]

On Fri, 26 Sep 2014 09:08:31 -0400, Phil Hobbs
<hobbs@electrooptical.net> wrote:

On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann

ghf@hoffmann-hochfrequenz.de> wrote:



Am 25.09.2014 um 04:40 schrieb John Larkin:



If I shaped the rising edge of the 10 MHz square wave, and digitized

that with a wideband ADC triggered at 80 KHz, I'd get an ADC code
that

was about linear on phase error with full-span of 50 ps or some such.

Even 8 bits would get the LSB into the sub-ps range. Then do a
digital

PID loop driving a DAC into the VCO input. I do something vaguely

similar in my DDGs.



Even more radical, digitize the 10 MHz sine wave at 155.52 MHz sample

rate and do a monstrous amount of math.



I had proposed that already for the almost all digital solution.

The filter after the 10 MHz digitizer could be a FIR and you get

zero crossings given by 2 samples 7 ns apart, each with say 16 bits.

The monstrous math would be just interpolation between 2 samples,

maybe 3 samples if you want to remove corner cases.



I didn't have in mind any filtering of the sampled 10 MHz sinewave

data; just an enormous amount of math. We'd expect the samples to have

a pattern, namely a 10M sine wave sampled at 155.52. Any deviation

from that would generate a loop error, into the VCO. I'm not sure what

the algorithm would be (maybe some sort of cross-correlation?) but it

wouldn't be edge oriented.


should be straight forward pretty much a variation of a costas loops
I guess,

quadrature DDS, multipliers and filters

http://en.wikipedia.org/wiki/Costas_loop#mediaviewer/File:Costas_loop_general_siangls.svg



-Lasse

How about "take 1944 samples, do a DFT, throw out the amplitude
information
and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce overlapped
results (of any length) on every cycle of the 155.52 MHz clock. So no
need to wait 12.5 microseconds to close the loop.


There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

The problem that I see is that, if all the sinewave samples contribute
to the lock phase, then the sine wave has to be incredibly pure, and
the ADC incredibly accurate. A better algorithm would use the sinewave
samples for the HF part of the loop but something else for the DC
pull-in. And I still need to get the 1 PPS into there.

ISTM that the main issues with the B-B loop are: (1) gross PD ripple;

I think that will be OK, if the VCXO is good. Slow loop filter.

(b) the huge and poorly controlled gain of the phase detector, which
will depend critically on the residual wideband jitter of the two
clocks;

I don't care too much if it's uncontrolled, as long as it's huge!


and (c), that all the wideband jitter of the VCXO will be
>aliased down into the fundamental interval.

Low VCXO jitter is the goal. I think it can be kept down in the low ps
RMS.

Any metastability worries can be got round by reclocking the PD output
from either one of the oscillators, which won't cause significant extra
latency in an 80-kHz loop.

What, me worry? About metastability? Metastability is the award for
doing everything right.


Wrapping the VCXO inside a simple wideband

fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM none
will accomplish the required long-term timing stability.)

The residual drift and low-frequency crap could be removed afterwards,
using the bang-bang PD to control a varactor phase shifter on the 10 MHz
sine wave input. The combination ought to be pretty impressive.

Bangbang is the ultimate timing feedback. If the loop filter can't
attenuate the bangbang noise enough to keep the jitter down, I'll need
some faster AC-coupled feedback thing to fix that, some classical
RFish thing.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com