PLL tricks

[Bill Sloman]

On 24/09/2014 4:52 PM, Jeroen Belleman wrote:

On 2014-09-24 08:29, rickman wrote:
On 9/24/2014 1:52 AM, Bill Sloman wrote:
On Wednesday, 24 September 2014 13:51:19 UTC+10, rickman wrote:
On 9/23/2014 11:28 PM, Bill Sloman wrote:
On Tuesday, 23 September 2014 22:48:02 UTC+10, dagmarg...@yahoo.com
wrote:
On Monday, September 22, 2014 9:53:47 PM UTC-4, Bill Sloman wrote:
On Tuesday, 23 September 2014 10:48:11 UTC+10, dagmarg...@yahoo.com
wrote:

<snip>

The DAC and the following low-pass are there only to smooth out the
6.4ns cycle-to-cyle variations of the 10MHz DDS output. I don't see
why one would bother with a DAC at all. Just use the MSB of the phase
accumulator and let the loop filter do the filtering. No more drifty
analog filters in the critical path.

I think the issue here is the phase-to-voltage linearity of the phase
detector. Fractional-n puts up to 6.4nsec - typically about 3nsec -
phase excursions on pretty much every clock edge, and you want them to
cancel out - to sub-picoscend accuracy over the 12.5usec it takes the
cycle to repeat.

DDS offers a much better approximation to a 10MHz sine wave going into
the phase detector and puts a correspondingly lower demand on it's
linearity.

John Larkin is infatuated with his - totally non-linear - edge driven
bang-bang phase detector, so fractional-n doesn't get a look-in.

If you tweak the NCO to make the MSB a 50% duty cycle square wave
on average, you can pipe it straight into a DB mixer with your
sine-wave 10MHz reference at the other input to make the phase
error signal.

Tricky. The fractional-N approximation from a 155.52MHz clock to a
10MHz output is 56 15-cycle segments and 69 16 cycle segments, which
cycles at 80kHz.

You can split the 16 cycle segments into 8+8 but the 15 cycle ones are 7+8.

The crudest way of getting there is a 250 entry look-up table - 194
divide by eight and 56 divide by seven. You end up with 30 three divides
by eight followed by one divide by seven, plus 26 four divides by eight
followed by one divide by seven.

--
Bill Sloman, Sydney

 

[rickman]

On 9/24/2014 2:52 AM, Jeroen Belleman wrote:

On 2014-09-24 08:29, rickman wrote:
On 9/24/2014 1:52 AM, Bill Sloman wrote:
On Wednesday, 24 September 2014 13:51:19 UTC+10, rickman wrote:
On 9/23/2014 11:28 PM, Bill Sloman wrote:
On Tuesday, 23 September 2014 22:48:02 UTC+10, dagmarg...@yahoo.com
wrote:
On Monday, September 22, 2014 9:53:47 PM UTC-4, Bill Sloman wrote:
On Tuesday, 23 September 2014 10:48:11 UTC+10, dagmarg...@yahoo.com
wrote:

The DDS in the signal path adds a horrendous, variable delay,
loads of
transistors in the signal path, and no control over how clean the
supplies and signals are. I don't see how the DDS' wandering analog
output delay can be re-sync'd to the reference clock, something the
bang-bang can do with a single flop.

The DDS would use the 155.52MHz source to clock the DAC producing
the stair-case approximation to the desired 10MHz waveform.

That's not any kind of "horrendous variable delay" and there are
very few transistors in that signal path. And you've got total
control over rails feeding the DDS chip. The DDS doesn't have any
kind of "wandering analog output delay".

AIUI the object is to stabilize the phase of the 155.52MHz output to
~10ppm w.r.t. a precision 10MHz reference signal.

When you insert the DDS between the output signal and the phase
comparison, you've added an uncalibrated delay that cannot be
removed, ditto any noise or jitter produced in the DDS, that's my
point.

And it's a very poor one.

In my previous response to this post I mentioned that you could roll
your own DDS and get pick your own - calibrated - delay through the
DDS, which got me thinking about what a roll-your-own DDS might look
like.

Doing the usual minimal search on just-fast-enough DACs threw up the
Analog Devices

http://www.analog.com/static/imported-files/data_sheets/AD9704_9705_9706_9707.pdf



which are just fast enough - with a maximum up-date rate of 175MHz -
and have a typical output propagation delay of 4nsec.

http://www.analog.com/static/imported-files/data_sheets/AD9751.pdf

is faster, and not all that expensive, and offers a typical output
propagation delay of 1nsec. No doubt one could do better.

The rest of the DDS could be jammed into a single programmable logic
device, and would consist of an 11-bit address counter that counted
edges of the 155.52MHZ clock, from 0 to 1943 and rolled over to 0
after 1943, to address a 1944-entry sine lookup table, whose output
would drive the DAC (via a latch to re-sycnronise the digital output
to the 155.52MHz clock).

One of the nice things about working at a fixed frequency is that
you can use the DAC to drive an integrator, generating a
straight-line segment approximation to a sine wave, rather than the
usual DDS stair-case. A single pole of low-pass filtering on the DAC
output current - about 3nsec worth - could smooth the transitions
between the straight-line segments and smear out any switching
glitches.

Of course you'd have to add a slow DC-feedback loop around the
integrator to keep the output centered around 0V (or whatever fixed
DC voltage took your fancy) but that's not rocket science

It's taken me a surprisingly long time to wake up to this point. You
could also integrate the output of conventional DDS chip to get the
same effect.

Perhaps you could explain to me why you need a fast DAC if you are
going
to filter it through a low pass filter?

John Larkin wants to lock his 155.52MHz local clock to the 10MHz
reference clock distributed around the laser farm, and he wants to do
it with sub-picosecond long term stability.

There's a delay between clocking the DDS digital data on an edge of
the 155.52MHz clock, and the analog output from the DAC going into the
integrator.

There's a further delay through the integrator, but if you wrap it
around a really fast op amp, it won't be big either.

The delays, and - more important - all the drifts on these delays -
add up and eat into John's error budget. The crudest - but often the
most effective way of minimising - the drifts on the individual delays
is simply to keep them small.

It might be an argument for going for fractional-n rather than DDS for
getting the derived 10MHz waveform. With that you are definitely stuck
with a linear phase detector, but there are a up to 6.4nsec of phase
excursion on each nominally 10MHz edge, but the delays can all be
through ECLinPS logic.

I didn't need a recap of the whole thing. The question is why would you
worry about a couple of nanoseconds on the DAC when you are running the
output through a filter which delays it further likely by a larger
amount?


When you say "integrator" do you mean integrator or low pass filter?

I mean an integrator.

I'm unclear on what waveform you would expect from an integrator. Are

you going to set the values in your sine table to be the deltas rather
than the sine values? That might make sense.

The integral and the derivation of a sine wave is a cosine wave. It's
not rocket science.

No, but you are messing further with the delays which you seem to say
you care about. In reality the delays on this portion of the circuit
are moot. They will be calibrated out.

But this does give me some interesting ideas on better ways to do the
DAC.


The DAC and the following low-pass are there only to smooth out the
6.4ns cycle-to-cyle variations of the 10MHz DDS output. I don't see
why one would bother with a DAC at all. Just use the MSB of the phase
accumulator and let the loop filter do the filtering. No more drifty
analog filters in the critical path.

If you tweak the NCO to make the MSB a 50% duty cycle square wave
on average, you can pipe it straight into a DB mixer with your
sine-wave 10MHz reference at the other input to make the phase
error signal.

Perhaps, but DDS is not always about PLL. There are plenty of times
when you want a sine wave as your output.

--

Rick

 

[Jeroen Belleman]

On 2014-09-24 09:34, Bill Sloman wrote:

On 24/09/2014 4:52 PM, Jeroen Belleman wrote:
On 2014-09-24 08:29, rickman wrote:
On 9/24/2014 1:52 AM, Bill Sloman wrote:
On Wednesday, 24 September 2014 13:51:19 UTC+10, rickman wrote:
On 9/23/2014 11:28 PM, Bill Sloman wrote:
On Tuesday, 23 September 2014 22:48:02 UTC+10, dagmarg...@yahoo.com
wrote:
On Monday, September 22, 2014 9:53:47 PM UTC-4, Bill Sloman wrote:
On Tuesday, 23 September 2014 10:48:11 UTC+10, dagmarg...@yahoo.com
wrote:

snip


The DAC and the following low-pass are there only to smooth out the
6.4ns cycle-to-cyle variations of the 10MHz DDS output. I don't see
why one would bother with a DAC at all. Just use the MSB of the phase
accumulator and let the loop filter do the filtering. No more drifty
analog filters in the critical path.

I think the issue here is the phase-to-voltage linearity of the phase
detector. Fractional-n puts up to 6.4nsec - typically about 3nsec -
phase excursions on pretty much every clock edge, and you want them to
cancel out - to sub-picoscend accuracy over the 12.5usec it takes the
cycle to repeat.

DDS offers a much better approximation to a 10MHz sine wave going into
the phase detector and puts a correspondingly lower demand on it's
linearity.

John Larkin is infatuated with his - totally non-linear - edge driven
bang-bang phase detector, so fractional-n doesn't get a look-in.

If you tweak the NCO to make the MSB a 50% duty cycle square wave
on average, you can pipe it straight into a DB mixer with your
sine-wave 10MHz reference at the other input to make the phase
error signal.

Tricky. The fractional-N approximation from a 155.52MHz clock to a 10MHz
output is 56 15-cycle segments and 69 16 cycle segments, which cycles at
80kHz.

You can split the 16 cycle segments into 8+8 but the 15 cycle ones are 7+8.

The crudest way of getting there is a 250 entry look-up table - 194
divide by eight and 56 divide by seven. You end up with 30 three divides
by eight followed by one divide by seven, plus 26 four divides by eight
followed by one divide by seven.

I haven't worked out the details, but I might try to make an NCO with
a phase accumulator constrained to values between -972 to 971 when
interpreted as a signed 2's-complement number. Add 125 on each beat
of the 155.52MHz clock and the sign bit ends up a fair approximation
of a 50% duty cycle square at exactly 10MHz on average, with the phase
error pattern repeating every 12.5us. That's an FPGA job, of course.
Reclock the sign bit using an ECL FF clocked with the original clean
155.52MHz to remove FPGA-induced vagaries.

Removing the cycle-to-cycle phase variations is the loop filter's
job. They average out over 12.5us.

Jeroen Belleman

 

[rickman]

On 9/24/2014 4:55 AM, Jeroen Belleman wrote:

On 2014-09-24 09:34, Bill Sloman wrote:
On 24/09/2014 4:52 PM, Jeroen Belleman wrote:
On 2014-09-24 08:29, rickman wrote:
On 9/24/2014 1:52 AM, Bill Sloman wrote:
On Wednesday, 24 September 2014 13:51:19 UTC+10, rickman wrote:
On 9/23/2014 11:28 PM, Bill Sloman wrote:
On Tuesday, 23 September 2014 22:48:02 UTC+10, dagmarg...@yahoo.com
wrote:
On Monday, September 22, 2014 9:53:47 PM UTC-4, Bill Sloman wrote:
On Tuesday, 23 September 2014 10:48:11 UTC+10,
dagmarg...@yahoo.com
wrote:

snip


The DAC and the following low-pass are there only to smooth out the
6.4ns cycle-to-cyle variations of the 10MHz DDS output. I don't see
why one would bother with a DAC at all. Just use the MSB of the phase
accumulator and let the loop filter do the filtering. No more drifty
analog filters in the critical path.

I think the issue here is the phase-to-voltage linearity of the phase
detector. Fractional-n puts up to 6.4nsec - typically about 3nsec -
phase excursions on pretty much every clock edge, and you want them to
cancel out - to sub-picoscend accuracy over the 12.5usec it takes the
cycle to repeat.

DDS offers a much better approximation to a 10MHz sine wave going into
the phase detector and puts a correspondingly lower demand on it's
linearity.

John Larkin is infatuated with his - totally non-linear - edge driven
bang-bang phase detector, so fractional-n doesn't get a look-in.

If you tweak the NCO to make the MSB a 50% duty cycle square wave
on average, you can pipe it straight into a DB mixer with your
sine-wave 10MHz reference at the other input to make the phase
error signal.

Tricky. The fractional-N approximation from a 155.52MHz clock to a 10MHz
output is 56 15-cycle segments and 69 16 cycle segments, which cycles at
80kHz.

You can split the 16 cycle segments into 8+8 but the 15 cycle ones are
7+8.

The crudest way of getting there is a 250 entry look-up table - 194
divide by eight and 56 divide by seven. You end up with 30 three divides
by eight followed by one divide by seven, plus 26 four divides by eight
followed by one divide by seven.


I haven't worked out the details, but I might try to make an NCO with
a phase accumulator constrained to values between -972 to 971 when
interpreted as a signed 2's-complement number. Add 125 on each beat
of the 155.52MHz clock and the sign bit ends up a fair approximation
of a 50% duty cycle square at exactly 10MHz on average, with the phase
error pattern repeating every 12.5us. That's an FPGA job, of course.
Reclock the sign bit using an ECL FF clocked with the original clean
155.52MHz to remove FPGA-induced vagaries.

Removing the cycle-to-cycle phase variations is the loop filter's
job. They average out over 12.5us.

Of course logic is cheap in an FPGA so such a counter is not a big deal
to implement. But it can be smaller/faster to use a phase accumulator
that ranges between 0 and 971 followed by a divide by two FF to make the
square wave. Rather than use the MSB, make it a subtractor so that the
carry out is your flag to both reload the accumulator with the adjusted
value for the modulus and to toggle the square wave FF.

If you need something like this to run as fast as possible, the carry
can be registered and used to select the subtracted constant between 125
and 177 on the next clock cycle (using a 10 bit binary accumulator).
Since in this case you will have more than two clock cycles between the
counter rolling over it can be further pipelined with a register between
the constant selection and the subtractor to allow the design to run at
very high rates limited by the bit width of the subtractor.

--

Rick

 

[Jeroen Belleman]

On 2014-09-24 13:09, rickman wrote:

On 9/24/2014 4:55 AM, Jeroen Belleman wrote:
On 2014-09-24 09:34, Bill Sloman wrote:
On 24/09/2014 4:52 PM, Jeroen Belleman wrote:
On 2014-09-24 08:29, rickman wrote:
On 9/24/2014 1:52 AM, Bill Sloman wrote:
On Wednesday, 24 September 2014 13:51:19 UTC+10, rickman wrote:
On 9/23/2014 11:28 PM, Bill Sloman wrote:
On Tuesday, 23 September 2014 22:48:02 UTC+10, dagmarg...@yahoo.com
wrote:
On Monday, September 22, 2014 9:53:47 PM UTC-4, Bill Sloman wrote:
On Tuesday, 23 September 2014 10:48:11 UTC+10,
dagmarg...@yahoo.com
wrote:

snip


The DAC and the following low-pass are there only to smooth out the
6.4ns cycle-to-cyle variations of the 10MHz DDS output. I don't see
why one would bother with a DAC at all. Just use the MSB of the phase
accumulator and let the loop filter do the filtering. No more drifty
analog filters in the critical path.

I think the issue here is the phase-to-voltage linearity of the phase
detector. Fractional-n puts up to 6.4nsec - typically about 3nsec -
phase excursions on pretty much every clock edge, and you want them to
cancel out - to sub-picoscend accuracy over the 12.5usec it takes the
cycle to repeat.

DDS offers a much better approximation to a 10MHz sine wave going into
the phase detector and puts a correspondingly lower demand on it's
linearity.

John Larkin is infatuated with his - totally non-linear - edge driven
bang-bang phase detector, so fractional-n doesn't get a look-in.

If you tweak the NCO to make the MSB a 50% duty cycle square wave
on average, you can pipe it straight into a DB mixer with your
sine-wave 10MHz reference at the other input to make the phase
error signal.

Tricky. The fractional-N approximation from a 155.52MHz clock to a 10MHz
output is 56 15-cycle segments and 69 16 cycle segments, which cycles at
80kHz.

You can split the 16 cycle segments into 8+8 but the 15 cycle ones are
7+8.

The crudest way of getting there is a 250 entry look-up table - 194
divide by eight and 56 divide by seven. You end up with 30 three divides
by eight followed by one divide by seven, plus 26 four divides by eight
followed by one divide by seven.


I haven't worked out the details, but I might try to make an NCO with
a phase accumulator constrained to values between -972 to 971 when
interpreted as a signed 2's-complement number. Add 125 on each beat
of the 155.52MHz clock and the sign bit ends up a fair approximation
of a 50% duty cycle square at exactly 10MHz on average, with the phase
error pattern repeating every 12.5us. That's an FPGA job, of course.
Reclock the sign bit using an ECL FF clocked with the original clean
155.52MHz to remove FPGA-induced vagaries.

Removing the cycle-to-cycle phase variations is the loop filter's
job. They average out over 12.5us.

Of course logic is cheap in an FPGA so such a counter is not a big deal
to implement. But it can be smaller/faster to use a phase accumulator
that ranges between 0 and 971 followed by a divide by two FF to make the
square wave. Rather than use the MSB, make it a subtractor so that the
carry out is your flag to both reload the accumulator with the adjusted
value for the modulus and to toggle the square wave FF.

[...]

You're right that would work, except that you don't ever
reload the phase accumulator. Instead, you'd add 847 every time
subtracting 125 would make it go negative, and toggle the output
FF at each such occurrence. I suppose that's what you mean by
'reloading the adjusted value for the modulus'. Either way, it
still 11 FFs and it makes no difference for the cycle-to-cycle
phase errors. It's still a pattern that repeats every 12.5us.

Jeroen Belleman

 

[John Larkin]

On Wed, 24 Sep 2014 14:15:33 +0200, Jeroen Belleman
<jeroen@nospam.please> wrote:

On 2014-09-24 13:09, rickman wrote:
On 9/24/2014 4:55 AM, Jeroen Belleman wrote:
On 2014-09-24 09:34, Bill Sloman wrote:
On 24/09/2014 4:52 PM, Jeroen Belleman wrote:
On 2014-09-24 08:29, rickman wrote:
On 9/24/2014 1:52 AM, Bill Sloman wrote:
On Wednesday, 24 September 2014 13:51:19 UTC+10, rickman wrote:
On 9/23/2014 11:28 PM, Bill Sloman wrote:
On Tuesday, 23 September 2014 22:48:02 UTC+10, dagmarg...@yahoo.com
wrote:
On Monday, September 22, 2014 9:53:47 PM UTC-4, Bill Sloman wrote:
On Tuesday, 23 September 2014 10:48:11 UTC+10,
dagmarg...@yahoo.com
wrote:

snip


The DAC and the following low-pass are there only to smooth out the
6.4ns cycle-to-cyle variations of the 10MHz DDS output. I don't see
why one would bother with a DAC at all. Just use the MSB of the phase
accumulator and let the loop filter do the filtering. No more drifty
analog filters in the critical path.

I think the issue here is the phase-to-voltage linearity of the phase
detector. Fractional-n puts up to 6.4nsec - typically about 3nsec -
phase excursions on pretty much every clock edge, and you want them to
cancel out - to sub-picoscend accuracy over the 12.5usec it takes the
cycle to repeat.

DDS offers a much better approximation to a 10MHz sine wave going into
the phase detector and puts a correspondingly lower demand on it's
linearity.

John Larkin is infatuated with his - totally non-linear - edge driven
bang-bang phase detector, so fractional-n doesn't get a look-in.

If you tweak the NCO to make the MSB a 50% duty cycle square wave
on average, you can pipe it straight into a DB mixer with your
sine-wave 10MHz reference at the other input to make the phase
error signal.

Tricky. The fractional-N approximation from a 155.52MHz clock to a 10MHz
output is 56 15-cycle segments and 69 16 cycle segments, which cycles at
80kHz.

You can split the 16 cycle segments into 8+8 but the 15 cycle ones are
7+8.

The crudest way of getting there is a 250 entry look-up table - 194
divide by eight and 56 divide by seven. You end up with 30 three divides
by eight followed by one divide by seven, plus 26 four divides by eight
followed by one divide by seven.


I haven't worked out the details, but I might try to make an NCO with
a phase accumulator constrained to values between -972 to 971 when
interpreted as a signed 2's-complement number. Add 125 on each beat
of the 155.52MHz clock and the sign bit ends up a fair approximation
of a 50% duty cycle square at exactly 10MHz on average, with the phase
error pattern repeating every 12.5us. That's an FPGA job, of course.
Reclock the sign bit using an ECL FF clocked with the original clean
155.52MHz to remove FPGA-induced vagaries.

Removing the cycle-to-cycle phase variations is the loop filter's
job. They average out over 12.5us.

Of course logic is cheap in an FPGA so such a counter is not a big deal
to implement. But it can be smaller/faster to use a phase accumulator
that ranges between 0 and 971 followed by a divide by two FF to make the
square wave. Rather than use the MSB, make it a subtractor so that the
carry out is your flag to both reload the accumulator with the adjusted
value for the modulus and to toggle the square wave FF.

[...]

You're right that would work, except that you don't ever
reload the phase accumulator. Instead, you'd add 847 every time
subtracting 125 would make it go negative, and toggle the output
FF at each such occurrence. I suppose that's what you mean by
'reloading the adjusted value for the modulus'. Either way, it
still 11 FFs and it makes no difference for the cycle-to-cycle
phase errors. It's still a pattern that repeats every 12.5us.

Jeroen Belleman

Right. What Sloman described isn't a DDS, it's an elaborate,
expensive, drifty, noisy divide-by-1944, and the phase comparison
would still be at 80 KHz.

So, why not just divide by 1944?


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Michael A. Terrell]

krw@attt.bizz wrote:

On Sun, 21 Sep 2014 11:10:12 -0400, "Maynard A. Philbrook Jr."
jamie_ka1lpa@charter.net> wrote:

In article <loot1a9ud84ef4h6jasi66ngiv337scr95@4ax.com>, krw@attt.bizz
says...
the truth.

The real-world translation is "sane person".

You've never looked at one in the mirror, that's certain.

One doesn't need to know much about the
USA to realise that the TEA Party are bunch of political lemmings trying
to make a society that is moving the wrong way - becoming even more inegalitarian - even more dysfunctional.

More lies but nothing new.

Krw again congratulates me on being saner than he is - not a
particularly ringing endorsement, since even Jamie qualifies for it.

Once again, you prove my point. You *are* incapable of telling the
truth.



In Bill's case, the truth has to be known before it can be told.

He's been told the truth often enough but keeps spouting the same
lies. That pushes it out of the ignorance realm.

In other words, he's just a lame troll that people keep feeding.


--
Anyone wanting to run for any political office in the US should have to
have a DD214, and a honorable discharge.

 

[John Larkin]

On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin
<jlarkin@highlandtechnology.com> wrote:

If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.

Cool. 523 posts to this thread so far.

This might work:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/PLL_Series_Gate.JPG

It still does the phase compare at 80 KHz, probably a mathematical
necessity in my situation. But the phase detector gain is way higher
than a classical 2-pi phase detector... 1944 times as high, to be
exact. Picoseconds of phase error now become parts-per-thousand turf,
not parts per million.

The advantage over a bangbang detector is that the phase detector
output is linear on phase error, so the loop could be analyzed as
such, and will be far less noisy.

That 6 ns series gate, stable to around 0.1%, is non-trivial.

Ooh, that suggests a phase ADC, in a digital loop. Or maybe a multbit
bang-bang phase detector. Maybe later.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Bill Sloman]

On 25/09/2014 12:23 AM, John Larkin wrote:

On Wed, 24 Sep 2014 14:15:33 +0200, Jeroen Belleman
jeroen@nospam.please> wrote:

On 2014-09-24 13:09, rickman wrote:
On 9/24/2014 4:55 AM, Jeroen Belleman wrote:
On 2014-09-24 09:34, Bill Sloman wrote:
On 24/09/2014 4:52 PM, Jeroen Belleman wrote:
On 2014-09-24 08:29, rickman wrote:
On 9/24/2014 1:52 AM, Bill Sloman wrote:
On Wednesday, 24 September 2014 13:51:19 UTC+10, rickman wrote:
On 9/23/2014 11:28 PM, Bill Sloman wrote:
On Tuesday, 23 September 2014 22:48:02 UTC+10, dagmarg...@yahoo.com
wrote:
On Monday, September 22, 2014 9:53:47 PM UTC-4, Bill Sloman wrote:
On Tuesday, 23 September 2014 10:48:11 UTC+10,
dagmarg...@yahoo.com
wrote:

<snip>

Right. What Sloman described isn't a DDS, it's an elaborate,
expensive, drifty, noisy divide-by-1944, and the phase comparison
would still be at 80 KHz.

Wrong - on several counts. The main point is that that with either
fractional-n or DDS you derive a nominally 10MHz waveform from your
155.52MHz VCXO and do the phase comparison at 10MHz rather than 80kHz.

In neither case is the derived 10MHz waveform perfectly regular - the
DDS approach gives you something much closer to perfection than the
fractional-n approach and you pretty much have to use a product-type
phase detector, carefully analog-designed to give you a tolerably linear
phase-offset to voltage-out relationship, so that the residual
imperfections average out over the 80kHz cycle over which they repeat.

The DDS approach does involve more propagation delay in the path from
the 155.52MHz clock signal to the derived 10MHz waveform. It may strike
you as an elaborate approach, but I do seem to have worked with more
complicated systems than you, and it doesn't strike me as all that
complicated.

It needn't be all that drifty or noisy. The fractional-n approach is
simpler and involves smaller propagation delays, and while the
individual edges on the derived 10MHz do gad around more - up to 6.4nsec
- the deviations aren't random noise but systematic and entirely
predictable excursions.

> So, why not just divide by 1944?

For the reason you set out when you opened this thread - getting
information on the relative phase of the two waveforms at 80kHz rather
than 10MHz makes the system more susceptible to random noise in the
phase-detector. Using a thoroughly non-linear bang-bang phase detector
to do it makes the situation somewhat worse.

--
Bill Sloman, Sydney

 

[Jan Panteltje]

On a sunny day (Wed, 24 Sep 2014 08:01:46 -0700) it happened John Larkin
<jlarkin@highlandtechnology.com> wrote in
<ghm52ahcpfnjhcm82cpj6barsorjh8e187@4ax.com>:

On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin
jlarkin@highlandtechnology.com> wrote:



If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.


Cool. 523 posts to this thread so far.

This might work:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/PLL_Series_Gate.JPG

Yes John, I invented that back in 1984
http://panteltje.com/panteltje/z80/system14/diagrams/fdc-2.jpg
and discussed it here in detail too.

 

[John Larkin]

On Wed, 24 Sep 2014 15:29:56 GMT, Jan Panteltje <panteltje@yahoo.com>
wrote:

On a sunny day (Wed, 24 Sep 2014 08:01:46 -0700) it happened John Larkin
jlarkin@highlandtechnology.com> wrote in
ghm52ahcpfnjhcm82cpj6barsorjh8e187@4ax.com>:

On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin
jlarkin@highlandtechnology.com> wrote:



If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.


Cool. 523 posts to this thread so far.

This might work:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/PLL_Series_Gate.JPG

Yes John, I invented that back in 1984
http://panteltje.com/panteltje/z80/system14/diagrams/fdc-2.jpg
and discussed it here in detail too.

I suspect someone else invented it before either of us. I invented the
bang-bang phase detector ca 1972, ditto.

The trick would be to make that series switch work with roughly 0.1%
precision, given a 6 ns gate.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Phil Hobbs]

On 09/24/2014 11:01 AM, John Larkin wrote:

On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin
jlarkin@highlandtechnology.com> wrote:



If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.


Cool. 523 posts to this thread so far.

This might work:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/PLL_Series_Gate.JPG

It still does the phase compare at 80 KHz, probably a mathematical
necessity in my situation. But the phase detector gain is way higher
than a classical 2-pi phase detector... 1944 times as high, to be
exact. Picoseconds of phase error now become parts-per-thousand turf,
not parts per million.

The advantage over a bangbang detector is that the phase detector
output is linear on phase error, so the loop could be analyzed as
such, and will be far less noisy.

That 6 ns series gate, stable to around 0.1%, is non-trivial.

Ooh, that suggests a phase ADC, in a digital loop. Or maybe a multbit
bang-bang phase detector. Maybe later.

Phase digitizers are fun. I did one as a grad student, back around
1986--it ran at 60 MHz, 50k samples/s, and was good to 13 bits over a
cycle. It used an old-fashioned SAR chip plus DAC plus varactor phase
shifter, with a Mini Circuits RPD-1 phase detector. (It was one of the
two instruments papers I ever published.)
(*)
1 LSB of that digitizer was about 2 picoseconds--I learned the horrible
truth about picosecond stability and bending coax cables.

The stability of just the digitizer and its associated calibrator (which
was several times more complicated) was about +- 0.05 degrees over a few
hours, which is about +- 2 ps.

Cheers

Phil Hobbs



Hobbs, P. C. D., "High‐performance amplitude and phase digitizers at 60
MHz", Rev. Sci. Instrum. 58, 1518 (1987)

I don't think I have a copy any place, or I'd post a link.
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Phil Hobbs]

On 09/24/2014 01:32 PM, John Larkin wrote:

On Wed, 24 Sep 2014 15:29:56 GMT, Jan Panteltje <panteltje@yahoo.com
wrote:

On a sunny day (Wed, 24 Sep 2014 08:01:46 -0700) it happened John Larkin
jlarkin@highlandtechnology.com> wrote in
ghm52ahcpfnjhcm82cpj6barsorjh8e187@4ax.com>:

On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin
jlarkin@highlandtechnology.com> wrote:



If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.


Cool. 523 posts to this thread so far.

This might work:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/PLL_Series_Gate.JPG

Yes John, I invented that back in 1984
http://panteltje.com/panteltje/z80/system14/diagrams/fdc-2.jpg
and discussed it here in detail too.


I suspect someone else invented it before either of us. I invented the
bang-bang phase detector ca 1972, ditto.

The trick would be to make that series switch work with roughly 0.1%
precision, given a 6 ns gate.

Or at least make its imprecision symmetrical, e.g. with a 2-diode series
clipper.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[rickman]

On 9/24/2014 8:15 AM, Jeroen Belleman wrote:

On 2014-09-24 13:09, rickman wrote:
On 9/24/2014 4:55 AM, Jeroen Belleman wrote:
On 2014-09-24 09:34, Bill Sloman wrote:
On 24/09/2014 4:52 PM, Jeroen Belleman wrote:
On 2014-09-24 08:29, rickman wrote:
On 9/24/2014 1:52 AM, Bill Sloman wrote:
On Wednesday, 24 September 2014 13:51:19 UTC+10, rickman wrote:
On 9/23/2014 11:28 PM, Bill Sloman wrote:
On Tuesday, 23 September 2014 22:48:02 UTC+10,
dagmarg...@yahoo.com
wrote:
On Monday, September 22, 2014 9:53:47 PM UTC-4, Bill Sloman
wrote:
On Tuesday, 23 September 2014 10:48:11 UTC+10,
dagmarg...@yahoo.com
wrote:

snip


The DAC and the following low-pass are there only to smooth out the
6.4ns cycle-to-cyle variations of the 10MHz DDS output. I don't see
why one would bother with a DAC at all. Just use the MSB of the phase
accumulator and let the loop filter do the filtering. No more drifty
analog filters in the critical path.

I think the issue here is the phase-to-voltage linearity of the phase
detector. Fractional-n puts up to 6.4nsec - typically about 3nsec -
phase excursions on pretty much every clock edge, and you want them to
cancel out - to sub-picoscend accuracy over the 12.5usec it takes the
cycle to repeat.

DDS offers a much better approximation to a 10MHz sine wave going into
the phase detector and puts a correspondingly lower demand on it's
linearity.

John Larkin is infatuated with his - totally non-linear - edge driven
bang-bang phase detector, so fractional-n doesn't get a look-in.

If you tweak the NCO to make the MSB a 50% duty cycle square wave
on average, you can pipe it straight into a DB mixer with your
sine-wave 10MHz reference at the other input to make the phase
error signal.

Tricky. The fractional-N approximation from a 155.52MHz clock to a
10MHz
output is 56 15-cycle segments and 69 16 cycle segments, which
cycles at
80kHz.

You can split the 16 cycle segments into 8+8 but the 15 cycle ones are
7+8.

The crudest way of getting there is a 250 entry look-up table - 194
divide by eight and 56 divide by seven. You end up with 30 three
divides
by eight followed by one divide by seven, plus 26 four divides by eight
followed by one divide by seven.


I haven't worked out the details, but I might try to make an NCO with
a phase accumulator constrained to values between -972 to 971 when
interpreted as a signed 2's-complement number. Add 125 on each beat
of the 155.52MHz clock and the sign bit ends up a fair approximation
of a 50% duty cycle square at exactly 10MHz on average, with the phase
error pattern repeating every 12.5us. That's an FPGA job, of course.
Reclock the sign bit using an ECL FF clocked with the original clean
155.52MHz to remove FPGA-induced vagaries.

Removing the cycle-to-cycle phase variations is the loop filter's
job. They average out over 12.5us.

Of course logic is cheap in an FPGA so such a counter is not a big deal
to implement. But it can be smaller/faster to use a phase accumulator
that ranges between 0 and 971 followed by a divide by two FF to make the
square wave. Rather than use the MSB, make it a subtractor so that the
carry out is your flag to both reload the accumulator with the adjusted
value for the modulus and to toggle the square wave FF.

[...]

You're right that would work, except that you don't ever
reload the phase accumulator. Instead, you'd add 847 every time
subtracting 125 would make it go negative, and toggle the output
FF at each such occurrence. I suppose that's what you mean by
'reloading the adjusted value for the modulus'. Either way, it
still 11 FFs and it makes no difference for the cycle-to-cycle
phase errors. It's still a pattern that repeats every 12.5us.

Adding 847 and subtracting 177 are the same modulo 1024. The number of
FFs is not the issue. The number of adders and multiplexers and where
they are placed is the issue. If this is coded in a sloppy manner it
can produce more logic than is needed.

--

Rick

 

[rickman]

On 9/24/2014 10:23 AM, John Larkin wrote:

On Wed, 24 Sep 2014 14:15:33 +0200, Jeroen Belleman
jeroen@nospam.please> wrote:

On 2014-09-24 13:09, rickman wrote:
On 9/24/2014 4:55 AM, Jeroen Belleman wrote:
On 2014-09-24 09:34, Bill Sloman wrote:
On 24/09/2014 4:52 PM, Jeroen Belleman wrote:
On 2014-09-24 08:29, rickman wrote:
On 9/24/2014 1:52 AM, Bill Sloman wrote:
On Wednesday, 24 September 2014 13:51:19 UTC+10, rickman wrote:
On 9/23/2014 11:28 PM, Bill Sloman wrote:
On Tuesday, 23 September 2014 22:48:02 UTC+10, dagmarg...@yahoo.com
wrote:
On Monday, September 22, 2014 9:53:47 PM UTC-4, Bill Sloman wrote:
On Tuesday, 23 September 2014 10:48:11 UTC+10,
dagmarg...@yahoo.com
wrote:

snip


The DAC and the following low-pass are there only to smooth out the
6.4ns cycle-to-cyle variations of the 10MHz DDS output. I don't see
why one would bother with a DAC at all. Just use the MSB of the phase
accumulator and let the loop filter do the filtering. No more drifty
analog filters in the critical path.

I think the issue here is the phase-to-voltage linearity of the phase
detector. Fractional-n puts up to 6.4nsec - typically about 3nsec -
phase excursions on pretty much every clock edge, and you want them to
cancel out - to sub-picoscend accuracy over the 12.5usec it takes the
cycle to repeat.

DDS offers a much better approximation to a 10MHz sine wave going into
the phase detector and puts a correspondingly lower demand on it's
linearity.

John Larkin is infatuated with his - totally non-linear - edge driven
bang-bang phase detector, so fractional-n doesn't get a look-in.

If you tweak the NCO to make the MSB a 50% duty cycle square wave
on average, you can pipe it straight into a DB mixer with your
sine-wave 10MHz reference at the other input to make the phase
error signal.

Tricky. The fractional-N approximation from a 155.52MHz clock to a 10MHz
output is 56 15-cycle segments and 69 16 cycle segments, which cycles at
80kHz.

You can split the 16 cycle segments into 8+8 but the 15 cycle ones are
7+8.

The crudest way of getting there is a 250 entry look-up table - 194
divide by eight and 56 divide by seven. You end up with 30 three divides
by eight followed by one divide by seven, plus 26 four divides by eight
followed by one divide by seven.


I haven't worked out the details, but I might try to make an NCO with
a phase accumulator constrained to values between -972 to 971 when
interpreted as a signed 2's-complement number. Add 125 on each beat
of the 155.52MHz clock and the sign bit ends up a fair approximation
of a 50% duty cycle square at exactly 10MHz on average, with the phase
error pattern repeating every 12.5us. That's an FPGA job, of course.
Reclock the sign bit using an ECL FF clocked with the original clean
155.52MHz to remove FPGA-induced vagaries.

Removing the cycle-to-cycle phase variations is the loop filter's
job. They average out over 12.5us.

Of course logic is cheap in an FPGA so such a counter is not a big deal
to implement. But it can be smaller/faster to use a phase accumulator
that ranges between 0 and 971 followed by a divide by two FF to make the
square wave. Rather than use the MSB, make it a subtractor so that the
carry out is your flag to both reload the accumulator with the adjusted
value for the modulus and to toggle the square wave FF.

[...]

You're right that would work, except that you don't ever
reload the phase accumulator. Instead, you'd add 847 every time
subtracting 125 would make it go negative, and toggle the output
FF at each such occurrence. I suppose that's what you mean by
'reloading the adjusted value for the modulus'. Either way, it
still 11 FFs and it makes no difference for the cycle-to-cycle
phase errors. It's still a pattern that repeats every 12.5us.

Jeroen Belleman

Right. What Sloman described isn't a DDS, it's an elaborate,
expensive, drifty, noisy divide-by-1944, and the phase comparison
would still be at 80 KHz.

So, why not just divide by 1944?

Uh, it's not dividing by 1944... It is producing 10 MHz, not 80 kHz.
Did you actually read any of this?

--

Rick

 

[Bill Sloman]

On Thursday, 25 September 2014 00:54:50 UTC+10, Michael Terrell wrote:

krw@attt.bizz wrote:
On Sun, 21 Sep 2014 11:10:12 -0400, "Maynard A. Philbrook Jr."
jamie_ka1lpa@charter.net> wrote:
In article <loot1a9ud84ef4h6jasi66ngiv337scr95@4ax.com>, krw@attt.bizz
says...

<there was the usual large unmarked snip here>

the truth.

The real-world translation is "sane person".

You've never looked at one in the mirror, that's certain.

One doesn't need to know much about the USA to realise that the Tea Party are bunch of political lemmings trying to make a society that is moving the wrong way - becoming even more inegalitarian - even more dysfunctional.

More lies but nothing new.

Krw again congratulates me on being saner than he is - not a
particularly ringing endorsement, since even Jamie qualifies for it.

Once again, you prove my point. You *are* incapable of telling the
truth.

Krw confuses "what he knows" with "the truth".

In Bill's case, the truth has to be known before it can be told.

He's been told the truth often enough but keeps spouting the same lies.. That pushes it out of the ignorance realm.

Sadly, the ignorance here is all krw's. Unsurprising really - he has a remarkably generous supply of ignorance.

> In other words, he's just a lame troll that people keep feeding.

If Michael Terrell knew anything worthwhile about electronic circuit design, he'd be aware that most of my contributions to this - overly long - thread are distinctly above the "lame troll" level.

We seem to have finally persuaded John Larkin that his D-flip-flop-based bang-bang phase detector is probably sub-optimal for his particular application, but he still can't see the point of using DDS or fractional-n to generate an imperfect 10MHz waveform from his 155.52MHz VCXO so that he can measure phase at 10MHz rather than at 80kHz - you've got to measure and average 12.5usec's worth (1944)of phase comparisons before you can rely on the result, but that does shrink the random noise from each phase detection by the square root of 1944 (44.1). I've been banging on about this point since I first posted to this thread, on the 10th September 2014. I didn't start beating the drum about the superiority of the linear phase detector (as opposed to the bang-bang phase detector) until the following day, when John Larkin's irrational preference for the bang-bang detector had become more obvious..

My own appreciation of what the circuit does - and has to do - has also improved as we've gone on, which is not "lame troll" behaviour.

But Mike doesn't really appreciate what's been being discussed, so he's probably missed that.

--
Bill Sloman, Sydney

 

[Bill Sloman]

On Thursday, 25 September 2014 12:40:51 UTC+10, John Larkin wrote:

On Wed, 24 Sep 2014 14:08:52 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:
On 09/24/2014 11:01 AM, John Larkin wrote:
On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin
jlarkin@highlandtechnology.com> wrote:

If I shaped the rising edge of the 10 MHz square wave, and digitized
that with a wideband ADC triggered at 80 KHz, I'd get an ADC code that
was about linear on phase error with full-span of 50 ps or some such.
Even 8 bits would get the LSB into the sub-ps range. Then do a digital
PID loop driving a DAC into the VCO input. I do something vaguely
similar in my DDGs.

Even more radical, digitize the 10 MHz sine wave at 155.52 MHz sample
rate and do a monstrous amount of math.

That would be a huge waste of resources. Use the fractional-n approach to digitise at 20MHz, using the nearest 155.52MHz edge after the rising and falling 10MHz edges. You'll be able to predict how much later the digitisation ought to be happening, and interpret the ADC output as an exact - linear - time delay correction. You'd have to shape the 10MHz edges enough to give you something worth digitising up to 6.43nsec - probably actually closer to 12.86nsec - after the start of the 10MHz edge transition.

That does insert something like 7nsec of analog delay/time constant into your sampling path, and you'd have to do careful analog design to keep the temperature drift on that below a picosecond or so.

Multibit bang-bang would use several flops staggered in time to make a
thermometer code of phase shift. That would improve my loop noise a
little.

That does imply a precise and stable tapped delay line for the multiple D-type flip-flops to sample - all at once - at 80kHz. If you made the delay line longer than 6.44 nsec, you could use fractional-n division to let it sample at 10MHz but you'd then have to take out the predictable - up to 6.44nsec - excursions - on the non-coincident edges .

> Single flop bang-bang is looking pretty good!

Self-delusion.

--
Bill Sloman, Sydney

 

[Ralph Barone]

Phil Hobbs <hobbs@electrooptical.net> wrote:

On 9/22/2014 11:54 PM, mroberds@att.net wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den fredag den 19. september 2014 16.11.10 UTC+2 skrev dagmarg...@yahoo.com:
On Friday, September 12, 2014 9:18:41 PM UTC-4, mrob...@att.net wrote:

Sort of related: European starlings (Sturnus vulgaris) develop about
10 to 15 W of metabolic power, and deliver about 1 to 2.5 W at the
wings.

Pretty neat that a 100g critter makes 15W.

I liked the idea that if you have the amount of power that comes out of
a standard USB port, you can fly.

If you have a hub, you can power 100,000 mosquitoes.

Cheers

Phil Hobbs

If I have 100,000 mosquitos, can I use them to charge my phone?

 

[rickman]

On 9/24/2014 8:41 PM, Ralph Barone wrote:

Phil Hobbs <hobbs@electrooptical.net> wrote:
On 9/22/2014 11:54 PM, mroberds@att.net wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den fredag den 19. september 2014 16.11.10 UTC+2 skrev dagmarg...@yahoo.com:
On Friday, September 12, 2014 9:18:41 PM UTC-4, mrob...@att.net wrote:

Sort of related: European starlings (Sturnus vulgaris) develop about
10 to 15 W of metabolic power, and deliver about 1 to 2.5 W at the
wings.

Pretty neat that a 100g critter makes 15W.

I liked the idea that if you have the amount of power that comes out of
a standard USB port, you can fly.

If you have a hub, you can power 100,000 mosquitoes.

Cheers

Phil Hobbs


If I have 100,000 mosquitos, can I use them to charge my phone?

Sure, do you have the appropriate adapter cable? I bet you can find one
on AliExpress...

--

Rick

 

[Bill Sloman]

On 25/09/2014 1:01 AM, John Larkin wrote:

On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin
jlarkin@highlandtechnology.com> wrote:



If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.


Cool. 523 posts to this thread so far.

This might work:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/PLL_Series_Gate.JPG

It still does the phase compare at 80 KHz, probably a mathematical
necessity in my situation. But the phase detector gain is way higher
than a classical 2-pi phase detector... 1944 times as high, to be
exact. Picoseconds of phase error now become parts-per-thousand turf,
not parts per million.

The advantage over a bangbang detector is that the phase detector
output is linear on phase error, so the loop could be analyzed as
such, and will be far less noisy.

That 6 ns series gate, stable to around 0.1%, is non-trivial.

Ooh, that suggests a phase ADC, in a digital loop. Or maybe a multbit
bang-bang phase detector. Maybe later.

A second 6.4nsec series gate, looking at the inverted 10MHz reference,
972 cycles of the 155.52MHz clock later, could give you twice a many
edges per per unit time.

Or you could use an identical series gate looking at the same waveform,
but feeding into the opposite sense input of a differential integrator
to get the same advantage - two switches in either case.

Since ECL transmission gates typically generate almost perfectly
complementary outputs, the first approach would be the way to go.

The approach is incompatible with DDS, but using fractional-n to
generate a lot of close-enough gating pulses around all - or just a lot
of - the edges of the 10MHz clock would generate more data, albeit with
systematic noise which would exactly cancel over any 12.5usec period and
could be low-pass filtered to very low levels at the 500Hz output
bandwidth desired.

The capacitor without the series resistor in the drop-box diagram would
be of the order of a couple of pF, around the input capacitance of the
op amp chosen to realise the integrator.

--
Bill Sloman, Sydney