PLL tricks

[Jan Panteltje]

On a sunny day (Mon, 22 Sep 2014 17:48:11 -0700 (PDT)) it happened
dagmargoodboat@yahoo.com wrote in
<7d59822e-1992-4947-b82f-937ff5c53788@googlegroups.com>:

>If you mix 10Mhz and 155.52MHz sines directly, the result is an unfilterable mess.

Just use the sum or difference, easy to filter.
Either 165.52 or 145.52 MHz
Any ol' radio does that.

 

On Monday, September 22, 2014 1:29:26 PM UTC-4, Kevin Aylward wrote:

dagmarg...@yahoo.com wrote:

This ovenized VCXO specs -188dBc/Hz @ 100KHz, and -108dBc/Hz @ 10Hz offset:
http://www.wenzel.com/wp-content/parts/501-25900.pdf

When ever I see really low noise, its a given that it uses lots of volts.
You need the voltage swing to override circuit noise. My stuff is pretty
much restricted to below 5V, with 3.3 being the main stay.

You're serving a very valuable application area. Lots of people don't have
15v supplies and 8 peak watts to burn, or space for a big metal brick to
call home.

This means 2.8V
internal as everything is regulated. External power supplies are way too
noisy. In fact, my BG has 20 times less supply current for the same noise
offered by the likes of Linear Tech, Maxim, Analog Devices etc.

Classy.

All
other defects corrected by throwing transistors at it.

That makes sense. I was quite interested in doing the same nearly 20 years
ago, adding a uC to a VCXO for all those benefits. That's why I collected
a lot of oscillator / crystal literature.

Digital control is a bit tricky, especially for the heated few ppb
oscillators. 1 ppb steps would be way to large, so its usually all smooth
analog

My notion was ramp-and-hold stuff, which should have been somewhat clean.
I was mostly after 1ppm or 0.5ppm over temperature for an spread spectrum
transmitter, not ultimate world-besting performance.

They were making millions of something I designed, and an upgraded crystal
would've made possible a large improvement.

I realized I'd be in the oscillator-making business then though, which
wasn't
what I really wanted to do the rest of my life.

I got into it by default. The only reasonable option near to where I lived,
when I anticipated the current job at the then current employer was not
going to last.

I don't intend to stay in oscillators...

Nothing wrong with it, not at all. You've done some very nice work.
I just realized at the time that I didn't own an oscillator company and
didn't feel like starting one.

Doing the same work, working *for an oscillator company* would've been
completely different (and lots of fun).

Small world, isn't it?

Indeed.

Cheers,

James Arthur

 

On Tuesday, September 23, 2014 4:22:19 AM UTC-4, Jan Panteltje wrote:

On a sunny day (Mon, 22 Sep 2014 17:48:11 -0700 (PDT)) it happened
dagmargoo...@yahoo.com wrote:

If you mix 10Mhz and 155.52MHz sines directly, the result is an unfilterable mess.

Just use the sum or difference, easy to filter.

Either 165.52 or 145.52 MHz

Any ol' radio does that.

1. Not to ppb.
2. We're trying to extract an 80KHz phase signal / beat frequency.

Or, more specifically, to fix the 155.52 MHz phase in place,
at 15.552 000 00 cycles per 10MHz cycle, to a few pS over some
undefined time interval.

Cheers,
James Arthur

 

On Monday, September 22, 2014 9:53:47 PM UTC-4, Bill Sloman wrote:

On Tuesday, 23 September 2014 10:48:11 UTC+10, dagmarg...@yahoo.com wrote:

The DDS in the signal path adds a horrendous, variable delay, loads of
transistors in the signal path, and no control over how clean the
supplies and signals are. I don't see how the DDS' wandering analog
output delay can be re-sync'd to the reference clock, something the
bang-bang can do with a single flop.

The DDS would use the 155.52MHz source to clock the DAC producing the stair-case approximation to the desired 10MHz waveform.

That's not any kind of "horrendous variable delay" and there are very few transistors in that signal path. And you've got total control over rails feeding the DDS chip. The DDS doesn't have any kind of "wandering analog output delay".

AIUI the object is to stabilize the phase of the 155.52MHz output to ~10ppm
w.r.t. a precision 10MHz reference signal.

When you insert the DDS between the output signal and the phase comparison,
you've added an uncalibrated delay that cannot be removed, ditto any noise
or jitter produced in the DDS, that's my point.

Cheers,
James Arthur

 

[Bill Sloman]

On Tuesday, 23 September 2014 22:48:02 UTC+10, dagmarg...@yahoo.com wrote:

On Monday, September 22, 2014 9:53:47 PM UTC-4, Bill Sloman wrote:

On Tuesday, 23 September 2014 10:48:11 UTC+10, dagmarg...@yahoo.com wrote:

The DDS in the signal path adds a horrendous, variable delay, loads of
transistors in the signal path, and no control over how clean the
supplies and signals are. I don't see how the DDS' wandering analog
output delay can be re-sync'd to the reference clock, something the
bang-bang can do with a single flop.

The DDS would use the 155.52MHz source to clock the DAC producing the stair-case approximation to the desired 10MHz waveform.

That's not any kind of "horrendous variable delay" and there are very few transistors in that signal path. And you've got total control over rails feeding the DDS chip. The DDS doesn't have any kind of "wandering analog output delay".

AIUI the object is to stabilize the phase of the 155.52MHz output to ~10ppm
w.r.t. a precision 10MHz reference signal.

Of course. John Larkin spelled this out - initially a little less than perfectly clearly - when he started this thread, and he's clarified exactly what he wants to do in considerable detail since then.

When you insert the DDS between the output signal and the phase comparison,
you've added an uncalibrated delay that cannot be removed, ditto any noise
or jitter produced in the DDS, that's my point.

It's a delay you could calibrate. I was looking at the Analog Devices AD9913, as the cheapest AD DDS that can be clocked at 155.52MHz and it is true that they don't specify a propagation delay from pins 13 and 14 - Ref_Clock and complement_Ref_Clock - to the DAC output edges.

http://www.analog.com/static/imported-files/data_sheets/AD9913.pdf

If one dug around a bit deeper, one might find a better specified part, but - as has been repeatedly mentioned here - you can always put the DDS logic into a programmable logic part and clock your own DAC with a suitably precise clock derived directly from the 155.52 MHz VCXO source.

Back when I was directly interested, all the best fast DAC's relied on ECL logic levels at all the digital inputs, because it provided a much cleaner analog environment for the analog side of the device.

So it may be an objection to a particular DDS chip, but it's not an objection to using DDS to generate 10MHz from the 155.52 MHz clock output.

And if you are using a product phase detector - either a multiplier or full-wave switching phase detector - you can do almost as well with a fractional-n approximation to your 10MHz output - basically alternating dividing 155..52MHz by 15 almost half the time - 59 out of 125 cycles - and by 16 the rest of the time 69 out of 125 cycles. The phase is out by up to 6.4nsec in 100nsec on each cycle, but averages to exactly zero error over 125 cycles. With a respectably linear phase detector this will be systematic noise at 80KHz and above that can be low-pass filtered out to very little indeed at the 500Hz PLL output bandwidth that John says he wants.

The DDS approach would generate a whole lot less phase noise in the first place, but it is more complicated - though a lot less messy than you seem to think.

John enthusiasm for using a non-linear bang-bang phase detector rather limits his option. I thinks it's actually a very bad approach for his particular problem.

--
Bill Sloman, Sydney

 

[Jan Panteltje]

On a sunny day (Tue, 23 Sep 2014 05:02:56 -0700 (PDT)) it happened
dagmargoodboat@yahoo.com wrote in
<f4622486-63f5-46df-bd87-8be80ab63dc7@googlegroups.com>:

On Monday, September 22, 2014 11:46:54 AM UTC-4, Jan Panteltje wrote:
dagmargoo...@yahoo.com wrote:


I would've thought the "Ea" parts are the mixers, diode quads. The filters
are nicely realized on the PCB, and I'd have guessed the right-top chip
you mentioned is an output amplifier.

No, look at this:

http://www.juras-projects.org/files/lumax_lx-lst40.png

Ahh, multiple input amps--a diversity receiver,

No, look again, one amp is vertical polarization, the other horizontal.
One horn.

Two DROs, gated for band-switching as suspected.

That's a pretty impressive mixer, running at Ku-band.

I think that is pretty much the circuit diagram of this one too.

http://www.juras-projects.org/eng/hardware.php

That website gives nice info, bottom page.

Nice stuff. The DROs use BJTs--pretty neat that that's possible nowadays.

Yes I have some of those 2SC5508, Ft >= 20 GHz, noise typical 1.1 dB

 

[Jan Panteltje]

On a sunny day (Tue, 23 Sep 2014 05:15:00 -0700 (PDT)) it happened
dagmargoodboat@yahoo.com wrote in
<766f7aec-7611-413c-9a1b-80c45ffe0249@googlegroups.com>:

On Monday, September 22, 2014 12:42:18 PM UTC-4, Jan Panteltje wrote:
On a sunny day dagmargoo...@yahoo.com wrote:

I would've thought the "Ea" parts are the mixers, diode quads. The filters
are nicely realized on the PCB, and I'd have guessed the right-top chip
you mentioned is an output amplifier.


Well, maybe you are right,
could be active FET mixer...
then I will have to connect the coax a bit differently

Normally I'd expect the hair-pin bandpass to be the IF filter. I can't
tell from the dimensions from here, but it looks like it's at r.f. rather
than i.f. Weird.

Yes its RF, you find that bandpass filter in almost all sat LNBs.

ISTM the last FET to the right is the mixer, fed hot from the DROs, which
then goes through a wimpy IF filter before heading to the output amp.

I don't see any path from the DROs to the output chip, so either I've missed
it or it's likely not a mixer, just an amp.

As noted before, a Ku-band mixer chip would be something *mighty* special.

na, been done:
www.nxp.com/documents/application_note/AN11144.pdf

Sort of Startrek next generation...
2012
J.L. should look at the build in PLL.

 

[Jan Panteltje]

On a sunny day (Tue, 23 Sep 2014 05:40:18 -0700 (PDT)) it happened
dagmargoodboat@yahoo.com wrote in
<a1276880-0e94-4a2d-81e4-36ed6ca6f053@googlegroups.com>:

On Tuesday, September 23, 2014 4:22:19 AM UTC-4, Jan Panteltje wrote:
On a sunny day (Mon, 22 Sep 2014 17:48:11 -0700 (PDT)) it happened
dagmargoo...@yahoo.com wrote:

If you mix 10Mhz and 155.52MHz sines directly, the result is an unfilterable mess.

Just use the sum or difference, easy to filter.

Either 165.52 or 145.52 MHz

Any ol' radio does that.

1. Not to ppb.
2. We're trying to extract an 80KHz phase signal / beat frequency.

Well ,as I stated I'd like to know more about his 'reference' 10 MHz,
the absolute time and phase is bogus.
Low jitter can be done with a large time constant PLL loop filter.
I think that whole laser setup is well eh, CRAP.

Or, more specifically, to fix the 155.52 MHz phase in place,
at 15.552 000 00 cycles per 10MHz cycle, to a few pS over some
undefined time interval.

Do not see the problem, I am within 3 or ps (2 degrees) after
several conversions down from 1.something GHz.
People have proposed exact dividers already in this thread,
bit of filtering..
But even with some jitter 80 kHz can be filtered out,
a second more accurate phase comparator switched in, its all old hat.

 

[Phil Hobbs]

On 9/22/2014 11:54 PM, mroberds@att.net wrote:

Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den fredag den 19. september 2014 16.11.10 UTC+2 skrev dagmarg...@yahoo.com:
On Friday, September 12, 2014 9:18:41 PM UTC-4, mrob...@att.net wrote:

Sort of related: European starlings (Sturnus vulgaris) develop about
10 to 15 W of metabolic power, and deliver about 1 to 2.5 W at the
wings.

Pretty neat that a 100g critter makes 15W.

I liked the idea that if you have the amount of power that comes out of
a standard USB port, you can fly.

If you have a hub, you can power 100,000 mosquitoes.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[John Larkin]

On Mon, 22 Sep 2014 16:37:25 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

On Monday, September 22, 2014 2:56:05 PM UTC-4, John Larkin wrote:
On Mon, 22 Sep 2014 11:14:26 -0700 (PDT), dagmargoo...@yahoo.com wrote:

I like the microwave brick-style SRD->schottky sampling phase
detector--eliminates the need for one digital divider, and the
need to square up the 155.52 MHz. That's slick.

I assume samplers can be low-jitter. They're used in sampling
scopes, after all.

Samplers can have sub-ps jitter, but their equivalent noise figures
are terrible. They also tend to have a lot of time jitter vs
temperature. I think my d-flop bangbang phase detector will have the
best time stability.

Yeah, that has the advantage that you can sync it with an ECL D-flop
and take out virtually any arbitrary drift, delay, or wiggle.

Sounds good.

I was trying to avoid the comparator noise from squaring up the
155.52MHz, but there doesn't seem to be any easy way.

No problem. I'll be buying a VCXO with LVPECL outputs.

It would save a lot in the signal path if you could phase compare
sine waves, but with all these non-common factors in the frequencies
the filtering's impossible.

It's hard to get simpler than one d-flop.

My biggest concerns are filtering and squaring up to 10 MHz reference
sine wave, and the loop dynamics/noise. A little mental math suggests
that the 80 KHz bangbang loop will work, as long as the VCXO has good
open-loop jitter in the, roughly, milliseconds time scale.

I don't have tools to simulate this. Spice doesn't look appropriate.
If we get this job (chances are pretty good) the first thing to do is
a PLL breadboard.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[John Larkin]

On Mon, 22 Sep 2014 17:48:11 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

On Monday, September 22, 2014 8:03:55 PM UTC-4, Bill Sloman wrote:
On Tuesday, 23 September 2014 09:37:25 UTC+10, dagmarg...@yahoo.com wrote:
On Monday, September 22, 2014 2:56:05 PM UTC-4, John Larkin wrote:
On Mon, 22 Sep 2014 11:14:26 -0700 (PDT), dagmargoo...@yahoo.com wrote:

I like the microwave brick-style SRD->schottky sampling phase
detector--eliminates the need for one digital divider, and the
need to square up the 155.52 MHz. That's slick.

I assume samplers can be low-jitter. They're used in sampling
scopes, after all.

Samplers can have sub-ps jitter, but their equivalent noise figures
are terrible. They also tend to have a lot of time jitter vs
temperature. I think my d-flop bangbang phase detector will have the
best time stability.

The D-type bistable phase detector is a sampling detector. The signal at the D-input only influences the output at the active edge of the clock waveform.

The topic instant was schottky analog samplers.

Yeah, that has the advantage that you can sync it with an ECL D-flop
and take out virtually any arbitrary drift, delay, or wiggle.

Sounds good.

If you don't think about what's going on.


I was trying to avoid the comparator noise from squaring up the
155.52MHz, but there doesn't seem to be any easy way.

Any product detector will let you get away with comparing two sine waves. An AD834 might be one example.

If John has to divide down f(ref) and f(out), neither are sine waves.
One appeal of a sampler was that it eliminates the f(out) comparator
and divider.

If you mix 10Mhz and 155.52MHz sines directly, the result is an unfilterable
mess.

It would save a lot in the signal path if you could phase compare
sine waves, but with all these non-common factors in the frequencies
the filtering's impossible.

Use a DDS to get a 10MHz sine wave out of the 155.52MHz oscillator - low-pass filter the 10MHz to get reduce of the 155.52MHz step artifacts. I suspect that a two pole filter with a bit of ringing would distort the exponential segments between steps into something close enough to a sine wave for most purposes.



Detect phase with a reasonably linear product detector, so that the residual - systematic - spurs can average out over the 12.5usec repeat c...

The DDS in the signal path adds a horrendous, variable delay, loads of
transistors in the signal path, and no control over how clean the
supplies and signals are. I don't see how the DDS' wandering analog
output delay can be re-sync'd to the reference clock, something the
bang-bang can do with a single flop.

A DDS outputs a stepped pseudo-sine with a zero-crossing that will
periodically coincide with flat spots on the DDS'output waveform,
which modulates the zero-cross time (unless specific steps <ducks
are taken to prevent it). Filtering the DDS output to remove this
problem adds more critical circuitry, delay and drift.

Analog multiplier phase detectors are duty-cycle, d.c. offset, and
amplitude sensitive, all of which seem like bad ideas when John needs
rock-solid phase stability, AIUI.

Adding a DDS comes with a lot of deficits.

Correct. Even if you use a non-binary DDS to nail the frequency ratio,
the added errors would be ghastly.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Gerhard Hoffmann]

Am 23.09.2014 um 19:35 schrieb John Larkin:

No problem. I'll be buying a VCXO with LVPECL outputs.

....

My biggest concerns are filtering and squaring up to 10 MHz reference
sine wave, and the loop dynamics/noise. A little mental math suggests
that the 80 KHz bangbang loop will work, as long as the VCXO has good
open-loop jitter in the, roughly, milliseconds time scale.

Take a look at the LTC6957 family. Also, the differential limiter
on Wenzels web site is said to be good; recently, there was some
discussion on this on the timenuts list IIRC.

You already know the Oliver Collins paper on bandwidth limiting
and slope amplification.

regards, Gerhard

 

[Bill Sloman]

On Wednesday, 24 September 2014 03:35:44 UTC+10, John Larkin wrote:

On Mon, 22 Sep 2014 16:37:25 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:
On Monday, September 22, 2014 2:56:05 PM UTC-4, John Larkin wrote:
On Mon, 22 Sep 2014 11:14:26 -0700 (PDT), dagmargoo...@yahoo.com wrote:

I like the microwave brick-style SRD->schottky sampling phase
detector--eliminates the need for one digital divider, and the
need to square up the 155.52 MHz. That's slick.

I assume samplers can be low-jitter. They're used in sampling
scopes, after all.

Samplers can have sub-ps jitter, but their equivalent noise figures
are terrible. They also tend to have a lot of time jitter vs
temperature. I think my d-flop bangbang phase detector will have the
best time stability.

Yeah, that has the advantage that you can sync it with an ECL D-flop
and take out virtually any arbitrary drift, delay, or wiggle.

Sounds good.

I was trying to avoid the comparator noise from squaring up the
155.52MHz, but there doesn't seem to be any easy way.

If you used a product phase detector - like an AD834 - or even a switching full-wave phase detector like the Faulker and Harding long-tailed pair - it is dead easy. Not-invented-here concentration on the bang-bang sequential phase detector is not doing you any good at all.

> No problem. I'll be buying a VCXO with LVPECL outputs.

Of course.

It would save a lot in the signal path if you could phase compare
sine waves, but with all these non-common factors in the frequencies
the filtering's impossible.

It's hard to get simpler than one d-flop.

It's actually remarkably easy, but while you can lead a horse to water, you can't make him drink.

My biggest concerns are filtering and squaring up to 10 MHz reference
sine wave,

You don't have to. if you choose your phase detector sensibly.

and the loop dynamics/noise. A little mental math suggests
that the 80 KHz bangbang loop will work, as long as the VCXO has good
open-loop jitter in the, roughly, milliseconds time scale.

A little more would suggest that a product-type phase detector would work better, but they are not-invented-here devices.

I don't have tools to simulate this. Spice doesn't look appropriate.
If we get this job (chances are pretty good) the first thing to do is
a PLL breadboard.

A new pair of eyes on the problem might help more.

--
Bill Sloman, Sydney

 

[Bill Sloman]

On Wednesday, 24 September 2014 03:38:38 UTC+10, John Larkin wrote:

On Mon, 22 Sep 2014 17:48:11 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:
On Monday, September 22, 2014 8:03:55 PM UTC-4, Bill Sloman wrote:
On Tuesday, 23 September 2014 09:37:25 UTC+10, dagmarg...@yahoo.com
wrote:
On Monday, September 22, 2014 2:56:05 PM UTC-4, John Larkin wrote:
On Mon, 22 Sep 2014 11:14:26 -0700 (PDT), dagmargoo...@yahoo.com
wrote:

Any product detector will let you get away with comparing two sine waves. An AD834 might be one example.

If John has to divide down f(ref) and f(out), neither are sine waves.
One appeal of a sampler was that it eliminates the f(out) comparator
and divider.

If you mix 10Mhz and 155.52MHz sines directly, the result is an unfilterable
mess.

It would save a lot in the signal path if you could phase compare
sine waves, but with all these non-common factors in the frequencies
the filtering's impossible.

Use a DDS to get a 10MHz sine wave out of the 155.52MHz oscillator - low-pass filter the 10MHz to get reduce of the 155.52MHz step artifacts. I suspect that a two pole filter with a bit of ringing would distort the exponential segments between steps into something close enough to a sine wave for most purposes.

Detect phase with a reasonably linear product detector, so that the residual - systematic - spurs can average out over the 12.5usec repeat c...

The DDS in the signal path adds a horrendous, variable delay, loads of
transistors in the signal path, and no control over how clean the
supplies and signals are. I don't see how the DDS' wandering analog
output delay can be re-sync'd to the reference clock, something the
bang-bang can do with a single flop.

A DDS outputs a stepped pseudo-sine with a zero-crossing that will
periodically coincide with flat spots on the DDS'output waveform,
which modulates the zero-cross time (unless specific steps <ducks
are taken to prevent it). Filtering the DDS output to remove this
problem adds more critical circuitry, delay and drift.

Analog multiplier phase detectors are duty-cycle, d.c. offset, and
amplitude sensitive, all of which seem like bad ideas when John needs
rock-solid phase stability, AIUI.

Adding a DDS comes with a lot of deficits.

Correct.

Sure. But it eliminates a whole lot more that are intrinsic to your Bang-bang detect at 80KHz approach.

Even if you use a non-binary DDS to nail the frequency ratio,
the added errors would be ghastly.

Not that you have clue what they might be. The ghastliness is all in working out what they actually are.

--
Bill Sloman, Sydney

 

[Bill Sloman]

On Tuesday, 23 September 2014 22:48:02 UTC+10, dagmarg...@yahoo.com wrote:

On Monday, September 22, 2014 9:53:47 PM UTC-4, Bill Sloman wrote:
On Tuesday, 23 September 2014 10:48:11 UTC+10, dagmarg...@yahoo.com
wrote:

The DDS in the signal path adds a horrendous, variable delay, loads of
transistors in the signal path, and no control over how clean the
supplies and signals are. I don't see how the DDS' wandering analog
output delay can be re-sync'd to the reference clock, something the
bang-bang can do with a single flop.

The DDS would use the 155.52MHz source to clock the DAC producing the stair-case approximation to the desired 10MHz waveform.

That's not any kind of "horrendous variable delay" and there are very few transistors in that signal path. And you've got total control over rails feeding the DDS chip. The DDS doesn't have any kind of "wandering analog output delay".

AIUI the object is to stabilize the phase of the 155.52MHz output to ~10ppm
w.r.t. a precision 10MHz reference signal.

When you insert the DDS between the output signal and the phase comparison,
you've added an uncalibrated delay that cannot be removed, ditto any noise
or jitter produced in the DDS, that's my point.

And it's a very poor one.

In my previous response to this post I mentioned that you could roll your own DDS and get pick your own - calibrated - delay through the DDS, which got me thinking about what a roll-your-own DDS might look like.

Doing the usual minimal search on just-fast-enough DACs threw up the Analog Devices

http://www.analog.com/static/imported-files/data_sheets/AD9704_9705_9706_9707.pdf

which are just fast enough - with a maximum up-date rate of 175MHz - and have a typical output propagation delay of 4nsec.

http://www.analog.com/static/imported-files/data_sheets/AD9751.pdf

is faster, and not all that expensive, and offers a typical output propagation delay of 1nsec. No doubt one could do better.

The rest of the DDS could be jammed into a single programmable logic device, and would consist of an 11-bit address counter that counted edges of the 155.52MHZ clock, from 0 to 1943 and rolled over to 0 after 1943, to address a 1944-entry sine lookup table, whose output would drive the DAC (via a latch to re-sycnronise the digital output to the 155.52MHz clock).

One of the nice things about working at a fixed frequency is that you can use the DAC to drive an integrator, generating a straight-line segment approximation to a sine wave, rather than the usual DDS stair-case. A single pole of low-pass filtering on the DAC output current - about 3nsec worth - could smooth the transitions between the straight-line segments and smear out any switching glitches.

Of course you'd have to add a slow DC-feedback loop around the integrator to keep the output centered around 0V (or whatever fixed DC voltage took your fancy) but that's not rocket science.

It's taken me a surprisingly long time to wake up to this point. You could also integrate the output of conventional DDS chip to get the same effect.

--
Bill Sloman, Sydney

 

[Bill Sloman]

On Wednesday, 24 September 2014 13:51:19 UTC+10, rickman wrote:

On 9/23/2014 11:28 PM, Bill Sloman wrote:
On Tuesday, 23 September 2014 22:48:02 UTC+10, dagmarg...@yahoo.com wrote:
On Monday, September 22, 2014 9:53:47 PM UTC-4, Bill Sloman wrote:
On Tuesday, 23 September 2014 10:48:11 UTC+10, dagmarg...@yahoo.com
wrote:

The DDS in the signal path adds a horrendous, variable delay, loads of
transistors in the signal path, and no control over how clean the
supplies and signals are. I don't see how the DDS' wandering analog
output delay can be re-sync'd to the reference clock, something the
bang-bang can do with a single flop.

The DDS would use the 155.52MHz source to clock the DAC producing the stair-case approximation to the desired 10MHz waveform.

That's not any kind of "horrendous variable delay" and there are very few transistors in that signal path. And you've got total control over rails feeding the DDS chip. The DDS doesn't have any kind of "wandering analog output delay".

AIUI the object is to stabilize the phase of the 155.52MHz output to
~10ppm w.r.t. a precision 10MHz reference signal.

When you insert the DDS between the output signal and the phase comparison, you've added an uncalibrated delay that cannot be removed, ditto any noise or jitter produced in the DDS, that's my point.

And it's a very poor one.

In my previous response to this post I mentioned that you could roll your own DDS and get pick your own - calibrated - delay through the DDS, which got me thinking about what a roll-your-own DDS might look like.

Doing the usual minimal search on just-fast-enough DACs threw up the Analog Devices

http://www.analog.com/static/imported-files/data_sheets/AD9704_9705_9706_9707.pdf

which are just fast enough - with a maximum up-date rate of 175MHz - and have a typical output propagation delay of 4nsec.

http://www.analog.com/static/imported-files/data_sheets/AD9751.pdf

is faster, and not all that expensive, and offers a typical output propagation delay of 1nsec. No doubt one could do better.

The rest of the DDS could be jammed into a single programmable logic device, and would consist of an 11-bit address counter that counted edges of the 155.52MHZ clock, from 0 to 1943 and rolled over to 0 after 1943, to address a 1944-entry sine lookup table, whose output would drive the DAC (via a latch to re-sycnronise the digital output to the 155.52MHz clock).

One of the nice things about working at a fixed frequency is that you can use the DAC to drive an integrator, generating a straight-line segment approximation to a sine wave, rather than the usual DDS stair-case. A single pole of low-pass filtering on the DAC output current - about 3nsec worth - could smooth the transitions between the straight-line segments and smear out any switching glitches.

Of course you'd have to add a slow DC-feedback loop around the integrator to keep the output centered around 0V (or whatever fixed DC voltage took your fancy) but that's not rocket science

It's taken me a surprisingly long time to wake up to this point. You could also integrate the output of conventional DDS chip to get the same effect.

Perhaps you could explain to me why you need a fast DAC if you are going
to filter it through a low pass filter?

John Larkin wants to lock his 155.52MHz local clock to the 10MHz reference clock distributed around the laser farm, and he wants to do it with sub-picosecond long term stability.

There's a delay between clocking the DDS digital data on an edge of the 155..52MHz clock, and the analog output from the DAC going into the integrator.

There's a further delay through the integrator, but if you wrap it around a really fast op amp, it won't be big either.

The delays, and - more important - all the drifts on these delays - add up and eat into John's error budget. The crudest - but often the most effective way of minimising - the drifts on the individual delays is simply to keep them small.

It might be an argument for going for fractional-n rather than DDS for getting the derived 10MHz waveform. With that you are definitely stuck with a linear phase detector, but there are a up to 6.4nsec of phase excursion on each nominally 10MHz edge, but the delays can all be through ECLinPS logic.

> When you say "integrator" do you mean integrator or low pass filter?

I mean an integrator.

I'm unclear on what waveform you would expect from an integrator. Are

you going to set the values in your sine table to be the deltas rather
than the sine values? That might make sense.

The integral and the derivation of a sine wave is a cosine wave. It's not rocket science.

--
Bill Sloman, Sydney

 

[rickman]

On 9/24/2014 1:52 AM, Bill Sloman wrote:

On Wednesday, 24 September 2014 13:51:19 UTC+10, rickman wrote:
On 9/23/2014 11:28 PM, Bill Sloman wrote:
On Tuesday, 23 September 2014 22:48:02 UTC+10, dagmarg...@yahoo.com wrote:
On Monday, September 22, 2014 9:53:47 PM UTC-4, Bill Sloman wrote:
On Tuesday, 23 September 2014 10:48:11 UTC+10, dagmarg...@yahoo.com
wrote:

The DDS in the signal path adds a horrendous, variable delay, loads of
transistors in the signal path, and no control over how clean the
supplies and signals are. I don't see how the DDS' wandering analog
output delay can be re-sync'd to the reference clock, something the
bang-bang can do with a single flop.

The DDS would use the 155.52MHz source to clock the DAC producing the stair-case approximation to the desired 10MHz waveform.

That's not any kind of "horrendous variable delay" and there are very few transistors in that signal path. And you've got total control over rails feeding the DDS chip. The DDS doesn't have any kind of "wandering analog output delay".

AIUI the object is to stabilize the phase of the 155.52MHz output to
~10ppm w.r.t. a precision 10MHz reference signal.

When you insert the DDS between the output signal and the phase comparison, you've added an uncalibrated delay that cannot be removed, ditto any noise or jitter produced in the DDS, that's my point.

And it's a very poor one.

In my previous response to this post I mentioned that you could roll your own DDS and get pick your own - calibrated - delay through the DDS, which got me thinking about what a roll-your-own DDS might look like.

Doing the usual minimal search on just-fast-enough DACs threw up the Analog Devices

http://www.analog.com/static/imported-files/data_sheets/AD9704_9705_9706_9707.pdf

which are just fast enough - with a maximum up-date rate of 175MHz - and have a typical output propagation delay of 4nsec.

http://www.analog.com/static/imported-files/data_sheets/AD9751.pdf

is faster, and not all that expensive, and offers a typical output propagation delay of 1nsec. No doubt one could do better.

The rest of the DDS could be jammed into a single programmable logic device, and would consist of an 11-bit address counter that counted edges of the 155.52MHZ clock, from 0 to 1943 and rolled over to 0 after 1943, to address a 1944-entry sine lookup table, whose output would drive the DAC (via a latch to re-sycnronise the digital output to the 155.52MHz clock).

One of the nice things about working at a fixed frequency is that you can use the DAC to drive an integrator, generating a straight-line segment approximation to a sine wave, rather than the usual DDS stair-case. A single pole of low-pass filtering on the DAC output current - about 3nsec worth - could smooth the transitions between the straight-line segments and smear out any switching glitches.

Of course you'd have to add a slow DC-feedback loop around the integrator to keep the output centered around 0V (or whatever fixed DC voltage took your fancy) but that's not rocket science

It's taken me a surprisingly long time to wake up to this point. You could also integrate the output of conventional DDS chip to get the same effect.

Perhaps you could explain to me why you need a fast DAC if you are going
to filter it through a low pass filter?

John Larkin wants to lock his 155.52MHz local clock to the 10MHz reference clock distributed around the laser farm, and he wants to do it with sub-picosecond long term stability.

There's a delay between clocking the DDS digital data on an edge of the 155.52MHz clock, and the analog output from the DAC going into the integrator.

There's a further delay through the integrator, but if you wrap it around a really fast op amp, it won't be big either.

The delays, and - more important - all the drifts on these delays - add up and eat into John's error budget. The crudest - but often the most effective way of minimising - the drifts on the individual delays is simply to keep them small.

It might be an argument for going for fractional-n rather than DDS for getting the derived 10MHz waveform. With that you are definitely stuck with a linear phase detector, but there are a up to 6.4nsec of phase excursion on each nominally 10MHz edge, but the delays can all be through ECLinPS logic.

I didn't need a recap of the whole thing. The question is why would you
worry about a couple of nanoseconds on the DAC when you are running the
output through a filter which delays it further likely by a larger amount?

When you say "integrator" do you mean integrator or low pass filter?

I mean an integrator.

I'm unclear on what waveform you would expect from an integrator. Are

you going to set the values in your sine table to be the deltas rather
than the sine values? That might make sense.

The integral and the derivation of a sine wave is a cosine wave. It's not rocket science.

No, but you are messing further with the delays which you seem to say
you care about. In reality the delays on this portion of the circuit
are moot. They will be calibrated out.

But this does give me some interesting ideas on better ways to do the DAC.

--

Rick

 

[rickman]

On 9/23/2014 11:28 PM, Bill Sloman wrote:

On Tuesday, 23 September 2014 22:48:02 UTC+10, dagmarg...@yahoo.com wrote:
On Monday, September 22, 2014 9:53:47 PM UTC-4, Bill Sloman wrote:
On Tuesday, 23 September 2014 10:48:11 UTC+10, dagmarg...@yahoo.com
wrote:

The DDS in the signal path adds a horrendous, variable delay, loads of
transistors in the signal path, and no control over how clean the
supplies and signals are. I don't see how the DDS' wandering analog
output delay can be re-sync'd to the reference clock, something the
bang-bang can do with a single flop.

The DDS would use the 155.52MHz source to clock the DAC producing the stair-case approximation to the desired 10MHz waveform.

That's not any kind of "horrendous variable delay" and there are very few transistors in that signal path. And you've got total control over rails feeding the DDS chip. The DDS doesn't have any kind of "wandering analog output delay".

AIUI the object is to stabilize the phase of the 155.52MHz output to ~10ppm
w.r.t. a precision 10MHz reference signal.

When you insert the DDS between the output signal and the phase comparison,
you've added an uncalibrated delay that cannot be removed, ditto any noise
or jitter produced in the DDS, that's my point.

And it's a very poor one.

In my previous response to this post I mentioned that you could roll your own DDS and get pick your own - calibrated - delay through the DDS, which got me thinking about what a roll-your-own DDS might look like.

Doing the usual minimal search on just-fast-enough DACs threw up the Analog Devices

http://www.analog.com/static/imported-files/data_sheets/AD9704_9705_9706_9707.pdf

which are just fast enough - with a maximum up-date rate of 175MHz - and have a typical output propagation delay of 4nsec.

http://www.analog.com/static/imported-files/data_sheets/AD9751.pdf

is faster, and not all that expensive, and offers a typical output propagation delay of 1nsec. No doubt one could do better.

The rest of the DDS could be jammed into a single programmable logic device, and would consist of an 11-bit address counter that counted edges of the 155.52MHZ clock, from 0 to 1943 and rolled over to 0 after 1943, to address a 1944-entry sine lookup table, whose output would drive the DAC (via a latch to re-sycnronise the digital output to the 155.52MHz clock).

One of the nice things about working at a fixed frequency is that you can use the DAC to drive an integrator, generating a straight-line segment approximation to a sine wave, rather than the usual DDS stair-case. A single pole of low-pass filtering on the DAC output current - about 3nsec worth - could smooth the transitions between the straight-line segments and smear out any switching glitches.

Of course you'd have to add a slow DC-feedback loop around the integrator to keep the output centered around 0V (or whatever fixed DC voltage took your fancy) but that's not rocket science.

It's taken me a surprisingly long time to wake up to this point. You could also integrate the output of conventional DDS chip to get the same effect.

Perhaps you could explain to me why you need a fast DAC if you are going
to filter it through a low pass filter?

When you say "integrator" do you mean integrator or low pass filter?
I'm unclear on what waveform you would expect from an integrator. Are
you going to set the values in your sine table to be the deltas rather
than the sine values? That might make sense.

--

Rick

 

[Bill Sloman]

On Wednesday, 24 September 2014 16:29:14 UTC+10, rickman wrote:

On 9/24/2014 1:52 AM, Bill Sloman wrote:
On Wednesday, 24 September 2014 13:51:19 UTC+10, rickman wrote:
On 9/23/2014 11:28 PM, Bill Sloman wrote:
On Tuesday, 23 September 2014 22:48:02 UTC+10, dagmarg...@yahoo.com
wrote:
On Monday, September 22, 2014 9:53:47 PM UTC-4, Bill Sloman wrote:
On Tuesday, 23 September 2014 10:48:11 UTC+10, dagmarg...@yahoo.com
wrote:

<snip>

> I didn't need a recap of the whole thing.

That was less than obvious.

The question is why would you
worry about a couple of nanoseconds on the DAC when you are running the
output through a filter which delays it further likely by a larger amount?

You won't use much filtering on the DAC output before you put it into the phase detector of the PLL.

With a staircase approximation, I was thinking of a slightly ringing two-pole filter which might have had a delay of about 6nsec, and with the straight-line segment approximation you'd get coming out of an integrator, one pole and about 3nsec would probably be plenty - and you could probably get away with with rather less.

After the phase detector has turned any phase error into a DC signal, you then low-pass filter like hell, but you can set up the PLL feedback path to cope with this and still offer a dead-beat response, albeit with a delay of a millisecond or so, if I've understood John Larkin's ambitions correctly.

When you say "integrator" do you mean integrator or low pass filter?

I mean an integrator.

I'm unclear on what waveform you would expect from an integrator. Are
you going to set the values in your sine table to be the deltas rather
than the sine values? That might make sense.

The integral and the derivation of a sine wave is a cosine wave. It's not rocket science.

No, but you are messing further with the delays which you seem to say
you care about. In reality the delays on this portion of the circuit
are moot. They will be calibrated out.

The frequency response of the op amp around which the integrator is built will introduce a delay, but - with a fast op amp - not a big one

> But this does give me some interesting ideas on better ways to do the DAC..

Do try to sell them to Analog Device, Linear Technology and the rest - they've been looking for better ways to realise special purpose DACs for some time now.

--
Bill Sloman, Sydney

 

[Jeroen Belleman]

On 2014-09-24 08:29, rickman wrote:

On 9/24/2014 1:52 AM, Bill Sloman wrote:
On Wednesday, 24 September 2014 13:51:19 UTC+10, rickman wrote:
On 9/23/2014 11:28 PM, Bill Sloman wrote:
On Tuesday, 23 September 2014 22:48:02 UTC+10, dagmarg...@yahoo.com
wrote:
On Monday, September 22, 2014 9:53:47 PM UTC-4, Bill Sloman wrote:
On Tuesday, 23 September 2014 10:48:11 UTC+10, dagmarg...@yahoo.com
wrote:

The DDS in the signal path adds a horrendous, variable delay,
loads of
transistors in the signal path, and no control over how clean the
supplies and signals are. I don't see how the DDS' wandering analog
output delay can be re-sync'd to the reference clock, something the
bang-bang can do with a single flop.

The DDS would use the 155.52MHz source to clock the DAC producing
the stair-case approximation to the desired 10MHz waveform.

That's not any kind of "horrendous variable delay" and there are
very few transistors in that signal path. And you've got total
control over rails feeding the DDS chip. The DDS doesn't have any
kind of "wandering analog output delay".

AIUI the object is to stabilize the phase of the 155.52MHz output to
~10ppm w.r.t. a precision 10MHz reference signal.

When you insert the DDS between the output signal and the phase
comparison, you've added an uncalibrated delay that cannot be
removed, ditto any noise or jitter produced in the DDS, that's my
point.

And it's a very poor one.

In my previous response to this post I mentioned that you could roll
your own DDS and get pick your own - calibrated - delay through the
DDS, which got me thinking about what a roll-your-own DDS might look
like.

Doing the usual minimal search on just-fast-enough DACs threw up the
Analog Devices

http://www.analog.com/static/imported-files/data_sheets/AD9704_9705_9706_9707.pdf


which are just fast enough - with a maximum up-date rate of 175MHz -
and have a typical output propagation delay of 4nsec.

http://www.analog.com/static/imported-files/data_sheets/AD9751.pdf

is faster, and not all that expensive, and offers a typical output
propagation delay of 1nsec. No doubt one could do better.

The rest of the DDS could be jammed into a single programmable logic
device, and would consist of an 11-bit address counter that counted
edges of the 155.52MHZ clock, from 0 to 1943 and rolled over to 0
after 1943, to address a 1944-entry sine lookup table, whose output
would drive the DAC (via a latch to re-sycnronise the digital output
to the 155.52MHz clock).

One of the nice things about working at a fixed frequency is that
you can use the DAC to drive an integrator, generating a
straight-line segment approximation to a sine wave, rather than the
usual DDS stair-case. A single pole of low-pass filtering on the DAC
output current - about 3nsec worth - could smooth the transitions
between the straight-line segments and smear out any switching
glitches.

Of course you'd have to add a slow DC-feedback loop around the
integrator to keep the output centered around 0V (or whatever fixed
DC voltage took your fancy) but that's not rocket science

It's taken me a surprisingly long time to wake up to this point. You
could also integrate the output of conventional DDS chip to get the
same effect.

Perhaps you could explain to me why you need a fast DAC if you are going
to filter it through a low pass filter?

John Larkin wants to lock his 155.52MHz local clock to the 10MHz
reference clock distributed around the laser farm, and he wants to do
it with sub-picosecond long term stability.

There's a delay between clocking the DDS digital data on an edge of
the 155.52MHz clock, and the analog output from the DAC going into the
integrator.

There's a further delay through the integrator, but if you wrap it
around a really fast op amp, it won't be big either.

The delays, and - more important - all the drifts on these delays -
add up and eat into John's error budget. The crudest - but often the
most effective way of minimising - the drifts on the individual delays
is simply to keep them small.

It might be an argument for going for fractional-n rather than DDS for
getting the derived 10MHz waveform. With that you are definitely stuck
with a linear phase detector, but there are a up to 6.4nsec of phase
excursion on each nominally 10MHz edge, but the delays can all be
through ECLinPS logic.

I didn't need a recap of the whole thing. The question is why would you
worry about a couple of nanoseconds on the DAC when you are running the
output through a filter which delays it further likely by a larger amount?


When you say "integrator" do you mean integrator or low pass filter?

I mean an integrator.

I'm unclear on what waveform you would expect from an integrator. Are

you going to set the values in your sine table to be the deltas rather
than the sine values? That might make sense.

The integral and the derivation of a sine wave is a cosine wave. It's
not rocket science.

No, but you are messing further with the delays which you seem to say
you care about. In reality the delays on this portion of the circuit
are moot. They will be calibrated out.

But this does give me some interesting ideas on better ways to do the DAC.

The DAC and the following low-pass are there only to smooth out the
6.4ns cycle-to-cyle variations of the 10MHz DDS output. I don't see
why one would bother with a DAC at all. Just use the MSB of the phase
accumulator and let the loop filter do the filtering. No more drifty
analog filters in the critical path.

If you tweak the NCO to make the MSB a 50% duty cycle square wave
on average, you can pipe it straight into a DB mixer with your
sine-wave 10MHz reference at the other input to make the phase
error signal.

Jeroen Belleman