PLL tricks

[Bill Sloman]

On 27/09/2014 12:17 PM, rickman wrote:

On 9/26/2014 9:50 PM, Bill Sloman wrote:
On Saturday, 27 September 2014 02:34:10 UTC+10, rickman wrote:
On 9/26/2014 10:53 AM, Bill Sloman wrote:
On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John
Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip


It's got to be fast enough - coping with the output of 16-bit ADC
sampling every 6.43nsec is demanding. The last time I tried to do
anything like - with 100k ECL - 20nsec proved to be faster than we
could manage - mainly because the ECL memory chips we could buy back
then weren't all that quick.

Wow, trying to design a 200 MHz circuit in ECL would be a massive
design. I worked on a machine that used ECL gate arrays for what
amounts to the ALU of a DSP chip in a whole rack cabinet of circuitry.
That was about forty years ago. Things have changed since then... The
new big is "small". Nearly any FPGA will run multipliers with a 200 MHz
clock. So I don't think accepting inputs from a 16 bit 200 MHz ADC will
be much problem.

Sure. Our digital signal processing took up a triple-extended Eurocard.
What we should have done was use Xilinx XC4000 chips (this was 1988-91)
but that wouldn't have sampled faster than 10MHz and the boss/marketing
guy wanted to have more impressive numbers to boast about, which we gave
him, but we took long doing it that it turned out that ww should have done.

A programmable logic chips big enough to offer a couple of thousand
16-bit wide words of static RAM memory would be attractive.

Nearly *any* FPGA has several thousand bytes of RAM. But they all are
clocked if that makes any difference. No more async RAMs. Many have
100's of kB of RAM on chip... the big brutes.

I haven't a clue why Gerhard Hoffmann singled out the Spartan 6. I
last used a programmable logic device back in 1998 - and it wasn't a
big one. I've thought about using the Philips - now Xilinx -
Coolrunner parts for odd projects since then and actually have 25 of
them in a box somewhere, but while I did - once - downloaded the
Xilinx programming software, my colleague in London persuaded me that
programming any digital logic would be a distraction from the work
that really needed to be done at the time.

I'm not trying to be negative about the Spartan 6 devices. It is just
that any time people mention FPGAs, the image that seems to come to mind
is a big, sweaty, brutish chip that is only considered when everything
else won't do the job. I'm just trying to make a point that there are
many flavors of FPGAs out there across a spectrum, much like other
device families like MCUs and even simple logic. If you say you need to
put a flipflop on your board do you automatically assume that means an
ECL device? No, there are many flavors of logic and the same is true
for programmable logic devices.

The flavor that you mentioned, coolrunner, are actually obsolete.
Coolrunner II is still made I believe, but are functionally obsolete in
that there are lots of much better choices out there.

The charm for me was always the low power consumption. Most CPLD's are
designed on the basis theat they are going to be as fast as possible and
consequently draw hideous amounts of current and run really hot.

I'd have to do quite a lot of reading before I could work out any
useful ideas about anything bigger or faster.

Programmable logic can be *very* powerful. I'm not sure why learning
about CPLDs or FPGAs would be a distraction if they could be used in
your designs. It's hard to imagine a design that can't use programmable
logic, at least for me...

BTW, nearly all logic designs are done in an HDL now. So it really
isn't so much an issue of design size. It is very much like writing
software and many of the techniques apply; modules, unit test, test
benches... You just need to be systematic about it and remember that
you aren't writing code as much as describing hardware, hence the name HDL.

You are preaching to the thoroughly converted. I first got well into
that idea when I was writing assembler for a PDP-8 back in 1968 - I'd
done Theory of Computation 1 as a single course the previous year and
the lecturer had been insistent that you only programmed in assembler
when you had to take into account the limitations of the processor
hardware. They also talked about adjusting your Fortran code for the
same reason.

--
Bill Sloman, Sydney
>

 

[Bill Sloman]

On Saturday, 27 September 2014 16:42:50 UTC+10, Kevin Aylward wrote:

"Bill Sloman" wrote in message news:m05f86$iq2$1@dont-email.me...
On 27/09/2014 2:36 AM, Kevin Aylward wrote:
"Bill Sloman" wrote in message news:m03ukr$n3k$1@dont-email.me...

My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter sampling
at 155.52MHz and feeding a number cruncher embedded in a reasonably
big programmable logic device. He mentioned a Xilinx Spartan-6

As an analog man, this is fingernails down a blackboard...

Perhaps. But I'm a mixed-signal man myself. John Larkin is only going to
build eight units, so buying a lot analog refinement probably wouldn't make
sense. Analog signal processing is a lot cheaper than digital, but analog
development is slower.

Yes. I can add two numbers with two resistors!

Its the small number of units that make this a more difficult task. Larger
numbers, and its an IC.

When I was closer to the coal-face, 100,000 units was about what it took to justify an ASIC.

European Semiconductor Structures - with their shaped beam electron beam microfabricators - offered maskless ASICs that were practicable in smaller volume - Cambridge Instruments were looking at 500 per year.

I don't know the current state of play. Programmable parts have chewed into the low volume ASIC market, but I don't know where the cut-offs are now.

You're other postyou had:

It's got to be fast enough - coping with the output of 16-bit ADC sampling
every 6.43nsec is demanding.

A vanilla, relatively cheap 0.18u process has around 50ps gate days, so in
my IC analog world, 6ns is pretty much a no-brainer.

Provided you can keep it all on one chip. Driving terminated transmission lines between chips is greedy of current.

Interestingly, you highlight a basic problem with the impeding 50Gs/s optic
systems for board level. One approach uses 300 of 200MHz 8bit ADC with a
interleaved sampler. Its impossible to do this discretely. It has to be all
on chip, e.g. to avoid the huge data bus problems.

If you want to do it tolerably cheaply. An ECL or an LVDS terminated bus

http://en.wikipedia.org/wiki/Low-voltage_differential_signaling

is perfectly practical, but bulky and not all that cheap.

--
Bill Sloman, Sydney

 

[Kevin Aylward]

"Bill Sloman" wrote in message news:m05f86$iq2$1@dont-email.me...

On 27/09/2014 2:36 AM, Kevin Aylward wrote:

"Bill Sloman" wrote in message news:m03ukr$n3k$1@dont-email.me...

My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter sampling
at 155.52MHz and feeding a number cruncher embedded in a reasonably
big programmable logic device. He mentioned a Xilinx Spartan-6

As an analog man, this is fingernails down a blackboard...

Perhaps. But I'm a mixed-signal man myself. John Larkin is only going to
build eight units, so buying a lot analog refinement probably wouldn't make
sense. Analog signal processing is a lot cheaper than digital, but analog
development is slower.

Yes. I can add two numbers with two resistors!

Its the small number o units that make this a more difficult task. Larger
numbers, and its an IC.

You're other postyou had:

It's got to be fast enough - coping with the output of 16-bit ADC sampling
every 6.43nsec is demanding.

A vanilla, relatively cheap 0.18u process has around 50ps gate days, so in
my IC analog world, 6ns is pretty much a no-brainer.

Interestingly, you highlight a basic problem with the impeding 50Gs/s optic
sytems for board level. One approach uses 300 of 200MHz 8bit ADC with a
interleaved sampler. Its impossible to do this discretely. It has to be all
on chip, e.g. to avoid the huge data bus problems.


Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

 

[Bill Sloman]

On Saturday, 27 September 2014 21:45:31 UTC+10, Kevin Aylward wrote:

"Bill Sloman" wrote in message
news:63c0a9d9-72af-461d-ab28-11b57cd5172e@googlegroups.com...

Interestingly, you highlight a basic problem with the impeding 50Gs/s
optic systems for board level. One approach uses 300 of 200MHz 8bit ADC
with a interleaved sampler. Its impossible to do this discretely. It has
to be all on chip, e.g. to avoid the huge data bus problems.

f you want to do it tolerably cheaply. An ECL or an LVDS terminated bus

http://en.wikipedia.org/wiki/Low-voltage_differential_signaling

is perfectly practical, but bulky and not all that cheap.

I know all about LVDS....I think you may not have thought about this problem
yet Bill.

I though about it enough to use ECL buses across the backplane of the signal-processing crate in our electron beam tester - which worked, but not soon enough for us to put it into production in 1991.

http://www.fujitsu.com/downloads/MICRO/fme/dataconverters/OFC-2010-56Gss-ADC-Enabling-100GbE.pdf

http://www.ece.queensu.ca/Current-Students/Undergraduate/Course-Homepages/ELEC-486/files/Bower_OFT_2011.pdf

No chance, whatsoever of doing that type of product off chip.

Well, their ADCs are working a couple of order of magnitude faster than the parts I could get my hands on.

> Its stunning difficult.

Certainly not simple. We had more trouble getting getting components to accept the data at high rates than we ever had getting the data to them.

--
Bill Sloman, Sydney

 

[Kevin Aylward]

"Bill Sloman" wrote in message
news:63c0a9d9-72af-461d-ab28-11b57cd5172e@googlegroups.com...

Interestingly, you highlight a basic problem with the impeding 50Gs/s
optic
systems for board level. One approach uses 300 of 200MHz 8bit ADC with a
interleaved sampler. Its impossible to do this discretely. It has to be
all
on chip, e.g. to avoid the huge data bus problems.

f you want to do it tolerably cheaply. An ECL or an LVDS terminated bus

http://en.wikipedia.org/wiki/Low-voltage_differential_signaling

is perfectly practical, but bulky and not all that cheap.

I know all about LVDS....I think you may not have thought about this problem
yet Bill.

http://www.fujitsu.com/downloads/MICRO/fme/dataconverters/OFC-2010-56Gss-ADC-Enabling-100GbE.pdf

http://www.ece.queensu.ca/Current-Students/Undergraduate/Course-Homepages/ELEC-486/files/Bower_OFT_2011.pdf

No chance, whatsoever of doing that type of product off chip.

Its stunning difficult.

Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

 

[DecadentLinuxUserNumeroUn]

On Sat, 27 Sep 2014 12:45:31 +0100, "Kevin Aylward"
<ExtractkevinRemove@kevinaylward.co.uk> Gave us:

>http://www.fujitsu.com/downloads/MICRO/fme/dataconverters/OFC-2010-56Gss-ADC-Enabling-100GbE.pdf

Nice! Fujitsu appears to be placing a lot into it.

All of the optical interlinks we typically use these days (XFP, SFP,
Etc.)are all 10Gb/s ports.

100Gb is a lot of electrons being carefully manipulated. Wow!

 

[DecadentLinuxUserNumeroUn]

On Sat, 27 Sep 2014 08:48:53 -0700 (PDT), Bill Sloman
<bill.sloman@gmail.com> Gave us:

Inductance isn't necessarily a problem - within limits.

Yeah... like frequency of operation.

That remark you made about data rates and orders of magnitude can be
assigned to your grasp of the effects of inductance at these data rates
and when trying to generate clean modulation constellations.

Your grasp is DOWN a few orders of magnitude. And a couple decades.

 

[Phil Hobbs]

On 9/26/2014 10:24 PM, rickman wrote:

On 9/26/2014 7:58 PM, Phil Hobbs wrote:
On 9/26/2014 1:57 PM, rickman wrote:
On 9/26/2014 1:13 PM, Phil Hobbs wrote:
On 9/26/2014 10:53 AM, Bill Sloman wrote:
On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John
Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the amplitude
information and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce
overlapped
results (of any length) on every cycle of the 155.52 MHz clock.
So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the
loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

There's no intrinsic 1944 sample latency if you are using an A/D
converter to sample the 10MHz reference sine wave at 155.52MHz.

There's nothing magic about FFTs--each channel is equivalent to a bog
standard FIR filter. The filter has to be causal, so since it's 1944
samples wide, the delay has to be at least half that.

With infinite computational resources you could do a non-linear
least-squares fit of a 10MHz-ish sine wave to anything more than about
four successive samples - since you can be pretty confident that you
are
looking at a 10MHz sine wave. With a few as 16 samples - if there was
hardly any noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

You keep ignoring drift.


The 10MHz sine wave would be described by four parameters - frequency,
absolute phase, amplitude and DC offset. The DC offset ought to be
zero,
but A/D converters aren't perfect.

Since John actually wants only about 500Hz bandwidth in his PLL
feedback
path, worrying about a 12.5usec latency implicit in the 1944 sample
repeat cycle is probably not a useful exercise, even if it were real.

Which it is (972 samples' worth, anyway).


ISTM that the main issues with the B-B loop are: (1) gross PD ripple;
(b) the huge and poorly controlled gain of the phase detector, which
will depend critically on the residual wideband jitter of the two
clocks; and (c), that all the wideband jitter of the VCXO will be
aliased down into the fundamental interval.

Any metastability worries can be got round by reclocking the PD
output
from either one of the oscillators, which won't cause significant
extra
latency in an 80-kHz loop. Wrapping the VCXO inside a simple
wideband
fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM
none
will accomplish the required long-term timing stability.)

The residual drift and low-frequency crap could be removed
afterwards,
using the bang-bang PD to control a varactor phase shifter on the 10
MHz
sine wave input. The combination ought to be pretty impressive.

One would be impressed that he'd got it to work, less impressed by the
fact that he hadn't been able to recognise the superiority of any of
the
better schemes that have been proposed here.

Most of which ignore drift. A picosecond is not a long time.


My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter
sampling at
155.52MHz and feeding a number cruncher embedded in a reasonably big
programmable logic device. He mentioned a Xilinx Spartan-6

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/

A pretty big hammer to replace a single D-flop!

I could have sworn there was some other stuff in that design... another
d-flop to start (fancy ECL stuff, and expensive)... a rather tricky
filter and bunches more. Most of that gets replaced with logic in the
FPGA, the ADC and a DAC.

man-with-only-a-hammer-alert

The D-flop costs about $5 in unit quantity, which is pretty cheap for an
FPGA, especially since all the programming effort would be amortized
over 8 whole units.

And the rest??? Doesn't that have NRE design costs?

Not on the same scale at all. One can design a PLL on a napkin in a few
minutes. The parlour tricks are (1) analogue conditioning of the 10
MHz; (2) resampling the divider output to get rid of its jitter and
timing drift; (3) characterization when you're done. All three of those
things still have to be done with the FPGA approach.

As for the rest, the 10 MHz will have to be cleaned up in analogue
somehow, because otherwise its jitter will show up in the FPGA's
output--the analogy between DSP and real genuine analogue signal
processing stands or falls by the samples being evenly spaced. Most of
the time that's not such a worry, but for 1 ps timing accuracy, it most
emphatically is.

Not sure which 10 MHz you are talking about, from the bang bang detector
or the signal processing based approach. I'm not sure why there would
be a 10 MHz signal in the signal processing approach.

Because that's what you're locking to, of course.

I'm old-fashioned - I find anything more powerful than 22V10 a trifle
intimidating, though I did some useful stuff with the PA7024 (which
is a
more powerful drop-in replacement for 22V10).

Dangerous Prototypes sells some nice Xilinx XC9572XL CPLD breakout
boards with JTAG headers. The software is free, if clunky, and you can
get a programming cable from Digilent for $50. (You can also build
your
own from published plans.)

Wow! That is an old part and very limited. There are lots better
devices to get familiar with.

Sure. But it was cheap, did the job, and since there's nothing very
special about different CPLDs, there's nothing obsolete about the
knowledge gained.

Sure, any port... but that really wasn't anything remotely appropriate
for the issue we are discussing. It's like saying to get familiar with
the design we are talking about by learning how to use an opamp, a good
first step.

I was responding to Bill, not to you. He was talking about 22V10s.

What are the published plans for FPGA programming cables? Are you
talking about the ones that require a parallel port on a PC?

I wasn't talking about FPGAs at all.

/man-with-only-a-hammer-alert

Uh, what were you talking about building then?

I posted the block diagram many lines up in this thread.

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Phil Hobbs]

On 9/26/2014 10:57 PM, Bill Sloman wrote:

On 27/09/2014 9:58 AM, Phil Hobbs wrote:
On 9/26/2014 1:57 PM, rickman wrote:
On 9/26/2014 1:13 PM, Phil Hobbs wrote:
On 9/26/2014 10:53 AM, Bill Sloman wrote:
On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2
skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard
Hoffmann <ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the
amplitude information and run your VCXO from the phase
information"?

Yeah, and the calculations can very easily be done to
produce overlapped results (of any length) on every
cycle of the 155.52 MHz clock. So no need to wait 12.5
microseconds to close the loop.

There's still the 1944-cycle latency, though, which will
make the loop unstable if you try to go much faster. The
good news is that it wouldn't have the grotesque output
ripple of a bang-bang PD, so it wouldn't have to be
filtered as hard.

There's no intrinsic 1944 sample latency if you are using an
A/D converter to sample the 10MHz reference sine wave at
155.52MHz.

There's nothing magic about FFTs--each channel is equivalent
to a bog standard FIR filter. The filter has to be causal, so
since it's 1944 samples wide, the delay has to be at least
half that.

With infinite computational resources you could do a
non-linear least-squares fit of a 10MHz-ish sine wave to
anything more than about four successive samples - since you
can be pretty confident that you are looking at a 10MHz sine
wave. With a few as 16 samples - if there was hardly any
noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

You keep ignoring drift.

The 10MHz sine wave would be described by four parameters -
frequency, absolute phase, amplitude and DC offset. The DC
offset ought to be zero, but A/D converters aren't perfect.

Since John actually wants only about 500Hz bandwidth in his
PLL feedback path, worrying about a 12.5usec latency
implicit in the 1944 sample repeat cycle is probably not a
useful exercise, even if it were real.

Which it is (972 samples' worth, anyway).

Only if you let yourself be jammed into the computational
straight-jacket of the DFT or FFT.

(a) that is what we were discussing, and (b) causality is not only a
problem with DFTs, it's a generic problem common to all digital filters.

ISTM that the main issues with the B-B loop are: (1) gross
PD ripple; (b) the huge and poorly controlled gain of the
phase detector, which will depend critically on the
residual wideband jitter of the two clocks; and (c), that
all the wideband jitter of the VCXO will be aliased down
into the fundamental interval.

Any metastability worries can be got round by reclocking
the PD output from either one of the oscillators, which
won't cause significant extra latency in an 80-kHz loop.
Wrapping the VCXO inside a simple wideband fractional-N
PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of
which ISTM none will accomplish the required long-term
timing stability.)

The residual drift and low-frequency crap could be removed
afterwards, using the bang-bang PD to control a varactor
phase shifter on the 10 MHz sine wave input. The
combination ought to be pretty impressive.

One would be impressed that he'd got it to work, less
impressed by the fact that he hadn't been able to recognise
the superiority of any of the better schemes that have been
proposed here.

Most of which ignore drift. A picosecond is not a long time.

They don't. I've got no idea where you got that idea.

Um, from reading the thread? You need few-ppm analogue stability in all
parameters to get 1 ps stability out of a 100 ns reference period.
Logic slows down with increasing temperature, phase detector offsets
drift, filter components drift, you name it. The more of that stuff you
have strung together, the worse it gets.

My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter
sampling at 155.52MHz and feeding a number cruncher
embedded in a reasonably big programmable logic device. He
mentioned a Xilinx Spartan-6

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/



snip

As for the rest, the 10 MHz will have to be cleaned up in analogue
somehow, because otherwise its jitter will show up in the FPGA's
output--the analogy between DSP and real genuine analogue signal
processing stands or falls by the samples being evenly spaced. Most
of the time that's not such a worry, but for 1 ps timing accuracy,
it most emphatically is.

The samples will be as evenly spaced as the clock edges coming out
of the 155.52MHz VCXO - which will be very evenly spaced indeed.

We hope. That's the problem we're trying to solve, of course.

The fact that 155.52MHz is not a simple multiple of 10MHz is going
to complicate the digital signal processing, which is why you want to
do it a decent-sized and quick FPGA, but that's a number-crunching
exercise, and The A/D converter approach gives you lots of good
numbers to crunch.

Sure. But the ADC's jitter spec is at constant temperature, no?

There will be no "jitter" on the 10MHz waveform - unless the
GSP-disciplining is done very crudely indeed.

Doesn't have to be very crude to be bigger than a picosecond!

I'm old-fashioned - I find anything more powerful than 22V10
a trifle intimidating, though I did some useful stuff with
the PA7024 (which is a more powerful drop-in replacement for
22V10).

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[John Larkin]

On Sat, 27 Sep 2014 13:54:34 -0400, Phil Hobbs
<hobbs@electrooptical.net> wrote:

And the rest??? Doesn't that have NRE design costs?

Not on the same scale at all. One can design a PLL on a napkin in a few
minutes. The parlour tricks are (1) analogue conditioning of the 10
MHz; (2) resampling the divider output to get rid of its jitter and
timing drift; (3) characterization when you're done. All three of those
things still have to be done with the FPGA approach.

The napkin-level analysis suggests that the bang-bang ecl phase
detector thing will probably work. We won't know for sure until we get
an assortment of VCXOs and build a breadboard. That would be a one-off
4-layer PCB with versions of the various circuits, and lots of SMA
connectors for observability.

I think I could Spice the loop dynamics, and estimate jitter, by
abstracting the VCO as an integrator and the phase detector as some
sort of tunable random noise generator. Namely don't try to work at
155 MHz, or Spice with delta-t in the picosecond range.

Well, breadboarding is easier, and we need to do that anyhow.

As for the rest, the 10 MHz will have to be cleaned up in analogue
somehow, because otherwise its jitter will show up in the FPGA's
output--the analogy between DSP and real genuine analogue signal
processing stands or falls by the samples being evenly spaced. Most of
the time that's not such a worry, but for 1 ps timing accuracy, it most
emphatically is.

Not sure which 10 MHz you are talking about, from the bang bang detector
or the signal processing based approach. I'm not sure why there would
be a 10 MHz signal in the signal processing approach.

Because that's what you're locking to, of course.

Yeah, it would be silly to make a PLL that locks to itself.

I'm old-fashioned - I find anything more powerful than 22V10 a trifle
intimidating, though I did some useful stuff with the PA7024 (which
is a
more powerful drop-in replacement for 22V10).

Dangerous Prototypes sells some nice Xilinx XC9572XL CPLD breakout
boards with JTAG headers. The software is free, if clunky, and you can
get a programming cable from Digilent for $50. (You can also build
your
own from published plans.)

Wow! That is an old part and very limited. There are lots better
devices to get familiar with.

Sure. But it was cheap, did the job, and since there's nothing very
special about different CPLDs, there's nothing obsolete about the
knowledge gained.

Sure, any port... but that really wasn't anything remotely appropriate
for the issue we are discussing. It's like saying to get familiar with
the design we are talking about by learning how to use an opamp, a good
first step.

I was responding to Bill, not to you. He was talking about 22V10s.

I actually designed something using a 22V10, a couple years back. It
reformats the data into a serial DAC, on the fly. Just a little
timing, and invert the MSB.


With just the occasional prod, I may get this thread up to 1000 posts!



--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[rickman]

On 9/27/2014 12:58 PM, DecadentLinuxUserNumeroUno wrote:

On Sat, 27 Sep 2014 08:48:53 -0700 (PDT), Bill Sloman
bill.sloman@gmail.com> Gave us:


Inductance isn't necessarily a problem - within limits.


Yeah... like frequency of operation.

That remark you made about data rates and orders of magnitude can be
assigned to your grasp of the effects of inductance at these data rates
and when trying to generate clean modulation constellations.

Your grasp is DOWN a few orders of magnitude. And a couple decades.

It is always nice to see professionals having a technical conversation.
The mutual respect is obvious.

--

Rick

 

[rickman]

On 9/27/2014 1:54 PM, Phil Hobbs wrote:

On 9/26/2014 10:24 PM, rickman wrote:
On 9/26/2014 7:58 PM, Phil Hobbs wrote:
On 9/26/2014 1:57 PM, rickman wrote:
On 9/26/2014 1:13 PM, Phil Hobbs wrote:
On 9/26/2014 10:53 AM, Bill Sloman wrote:
On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John
Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the amplitude
information and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce
overlapped
results (of any length) on every cycle of the 155.52 MHz clock.
So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the
loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

There's no intrinsic 1944 sample latency if you are using an A/D
converter to sample the 10MHz reference sine wave at 155.52MHz.

There's nothing magic about FFTs--each channel is equivalent to a bog
standard FIR filter. The filter has to be causal, so since it's 1944
samples wide, the delay has to be at least half that.

With infinite computational resources you could do a non-linear
least-squares fit of a 10MHz-ish sine wave to anything more than
about
four successive samples - since you can be pretty confident that you
are
looking at a 10MHz sine wave. With a few as 16 samples - if there was
hardly any noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

You keep ignoring drift.


The 10MHz sine wave would be described by four parameters -
frequency,
absolute phase, amplitude and DC offset. The DC offset ought to be
zero,
but A/D converters aren't perfect.

Since John actually wants only about 500Hz bandwidth in his PLL
feedback
path, worrying about a 12.5usec latency implicit in the 1944 sample
repeat cycle is probably not a useful exercise, even if it were real.

Which it is (972 samples' worth, anyway).


ISTM that the main issues with the B-B loop are: (1) gross PD
ripple;
(b) the huge and poorly controlled gain of the phase detector, which
will depend critically on the residual wideband jitter of the two
clocks; and (c), that all the wideband jitter of the VCXO will be
aliased down into the fundamental interval.

Any metastability worries can be got round by reclocking the PD
output
from either one of the oscillators, which won't cause significant
extra
latency in an 80-kHz loop. Wrapping the VCXO inside a simple
wideband
fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM
none
will accomplish the required long-term timing stability.)

The residual drift and low-frequency crap could be removed
afterwards,
using the bang-bang PD to control a varactor phase shifter on the 10
MHz
sine wave input. The combination ought to be pretty impressive.

One would be impressed that he'd got it to work, less impressed by
the
fact that he hadn't been able to recognise the superiority of any of
the
better schemes that have been proposed here.

Most of which ignore drift. A picosecond is not a long time.


My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter
sampling at
155.52MHz and feeding a number cruncher embedded in a reasonably big
programmable logic device. He mentioned a Xilinx Spartan-6

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/

A pretty big hammer to replace a single D-flop!

I could have sworn there was some other stuff in that design... another
d-flop to start (fancy ECL stuff, and expensive)... a rather tricky
filter and bunches more. Most of that gets replaced with logic in the
FPGA, the ADC and a DAC.

man-with-only-a-hammer-alert

The D-flop costs about $5 in unit quantity, which is pretty cheap for an
FPGA, especially since all the programming effort would be amortized
over 8 whole units.

And the rest??? Doesn't that have NRE design costs?

Not on the same scale at all. One can design a PLL on a napkin in a few
minutes. The parlour tricks are (1) analogue conditioning of the 10
MHz; (2) resampling the divider output to get rid of its jitter and
timing drift; (3) characterization when you're done. All three of those
things still have to be done with the FPGA approach.

Methinks he doth protest *too* much. I also think you are hand waving
now.

Actually the need for analog conditioning the 10 MHz is greatly reduced
in the digital approach as this can be done in the digital domain.
There is *no* need to resample anything in the digital approach.

As for the rest, the 10 MHz will have to be cleaned up in analogue
somehow, because otherwise its jitter will show up in the FPGA's
output--the analogy between DSP and real genuine analogue signal
processing stands or falls by the samples being evenly spaced. Most of
the time that's not such a worry, but for 1 ps timing accuracy, it most
emphatically is.

Not sure which 10 MHz you are talking about, from the bang bang detector
or the signal processing based approach. I'm not sure why there would
be a 10 MHz signal in the signal processing approach.

Because that's what you're locking to, of course.

Oh, you mean the reference clock... The DSP can do a lot of "cleaning
up". Once you are in the digital domain this comes without all the
analog vagaries.

I'm old-fashioned - I find anything more powerful than 22V10 a trifle
intimidating, though I did some useful stuff with the PA7024 (which
is a
more powerful drop-in replacement for 22V10).

Dangerous Prototypes sells some nice Xilinx XC9572XL CPLD breakout
boards with JTAG headers. The software is free, if clunky, and you
can
get a programming cable from Digilent for $50. (You can also build
your
own from published plans.)

Wow! That is an old part and very limited. There are lots better
devices to get familiar with.

Sure. But it was cheap, did the job, and since there's nothing very
special about different CPLDs, there's nothing obsolete about the
knowledge gained.

Sure, any port... but that really wasn't anything remotely appropriate
for the issue we are discussing. It's like saying to get familiar with
the design we are talking about by learning how to use an opamp, a good
first step.

I was responding to Bill, not to you. He was talking about 22V10s.


What are the published plans for FPGA programming cables? Are you
talking about the ones that require a parallel port on a PC?

I wasn't talking about FPGAs at all.

/man-with-only-a-hammer-alert

Uh, what were you talking about building then?

I posted the block diagram many lines up in this thread.

Not sure what you are talking about now. I am responding to your comment...

Dangerous Prototypes sells some nice Xilinx XC9572XL CPLD breakout
boards with JTAG headers. The software is free, if clunky, and you can
get a programming cable from Digilent for $50. (You can also build your
own from published plans.)

Are you talking about a parallel port programming cable or what? I
don't see a block diagram.

--

Rick

 

[John Larkin]

On Sat, 27 Sep 2014 14:01:07 -0400, Phil Hobbs
<hobbs@electrooptical.net> wrote:

On 9/26/2014 10:57 PM, Bill Sloman wrote:
On 27/09/2014 9:58 AM, Phil Hobbs wrote:
On 9/26/2014 1:57 PM, rickman wrote:
On 9/26/2014 1:13 PM, Phil Hobbs wrote:
On 9/26/2014 10:53 AM, Bill Sloman wrote:
On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2
skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard
Hoffmann <ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the
amplitude information and run your VCXO from the phase
information"?

Yeah, and the calculations can very easily be done to
produce overlapped results (of any length) on every
cycle of the 155.52 MHz clock. So no need to wait 12.5
microseconds to close the loop.

There's still the 1944-cycle latency, though, which will
make the loop unstable if you try to go much faster. The
good news is that it wouldn't have the grotesque output
ripple of a bang-bang PD, so it wouldn't have to be
filtered as hard.

There's no intrinsic 1944 sample latency if you are using an
A/D converter to sample the 10MHz reference sine wave at
155.52MHz.

There's nothing magic about FFTs--each channel is equivalent
to a bog standard FIR filter. The filter has to be causal, so
since it's 1944 samples wide, the delay has to be at least
half that.

With infinite computational resources you could do a
non-linear least-squares fit of a 10MHz-ish sine wave to
anything more than about four successive samples - since you
can be pretty confident that you are looking at a 10MHz sine
wave. With a few as 16 samples - if there was hardly any
noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

You keep ignoring drift.

The 10MHz sine wave would be described by four parameters -
frequency, absolute phase, amplitude and DC offset. The DC
offset ought to be zero, but A/D converters aren't perfect.

Since John actually wants only about 500Hz bandwidth in his
PLL feedback path, worrying about a 12.5usec latency
implicit in the 1944 sample repeat cycle is probably not a
useful exercise, even if it were real.

Which it is (972 samples' worth, anyway).

Only if you let yourself be jammed into the computational
straight-jacket of the DFT or FFT.

(a) that is what we were discussing, and (b) causality is not only a
problem with DFTs, it's a generic problem common to all digital filters.

Causality is one of those cool, over-riding, simplifying things like
conservation of energy. The ideal lowpass filter, and its analog and
digital Butterworth approximations, is a beautiful example of the
cruelty of causality.

ISTM that the main issues with the B-B loop are: (1) gross
PD ripple; (b) the huge and poorly controlled gain of the
phase detector, which will depend critically on the
residual wideband jitter of the two clocks; and (c), that
all the wideband jitter of the VCXO will be aliased down
into the fundamental interval.

Any metastability worries can be got round by reclocking
the PD output from either one of the oscillators, which
won't cause significant extra latency in an 80-kHz loop.
Wrapping the VCXO inside a simple wideband fractional-N
PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of
which ISTM none will accomplish the required long-term
timing stability.)

The residual drift and low-frequency crap could be removed
afterwards, using the bang-bang PD to control a varactor
phase shifter on the 10 MHz sine wave input. The
combination ought to be pretty impressive.

One would be impressed that he'd got it to work, less
impressed by the fact that he hadn't been able to recognise
the superiority of any of the better schemes that have been
proposed here.

Most of which ignore drift. A picosecond is not a long time.

They don't. I've got no idea where you got that idea.

Um, from reading the thread? You need few-ppm analogue stability in all
parameters to get 1 ps stability out of a 100 ns reference period.
Logic slows down with increasing temperature, phase detector offsets
drift, filter components drift, you name it. The more of that stuff you
have strung together, the worse it gets.

Yeah. Anything with a filter, or an ADC, or a DAC, in the critical
path is going to have serious temperature drift issues.

My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter
sampling at 155.52MHz and feeding a number cruncher
embedded in a reasonably big programmable logic device. He
mentioned a Xilinx Spartan-6

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/



snip

As for the rest, the 10 MHz will have to be cleaned up in analogue
somehow, because otherwise its jitter will show up in the FPGA's
output--the analogy between DSP and real genuine analogue signal
processing stands or falls by the samples being evenly spaced. Most
of the time that's not such a worry, but for 1 ps timing accuracy,
it most emphatically is.

The samples will be as evenly spaced as the clock edges coming out
of the 155.52MHz VCXO - which will be very evenly spaced indeed.

We hope. That's the problem we're trying to solve, of course.

The fact that 155.52MHz is not a simple multiple of 10MHz is going
to complicate the digital signal processing, which is why you want to
do it a decent-sized and quick FPGA, but that's a number-crunching
exercise, and The A/D converter approach gives you lots of good
numbers to crunch.

Sure. But the ADC's jitter spec is at constant temperature, no?

Not just jitter, but aperture drift vs temp. That is generally not
specified. ADCs do often spec input offset vs temp, and it's mediocre
for fast ADCs, which incidentally tend to run hot. We use the
LTC2242-12 at 250 MHz, and we heat sink it from above and below. And
the danged thing costs almost $60.

There will be no "jitter" on the 10MHz waveform - unless the
GSP-disciplining is done very crudely indeed.

Doesn't have to be very crude to be bigger than a picosecond!

An ideal 5 volt p-p 10 MHz sine wave, into a real-world ECL
comparator, will have a slope of 155 uv/ps. If the comparator noise is
10 nv/rthz and we assume a working bandwidth of 2 GHz, the effective
comparator noise is about 500 uv RMS, so the jitter should be a few ps
RMS, which looks OK without further effort. Drift is a bigger concern,
especially if I have an input bandpass filter to remove fuzzies.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[rickman]

On 9/27/2014 2:37 PM, John Larkin wrote:

On Sat, 27 Sep 2014 13:54:34 -0400, Phil Hobbs
hobbs@electrooptical.net> wrote:


And the rest??? Doesn't that have NRE design costs?

Not on the same scale at all. One can design a PLL on a napkin in a few
minutes. The parlour tricks are (1) analogue conditioning of the 10
MHz; (2) resampling the divider output to get rid of its jitter and
timing drift; (3) characterization when you're done. All three of those
things still have to be done with the FPGA approach.

The napkin-level analysis suggests that the bang-bang ecl phase
detector thing will probably work. We won't know for sure until we get
an assortment of VCXOs and build a breadboard. That would be a one-off
4-layer PCB with versions of the various circuits, and lots of SMA
connectors for observability.

What aspect of this design makes it uncertain? Why can't you determine
the feasibility without building one?

I think I could Spice the loop dynamics, and estimate jitter, by
abstracting the VCO as an integrator and the phase detector as some
sort of tunable random noise generator. Namely don't try to work at
155 MHz, or Spice with delta-t in the picosecond range.

Well, breadboarding is easier, and we need to do that anyhow.



As for the rest, the 10 MHz will have to be cleaned up in analogue
somehow, because otherwise its jitter will show up in the FPGA's
output--the analogy between DSP and real genuine analogue signal
processing stands or falls by the samples being evenly spaced. Most of
the time that's not such a worry, but for 1 ps timing accuracy, it most
emphatically is.

Not sure which 10 MHz you are talking about, from the bang bang detector
or the signal processing based approach. I'm not sure why there would
be a 10 MHz signal in the signal processing approach.

Because that's what you're locking to, of course.

Yeah, it would be silly to make a PLL that locks to itself.

I thought he was talking about removing 10 MHz noise from the VCXO
control signal.

I'm old-fashioned - I find anything more powerful than 22V10 a trifle
intimidating, though I did some useful stuff with the PA7024 (which
is a
more powerful drop-in replacement for 22V10).

Dangerous Prototypes sells some nice Xilinx XC9572XL CPLD breakout
boards with JTAG headers. The software is free, if clunky, and you can
get a programming cable from Digilent for $50. (You can also build
your
own from published plans.)

Wow! That is an old part and very limited. There are lots better
devices to get familiar with.

Sure. But it was cheap, did the job, and since there's nothing very
special about different CPLDs, there's nothing obsolete about the
knowledge gained.

Sure, any port... but that really wasn't anything remotely appropriate
for the issue we are discussing. It's like saying to get familiar with
the design we are talking about by learning how to use an opamp, a good
first step.

I was responding to Bill, not to you. He was talking about 22V10s.

I actually designed something using a 22V10, a couple years back. It
reformats the data into a serial DAC, on the fly. Just a little
timing, and invert the MSB.


With just the occasional prod, I may get this thread up to 1000 posts!

Not sure that is something to brag about...

--

Rick

 

On Saturday, September 27, 2014 6:33:53 PM UTC-4, John Larkin wrote:

On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin wrote:


If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.

Consider this:

If we square up the 10 MHz reference, and the 155.52 MHz oscillator
were somehow locked to it, the edges line up at 80 KHz, namely every
12.5 us. So the bangbang phase detector only delivers one bit of
information (namely early/late) 80K times per second. That may be too
noisy to discipline a cheap 155 MHz VCXO.

Why not just use a non-cheap 155.52 MHz VCXO?

If the VCXO is very good you won't need to correct its phase very
often. (In fact you can't--its rock won't let you.)

A 1Hz error at 155.52 MHz is 80fs phase error per 80 kHz comparison
cycle.

If we have a counter mod 1944, to make 80K from 155.52 MHz, assume we
use state 0 to enable the bangbang phase comparison against the 10
MHz. We servo to zero time error. But, as noted, there are other
counter states that, if used to enable the d-flop, are near-misses to
10 MHz reference edges. There are two or three states that are within
+-50 ps, and maybe another 6 or so within about 100 ps.

So, we could do this:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/Multi_Bang_PLL.JPG

It's not hard to add a DAC that applies a bit of +- delay trim in one
differential ECL path, with the 10 MHz leg shown by example. A RAM in
the FPGA can map counter states into DAC codes hence time tweaks. So
we can trim 3 to 10 clock near-misses to be almost spot-on, and
multiply the compare rate accordingly. We can have software control
over which edges we use, and how much to time tweak each one. Then we
can trim the RAM data for minimum jitter.

I was going to have a time trim DAC for temperature compensation
anyhow, so this is almost free. The DAC doesn't need to be super fast,
since the near-miss events are fairly scattered in the 1944-state
space.

That's the time equivalent of adding a ripple-removing waveform to the
phase comparator output.

Doing it for tiny increments at the 10MHz comparator is better than
my initial while-jogging brainstorm of analog ramps for big increments.

Seems promising.

A Q=1e7 low-drift 155.52MHz resonator and some low noise processing would
eliminate a lot of this finagling.

James

 

[Bill Sloman]

On Sunday, 28 September 2014 08:33:53 UTC+10, John Larkin wrote:

On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin
jlarkin@highlandtechnology.com> wrote:

<snip>

I was going to have a time trim DAC for temperature compensation
anyhow, so this is almost free. The DAC doesn't need to be super fast,
since the near-miss events are fairly scattered in the 1944-state
space.

Your "time-trim DAC" probably ought to be an MC100EP195, as has been proposed earlier.

http://www.onsemi.com/pub_link/Collateral/MC10EP195-D.PDF

The catch is visible in Figure 4 of that data sheet. While the part offers a nominally 10psec granularity over a delay range which starts anywhere from 1.65 to 2.75nsec and can be as long as 9.5 to 15.8nsec, the actual delay varies from part to part, and with temperature. The temperature drift is about 15psec/degree Celcius on the longest delay.

If you use the part to set up a mark-to-space ratio at constant frequency and digitise the DC value of the filtered waveform, you can calibrate the delay with considerable precision and very rapidly - when I worked out a scheme it looked as if we could have measured every delay within a few milliseconds, though that was for the MC100E195 which was a 7-bit rather than an 10-bit device.

--
Bill Sloman, Sydney

 

[Maynard A. Philbrook Jr.]

In article <m071qv$95b$2@dont-email.me>, gnuarm@gmail.com says...

On 9/27/2014 12:58 PM, DecadentLinuxUserNumeroUno wrote:
On Sat, 27 Sep 2014 08:48:53 -0700 (PDT), Bill Sloman
bill.sloman@gmail.com> Gave us:


Inductance isn't necessarily a problem - within limits.


Yeah... like frequency of operation.

That remark you made about data rates and orders of magnitude can be
assigned to your grasp of the effects of inductance at these data rates
and when trying to generate clean modulation constellations.

Your grasp is DOWN a few orders of magnitude. And a couple decades.

It is always nice to see professionals having a technical conversation.
The mutual respect is obvious.

I've always said this is the place for the after work bar stop.

Jamie

 

[Maynard A. Philbrook Jr.]

In article <m072bp$ef6$1@dont-email.me>, gnuarm@gmail.com says...

Uh, what were you talking about building then?

I posted the block diagram many lines up in this thread.

Not sure what you are talking about now. I am responding to your comment...

Dangerous Prototypes sells some nice Xilinx XC9572XL CPLD breakout
boards with JTAG headers. The software is free, if clunky, and you can
get a programming cable from Digilent for $50. (You can also build your
own from published plans.)

Are you talking about a parallel port programming cable or what? I
don't see a block diagram.

Yes, pictures do help, draw us one.

Jamie

 

[Phil Hobbs]

On 9/27/2014 3:14 PM, rickman wrote:

On 9/27/2014 1:54 PM, Phil Hobbs wrote:
On 9/26/2014 10:24 PM, rickman wrote:
On 9/26/2014 7:58 PM, Phil Hobbs wrote:
On 9/26/2014 1:57 PM, rickman wrote:
On 9/26/2014 1:13 PM, Phil Hobbs wrote:
On 9/26/2014 10:53 AM, Bill Sloman wrote:
On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John
Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the amplitude
information and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce
overlapped
results (of any length) on every cycle of the 155.52 MHz clock.
So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the
loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

There's no intrinsic 1944 sample latency if you are using an A/D
converter to sample the 10MHz reference sine wave at 155.52MHz.

There's nothing magic about FFTs--each channel is equivalent to a bog
standard FIR filter. The filter has to be causal, so since it's 1944
samples wide, the delay has to be at least half that.

With infinite computational resources you could do a non-linear
least-squares fit of a 10MHz-ish sine wave to anything more than
about
four successive samples - since you can be pretty confident that you
are
looking at a 10MHz sine wave. With a few as 16 samples - if there
was
hardly any noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

You keep ignoring drift.


The 10MHz sine wave would be described by four parameters -
frequency,
absolute phase, amplitude and DC offset. The DC offset ought to be
zero,
but A/D converters aren't perfect.

Since John actually wants only about 500Hz bandwidth in his PLL
feedback
path, worrying about a 12.5usec latency implicit in the 1944 sample
repeat cycle is probably not a useful exercise, even if it were
real.

Which it is (972 samples' worth, anyway).


ISTM that the main issues with the B-B loop are: (1) gross PD
ripple;
(b) the huge and poorly controlled gain of the phase detector,
which
will depend critically on the residual wideband jitter of the two
clocks; and (c), that all the wideband jitter of the VCXO will be
aliased down into the fundamental interval.

Any metastability worries can be got round by reclocking the PD
output
from either one of the oscillators, which won't cause significant
extra
latency in an 80-kHz loop. Wrapping the VCXO inside a simple
wideband
fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM
none
will accomplish the required long-term timing stability.)

The residual drift and low-frequency crap could be removed
afterwards,
using the bang-bang PD to control a varactor phase shifter on
the 10
MHz
sine wave input. The combination ought to be pretty impressive.

One would be impressed that he'd got it to work, less impressed by
the
fact that he hadn't been able to recognise the superiority of any of
the
better schemes that have been proposed here.

Most of which ignore drift. A picosecond is not a long time.


My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter
sampling at
155.52MHz and feeding a number cruncher embedded in a reasonably big
programmable logic device. He mentioned a Xilinx Spartan-6

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/

A pretty big hammer to replace a single D-flop!

I could have sworn there was some other stuff in that design...
another
d-flop to start (fancy ECL stuff, and expensive)... a rather tricky
filter and bunches more. Most of that gets replaced with logic in the
FPGA, the ADC and a DAC.

man-with-only-a-hammer-alert

The D-flop costs about $5 in unit quantity, which is pretty cheap
for an
FPGA, especially since all the programming effort would be amortized
over 8 whole units.

And the rest??? Doesn't that have NRE design costs?

Not on the same scale at all. One can design a PLL on a napkin in a few
minutes. The parlour tricks are (1) analogue conditioning of the 10
MHz; (2) resampling the divider output to get rid of its jitter and
timing drift; (3) characterization when you're done. All three of those
things still have to be done with the FPGA approach.

Methinks he doth protest *too* much. I also think you are hand waving now.

Nope. I've done similar things both ways. What exactly did you not
agree with, and why?

Actually the need for analog conditioning the 10 MHz is greatly reduced
in the digital approach as this can be done in the digital domain. There
is *no* need to resample anything in the digital approach.

You have an exaggerated idea of the timing coherence of ADCs and FPGAs
over temperature, then. Logic slows down significantly with increasing
temperature, and a picosecond is not a long time. You may think I'm
arm-waving, but I haven't seen a lot of carefully supported numerical
estimates from you--just a lot of generalities. You also haven't
addressed my point about DSP standing or falling by the exact equal
spacing of the data samples, which ISTM is fatal to your view.

As for the rest, the 10 MHz will have to be cleaned up in analogue
somehow, because otherwise its jitter will show up in the FPGA's
output--the analogy between DSP and real genuine analogue signal
processing stands or falls by the samples being evenly spaced. Most of
the time that's not such a worry, but for 1 ps timing accuracy, it most
emphatically is.

Not sure which 10 MHz you are talking about, from the bang bang detector
or the signal processing based approach. I'm not sure why there would
be a 10 MHz signal in the signal processing approach.

Because that's what you're locking to, of course.

Oh, you mean the reference clock... The DSP can do a lot of "cleaning
up". Once you are in the digital domain this comes without all the
analog vagaries.

How _exactly_ would you clean up the clock you're locking to in the
digital domain, without depending on the reference or VCXO for
essentially ideal sampling? Analogue bandpass filters, I understand.
AFAICT your proposal is "pay no attention to the man behind the curtain!"

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Kevin Aylward]

"Bill Sloman" wrote in message
news:0ebc042c-dcc6-4fdf-af3a-c819cff51ec9@googlegroups.com...

On Sunday, 28 September 2014 01:22:07 UTC+10, Kevin Aylward wrote:

"Bill Sloman" wrote in message
news:1b775368-61fc-449c-b80b-7ca901bb44cd@googlegroups.com...
On Saturday, 27 September 2014 21:45:31 UTC+10, Kevin Aylward wrote:
"Bill Sloman" wrote in message
news:63c0a9d9-72af-461d-ab28-11b57cd5172e@googlegroups.com...

Interestingly, you highlight a basic problem with the impeding 50Gs/s
optic systems for board level. One approach uses 300 of 200MHz 8bit
ADC
with a interleaved sampler. Its impossible to do this discretely. It
has to be all on chip, e.g. to avoid the huge data-bus problems.

f you want to do it tolerably cheaply. An ECL or an LVDS terminated bus

http://en.wikipedia.org/wiki/Low-voltage_differential_signaling

is perfectly practical, but bulky and not all that cheap.

I know all about LVDS....I think you may not have thought about this
problem yet Bill.

I though about it enough to use ECL buses across the backplane of the
signal-processing crate in our electron beam tester - which worked, but
not
soon enough for us to put it into production in 1991.

I was only referring to the 50Gs/s problem. Board level ECL won't help
with
16 GHz, 4 phase clocks.

LVDS is not as fast as ECL though.

The overall point, is that things that can be done in an IC that just
can't,
realistically be done at board level. Inductance is about two orders less
of
a problem.

Inductance isn't necessarily a problem - within limits.

Ahmmmm...

Having said that, nobody would do stuff on a printed circuit board if they
could do it at chip level - if they could sell enough of the chips to cover
the up-front cost.

A 50 Gs/s, 6 bit ADC is probably saleable at $10k, off the cuff. Maybe even
$50k. Don't need many to make it worthwhile.


Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice