magnetic field

Subject: Re: Steering angle sensor
From: Bernd Felsche bernie@innovative.iinet.net.au
Date: 10/22/04 11:28 PM Eastern Daylight Time
Message-id: <iovo42xvm7.ln2@innovative.iinet.net.au

chump@pobox.com (Chump) writes:

I'm looking to make a steering angle sensor for my data acquisition
system in my race car. I basically need to translate the movement of
the steering wheel into voltage read by the logger unit.

The logger provides a 5v reference signal so I figured I could send
that signal through a potentiometer then back to the unit.

most commerical units available ($$$) use a system of pulleys driven
off of the movement of the steering shaft itself.

some questions -

what type of pot would be good for this application. I understand
audio ones are not linear enough?

You could linearise with a microcontroller; if the potentiometer
has _repeatable_ non-linearity.

Anyone have any idea where I can get different sized pulleys to go on
the end of the pot?

any other tips advice or different ways of doing it?

Optical or reluctance encoding off the steering shaft.

You could also do it "indirectly" by measuring the linear
translation of the steering rack, with potentiometer, linear encoder
using optical, potentiometer, inductive, or capacititative
measurement.
--
/"\ Bernd Felsche - Innovative Reckoning, Perth, Western Australia
\ / ASCII ribbon campaign | I'm a .signature virus!
X against HTML mail | Copy me into your ~/.signature
/ \ and postings | to help me spread!
For curiousity sake.... how much do these commercial units go for? Why?

How linear is linear enough? What are the design requirements for data
accuracy? How often is the data sampled?

There are lots of ways to do this that don't involve pulleys (dark ages?)

Regards,
Brad
 
That certainly matches my experience, which I had
put down to being supplie dfrom a reject batch.

So, what can we do as Radio Hams to prevent such
a problem?

How hot does the whole board have to be raised before
applying a solfering iron? Would a hairdryer do?

"Terry Given" <my_name@ieee.org> wrote in message
news:k1grd.19852$9A.331279@news.xtra.co.nz...
Larry Brasfield wrote:
Hand soldering can be very hard on SMD ceramic capacitors.
The high temperature gradiant created by applying heat suddenly
at one end can fracture the ceramic. This can lead to excess noise
or a tendency to break down at a lower than rated voltage as
moisure gets into the crack(s). The insidious aspect of this kind
of damage is that it can show up in the field, quite some time
after the parts perform alright in initial testing.

This is a VERY good point. Reflow ovens have very well controlled
thermal profiles, slowly ramping temperature to a plateau, holding,
slowly ramping up to final tmep, holding etc. Mostly to avoid this
thermal shock related mechanical failure mechanism. High voltage
ceramics are especially prone to this - hand soldering them is a risky
process.

I once used 2 x 15nF 1000V smt X7R caps in series across an 80-800Vdc
supply for a smps application. During testing one smps failed
catastrophically (two others ran fine). Detailed examination of the
corpse showed a blast pattern radiating outward from one of the caps,
which had ruptured. The resulting mess sprayed directly across the legs
of one of the FETs, thereby toasting the unit. At the time it was
operating at a DC bus voltage of around 400V, so the cap was nowhere
near its rated voltage, more like 20%. One of the guys I worked with had
extensive experience in this area (hi-rel smps hybrids for
il/aerospace), and showed us what went wrong. We immediately replaced
the capacitors, carefully using a manual hot air station, to both
preheat and solder. The units operated continuously into a dead short at
800Vdc, no problems - there were other issues of course, it was a
pre-production protoype, but none of the explosive kind.
 
Airy R. Bean wrote:
That certainly matches my experience, which I had
put down to being supplie dfrom a reject batch.

So, what can we do as Radio Hams to prevent such
a problem?

How hot does the whole board have to be raised before
applying a solfering iron? Would a hairdryer do?

"Terry Given" <my_name@ieee.org> wrote in message
news:k1grd.19852$9A.331279@news.xtra.co.nz...

Larry Brasfield wrote:

Hand soldering can be very hard on SMD ceramic capacitors.
The high temperature gradiant created by applying heat suddenly
--snip--

Folks are starting to experiment with reflow soldering in toaster ovens.
I've read good reports on the web, but have absolutely no personal
experience nor have I even talked to someone who's done it, so I can't
vouch for it. One of these days I'll give it a try, in the meantime you
can search on toaster oven reflow and get a slew of pages.

There's at least one company (www.pcbexpress.com) who'll even make
prototype stencils for your solder paste, although for stuff that's not
too fine you can dispense paste from a syringe.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
 
Have you seen my new soldering iron?
http://www.seattlerobotics.org/encoder/200006/oven_art.htm

w9gb


"Tim Wescott" <tim@wescottnospamdesign.com> wrote in message
news:10qrpaakl83j98d@corp.supernews.com...
Airy R. Bean wrote:
That certainly matches my experience, which I had
put down to being supplie dfrom a reject batch.

So, what can we do as Radio Hams to prevent such
a problem?

How hot does the whole board have to be raised before
applying a solfering iron? Would a hairdryer do?

"Terry Given" <my_name@ieee.org> wrote in message
news:k1grd.19852$9A.331279@news.xtra.co.nz...

Larry Brasfield wrote:

Hand soldering can be very hard on SMD ceramic capacitors.
The high temperature gradiant created by applying heat suddenly

--snip--



Folks are starting to experiment with reflow soldering in toaster ovens.
I've read good reports on the web, but have absolutely no personal
experience nor have I even talked to someone who's done it, so I can't
vouch for it. One of these days I'll give it a try, in the meantime you
can search on toaster oven reflow and get a slew of pages.

There's at least one company (www.pcbexpress.com) who'll even make
prototype stencils for your solder paste, although for stuff that's not
too fine you can dispense paste from a syringe.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
 
OK, so this is basically emulating the reflow process. The only issue with
this is that there is no real temperature control and you can damage both
the board and the components if you are not careful (as is the case with all
soldering).

The technique I use is lots of flux and a soldering iron. It is key to use
flux so that the solder flows properly. Sometimes a microscope is required
and then occasional washing to remove the solidified gunky flux [wash in
ethyl alcohol]. However if you want to solder an IC you can run the
soldering iron along the side of the IC. Slope the board and then run the
soldering iron down the board from the top most pin to the bottom most one
and the solder meniscus will stick/flow with the soldering iron. You will
end up with the last 2 or 3 pins with a bridge which can easily be removed
with solder braid. You do however need to tack the IC down to start off
with so that it doesn't move whilst soldering. I learned this from a very
skilled tech and it works incredibly well. Especially for 25-50mil pitch
QFPs. For Passives, it's a lot of work and the technique given in the link
below may be better if you have lots of them.

**FLUX** is always key though! Water soluble if possible as it's easier to
clean off. Just wash it and wait for it to dry. Don't try and heat it dry
since this can cause steam to form under the solder joints (and the ICs) and
cause adverse pressure. The pressure can cause joints to fail and parts to
crack.

I would also like to point out something else about the technique given in
the link below. Bake out! One real issue in SMT soldering is that IC's
have to be baked out if they've been sitting in a normal environmnet
(humidity) since the epoxy absorbs water. The water then gets heated by the
IR reflow process/oven and can cause the IC to crack. The way around this
is to heat the IC/components gently to above 100 deg C (125 deg C is OK).
This bkes out the water. USually in an industrial process this is done for
about an hour or 2. The IC's are then sealed in a waffle tray and bag with
anhydrous silicone crystals to make sure no water gets reabsorbed. You
shoudl only be wary of this if your IC's have been lying around in a damp
warm atmosphere for a few days. For normal prototyping this is not so much
of a problem.



You can also get the reflow "hairdryer" kinds of devices. These work well
also and are a little bit more controllable than an oven. If you paste as
described by the link below, just heat around the IC/components until the
solder goes shiny. It'll reflow at that point. Let it cool off and check
it.



"w9gb" <onw9mapsgb@no.arrl.spam.net> wrote in message
news:Q_vrd.178384$HA.36082@attbi_s01...
Have you seen my new soldering iron?
http://www.seattlerobotics.org/encoder/200006/oven_art.htm

w9gb


"Tim Wescott" <tim@wescottnospamdesign.com> wrote in message
news:10qrpaakl83j98d@corp.supernews.com...
Airy R. Bean wrote:
That certainly matches my experience, which I had
put down to being supplie dfrom a reject batch.

So, what can we do as Radio Hams to prevent such
a problem?

How hot does the whole board have to be raised before
applying a solfering iron? Would a hairdryer do?

"Terry Given" <my_name@ieee.org> wrote in message
news:k1grd.19852$9A.331279@news.xtra.co.nz...

Larry Brasfield wrote:

Hand soldering can be very hard on SMD ceramic capacitors.
The high temperature gradiant created by applying heat suddenly

--snip--



Folks are starting to experiment with reflow soldering in toaster ovens.
I've read good reports on the web, but have absolutely no personal
experience nor have I even talked to someone who's done it, so I can't
vouch for it. One of these days I'll give it a try, in the meantime you
can search on toaster oven reflow and get a slew of pages.

There's at least one company (www.pcbexpress.com) who'll even make
prototype stencils for your solder paste, although for stuff that's not
too fine you can dispense paste from a syringe.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
 
It is interesting to note that if you look at one of the winners (Robert
Lacoste) of the Circuit Cellar design contest (Steve Ciarcia's embedded
microcontroller design magazine) ... he addressed many of the issues that
you raised.
http://www.circuitcellar.com/library/print/0704/Lacoste_168/index.htm

In fact enough, with a $150 toaster oven and a low-cost controller, he
achieved reflows with good results. A few mfg. were very interested in his
design and approach (Robert has his own consulting company in France).

gb

"crzndog" <cool_blue_dog@nospam_hotmail.com> wrote in message
news:2c-dnRkyHqXFBDPcRVn-tw@comcast.com...
OK, so this is basically emulating the reflow process. The only issue
with this is that there is no real temperature control and you can damage
both the board and the components if you are not careful (as is the case
with all soldering).

I would also like to point out something else about the technique given in
the link below. Bake out! One real issue in SMT soldering is that IC's
have to be baked out if they've been sitting in a normal environmnet
(humidity) since the epoxy absorbs water. The water then gets heated by
the IR reflow process/oven and can cause the IC to crack. The way around
this is to heat the IC/components gently to above 100 deg C (125 deg C is
OK). This bkes out the water. USually in an industrial process this is
done for about an hour or 2. The IC's are then sealed in a waffle tray
and bag with anhydrous silicone crystals to make sure no water gets
reabsorbed. You shoudl only be wary of this if your IC's have been lying
around in a damp warm atmosphere for a few days. For normal prototyping
this is not so much of a problem.

"w9gb" <onw9mapsgb@no.arrl.spam.net> wrote in message
news:Q_vrd.178384$HA.36082@attbi_s01...
Have you seen my new soldering iron?
http://www.seattlerobotics.org/encoder/200006/oven_art.htm

w9gb


"Tim Wescott" <tim@wescottnospamdesign.com> wrote in message
news:10qrpaakl83j98d@corp.supernews.com...
Airy R. Bean wrote:
That certainly matches my experience, which I had
put down to being supplie dfrom a reject batch.

So, what can we do as Radio Hams to prevent such
a problem?

How hot does the whole board have to be raised before
applying a solfering iron? Would a hairdryer do?

"Terry Given" <my_name@ieee.org> wrote in message
news:k1grd.19852$9A.331279@news.xtra.co.nz...

Larry Brasfield wrote:

Hand soldering can be very hard on SMD ceramic capacitors.
The high temperature gradiant created by applying heat suddenly

--snip--



Folks are starting to experiment with reflow soldering in toaster ovens.
I've read good reports on the web, but have absolutely no personal
experience nor have I even talked to someone who's done it, so I can't
vouch for it. One of these days I'll give it a try, in the meantime you
can search on toaster oven reflow and get a slew of pages.

There's at least one company (www.pcbexpress.com) who'll even make
prototype stencils for your solder paste, although for stuff that's not
too fine you can dispense paste from a syringe.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
 
Thanks for your info, it was helpful. I will pass this to my friends
too.

Thanks,

AJ
www.a2zelectronicparts.com
your online sourcing partner


jason@eg3.com wrote:
Archive-name: sci/electronics-search-faq

Electronics Search FAQ - POINTER
http://www.eetoolbox.com/search/index.htm
http://www.cera2.com/search/index.htm
http://www.eg3.com/search/index.htm

Finding Electronic Design Information On The Internet
1998.09.15
------------------------------------------------------------

This FAQ focuses on sources of information useful for electronics
and electronics design. It lists meta resources such as EE search
engines, FAQ's, Web resources, FTP sites, publications, trade
shows, and conferences. It identifies all major EE publications,
and it explains how to use the Internet as a tool for practical
electronic design. Please email suggestions to comments@eg3.com.
Thanks!

------------------------------------------------------------

CONTENTS:
ALL include active WWW links to the relevant resource

* GENERAL SEARCH OVERVIEWS

* THE BIG THREE
-- FAQ's and Technical Reports: Finding Them
-- USENET: Searching for Groups and Searching USENET
-- World Wide Web: Major Search Engines

* OTHER REALLY IMPORTANT EE RESOURCES
-- Conferences: Locating Conferences on EE Subjects
-- FTP Sites: Finding Source Code and Software
-- Mailing Lists
-- Publications: Major EE Publications & Web Resources
-- Smart Semiconductor Search: NEW Search Engine, Searching
ALL major (embedded) chip vendors

* MERITORIOUS EE SEARCH RESOURCES
-- Books, Libraries, Bookstores, etc.
-- DSP Resources
-- EE Hunter: One Interface/Multiple EE Search Engines
-- Embedded Systems Index
-- Industrial Embedded Computing
-- Microcontroller/processor Internet Index
-- Miscellaneous but Meritorious Search Tools
-- News and Sources for EE Related News
-- Realtime and Software Development
-- VTS Buyers' Guides by Topic Area

* INTERNET RESOURCE PAGES
-- Artificial Intelligence
-- Ada
-- Assembly
-- Books
-- C Language
-- C++
-- (Tele)Communications
-- Compilers
-- DOS/Windows
-- Employment
-- Emulators
-- Engineering
-- FAQ's/Tech Rpts.
-- Forth
-- FTP Sites
-- Mailing Lists
-- Networking
-- News
-- Object-Oriented
-- Publications
-- Robotics
-- Shareware
-- Software Eng.
-- USENET
-- WWW Search Engines
-- 411 Marketplace
-- Windows/DOS
 
On 2004-12-20, Jim Thompson <thegreatone@example.com> wrote:
I'm in my usual mode of receiving (Spice) library files from systems
using Linux/Unix/Eunuchs, so paths are a gezillion deep, with *one
file* in each directory :-(

(1) Why in the hell do the Linux/Unix/Eunuchs types do that?
Since no one else has chosen to answer your first question,
I'll make a stab at it. I don't know the details in this
particular case, but I can make an educated guess.

The Unix filesystem can serve as a remarkably good kind of low-budget
database. And when Unix is upgraded, the database system
is upgraded as well, so you don't have to screw around with
waiting for upgrades to match the OS.

This fact has been used by many people to avoid upgrade problems,
so much so that it's now an "idiom" of the "language." Paul Graham
remarks that it was the underlying database used in getting Yahoo
Stores up and running.

Frequently deep directory structures reflect this database-oriented
attitude, just as in many programming languages, there are careful
namespace conventions, so that code I write in Java, for instance,
to do work in projective geometry, is in the package

edu.brown.cs.jfh.geom.projective

even though it could all probably be quite safely in the package "jfh".
Of course, that's only safe until I write a second Java class called
"Project", meaning "this project I'm working on" rather than "Projective
Geometry Tools". Then I get a name clash. So good discipline tells
me I should use the naming conventions to save myself trouble later.

It's sorta like using those .01uF caps across the power supply to
my logic chips, even though it seems to ME as if the first one
at the front of the circuit should do the job for the whole board.
But that's because I don't have (even slightly!) the mindset of
a circuit designer. It's simply good housekeeping of a different
form. In the words of Asterix and Obelix, "C'est une autre culture."

--John Hughes
 
Jon G., it would do you a great benefit if you pay attention to my past,
current, and future posts on matters of automotive technology.

Using formal knowledge coupled with practical experience, I have defeated
the industrio-Detroit complex. They want you to follow their service
procedures which have been developed with the intent to support million
dollar dealerships. Typically, the factory service manual specifies ten
thousand dollars in special tools and perhaps a hundred thousand in capital
shop equipment. Not to mention thousands in ordinary Snap-Ons and Protos.

My methods seldom require more than an insulated screwdriver and 18 gauge
zip (extension cord) with a Mueller on each end. My tool box is mostly
packed with Taiwanese sockets (some bought at Big Lots)and an old rusty
Cresent to round out the assortment.

Learn how to strip wires with a steak knife. Learn how to crimp Radio
Shack connectors with a Vise-Grip. Above all, learn ball peen techniques
in case you don't have a Vise-Grip. Forget all the fancy stuff.

Cars today can be repaired successfully using 1918 methods. Nothing
changed in 86 years.

In dealing with your V.R. problem, all you needed to do to test that
alternator was a jumper. You bypass the regulator by jumping the output to
field. Bring the engine up to fast idle and observe the headlamps. If you
see "flaring", the alternator is good and the regulator is bad. If there
is no change in headlamp brightness, the alternator is bad. Simple.

Nomen (master mechanic - don't call me a tech, for Pete's sake)
 
Subject: >>>DO NOT LISTEN TO PAYPAL POSTS
From: Matt donotlisten@topaypalposts.com
Date: 12/27/04 3:19 AM Eastern Standard Time
Message-id: <XzPzd.10044$Oy2.3568@newsfe1-win.ntli.net

DO NOT LISTEN TO PAYPAL POSTS!

IGNORE MY LAST POST!, IGNORE IT COMPLETELY!

DO NOT PART WITH ANY MONEY!

I have recently been taken in, I have thrown away many spam emails and
ignored many posts before. But the idea that this is legal because people are
knowingly paying to add their name to a list, sounded good!

Since sending the post I have received many emails, and I fear to say that I
have un knowingly managed to get myself into some serious shit!, only sending
the paypal post yesterday I have not heard from the local authorities
although I am expecting them to call, I have however contacted my local
police station myself, who have basically told me that as long as any money
paid to me is returned and I do not accept any of it. That is the best I can
do for now. However a member of the computer crime dept will be in touch
though as he feared I still may have commited other internet related crimes
that I was not aware of.

I do not have the ability to remove my last post, so all I can do to try and
put things right is to send another!
WARNING others of the consequeses you to may face if you respond in the way i
have!
The scheme you got suckered in is VERY old........ At least you had the
courage to fess up........
Brad
 
"The Phantom" <phantom@aol.com> wrote in message
news:9o3qt050o44qiju9okdbtvim06i6hpb9pk@4ax.com...
On Thu, 6 Jan 2005 01:48:37 -0800, "Watson A.Name - \"Watt Sun, the
Dark Remover\""
NOSPAM@dslextreme.com> wrote:


"The Phantom" <phantom@aol.com> wrote in message
news:citpt0pefseqd290tcgheag2v1ir44b1r4@4ax.com...
On Wed, 5 Jan 2005 23:39:15 -0800, "Watson A.Name - \"Watt Sun, the
Dark Remover\""
NOSPAM@dslextreme.com> wrote:


"The Phantom" <phantom@aol.com> wrote in message
news:qp2nt0551477oaivfo6574oshvoc4iac2g@4ax.com...
On Tue, 4 Jan 2005 21:36:26 -0800, "Watson A.Name - \"Watt Sun,
the
Dark Remover\""
NOSPAM@dslextreme.com> wrote:

G

Umm, don't you mean:


-----33u---o---3.3u----o---0.33u---o---gate
| | |
10K 100K 1M
| | |
G G G

In which case it looks like the network will be a substantial
load
on
the drain. So it would then be necessary to put an emitter
follower
on
the drain just to drive the network. Maybe it would be better
to
change
it to: (Or even higher)

----3.3u---o---.33u----o---.033u---o---gate
| | |
100K 1M 10M
| | |
G G G

Seems that the nice thing about using a four section network is
that
each section does 45 degrees. That would make the reactance
equal
to
the resistance. And this simplifies things a bit.

But others seem to favor the lag network over the lead network.

One disadvantage of the lead network is that the transmission
through the network is not
rolled off at high frequencies, increasing the possibility of
parasitic VHF oscillations.

Would you measure the gain from the gate to drain while it's
oscillating so we can see
what kind of performance might be possible with this particular
FET?
Be sure to use a
high impedance probe on the gate.

I have only a 1M 10x probe for my 'scope.

Since you are getting oscillations at such a low frequency, you
can
just put a 10 meg
resistor in series with the probe tip and measure the ac voltage at
gate and drain and
take the ratio. The probe need not be compensated for this
measurement.

I still have a couple problems. I've been watching (Well TV too)
this
thing, and after 40 minutes it's damped out again. I changed the
bias
resistor, and it takes maybe ten minutes to ramp up, then it
osillates
for another 10 or 20 min, then it takes another ten mins to die out.
So
even if I take a measurement, it isn't stable enough to be certain
the
reading is right. I'm still working on getting the bias right.

But if I put a 10M res in series with the probe, I still have a
problem.
The gate resistor is 4.3M, so I've effectively got a parallel
combination that's about 3.1M and as it's barely oscillating w/o the
probe, I would guess it won't osc at all with it. Not to mention
it's
still loading down the gate.

Put a *non-electrolytic* capacitor of a few tenths of a microfarad
in series with the
10 Meg resistor as well, and then the DC bias won't be upset. And you
could use *several*
10 Meg resistors. As long as your scope has enough gain so you can
get a useable
indication you should be able to make the measurement.
I don't think you understand what's happening. The JFET's gate has zero
volts bias across the gate resistor, because it's, well, a FET, not a
BJT. And at the freq we're dealing with here, the few tenths of a uF
will be essentially an open.

I'm thinking it might be better to put a .8M in series with the gate
res
to make a 10:1 divider and take the measurement across that res.

For
BJTs I've found that the lead network seems to have less
waveform
distortion than the lag.
 
Apologies, someone thought I was Phishing - here's the relevant part of
the article:

Through experimentation, I found that using the LPR protocol, if you
send a print job to a print server, and you connect 2 pairs of pins
together on the parallel port, the print server thinks that a printer
is accepting the data, and just streams the job. When the job is
complete, the pattern of the pins match the last byte of the print job
(this is often the Form Feed character (FF - Hex 0c). If you talk LPR
protocol directly, you can persuade it to display what bit pattern you
require.

The connections on the CENTRONICS connector to light an LED are as
follows:

* LED Anode to Pin 2 (Use a resistor in series so you don't blow the
port)
* LED Cathode to Pin 19
* Connect Pin 11 to Pin 20
* Connect Pin 12 to Pin 21

Shandy
 
On Fri, 7 Jan 2005 10:18:28 -0800, "Watson A.Name - \"Watt Sun, the Dark Remover\""
<NOSPAM@dslextreme.com> wrote:

"The Phantom" <phantom@aol.com> wrote in message

Just to make sure we're talking about the same thing, is the circuit
under discussion here?


+9V
|
.-.
| |
33k| |
'-'
|
.----------------------------------------------o----o Vout
| |
| o-------o |
.-. | | |
| | | 4.3M .-. |
| | 330k === | | +------o V out
'-' GND | | |
| '-' |
| +|| | |-
o---/\/\---o---/\/\--o--/\/\----o---||--o--->| JFET MPF102
| | | | || |-
| 330k | 330k | 330k | 10u |
| | | | o----.
| | | | | |
| | | | .-. |
--- 1.0u --- 1.0u --- 1.0u --- 1.0u | | | +
--- --- --- --- 1.0k | | --- 2 caps
| | | | See '-' --- 3200uF
| | | | note | | total
=== === === === below === ===
GND GND GND GNF GND GND

The circuit is essentially the same, except that I've changed the source
bias to three Si diodes in series, and a 1k resistor. I think I'll
lower the 1k even lower, to get the bias point to where the sine wave
swings are more symmetrical.

I suggested using a cap because I think you do in fact have some DC
bias at the gate. It is possible that you are getting some slight
rectification of the AC on the gate (since it's a junction FET), and

With the attenuation of the RC netwrok being 18, I don't see how the
signal swing could be more than 9V / 18 or 1/2V peak-to-peak.
That's why I said "slight". :)

the 10 uF capacitor looks to be an electrolytic (I infer this from the
+ sign on the left plate), and probably has enough leakage to give
some gate bias.

I used a larger cap before, and it was leaky, which upset the bias. I
changed it to 10uF, and the leakage problem went away. I'm not saying
that the 10 uF has none, just that it seems that it's much, much less
than the larger cap. As a precaution, I could change it to a different
cap. However I don't have a 10 uF in a non-'lytic that's anything
reasonable in size. I can parallel a few 1 uFs instead. The reactance
of the 10 uF is about 24k at .67Hz. If I go to a 1 uF the reactance
will be 240k, which is more than 5 percent of the 4.3M gate resistor,
and adds appreciably to the attenuation. In this circuit, with its
damped osc problem, that can make the difference between sustained
oscillation and damped.
In another posting John pointed out that the reactive and resistive components combine
in quadrature, so that the ratio of 240K to 4.3 Meg doesn't by itself indicate what the
change in gain requirement will be for a change to 1 uF. As you pointed out to him in
response, there is the changed phase shift to consider. One really has to analyze the
full phase shift network. The 10 uF and 4.3 Meg you have there now changes the required
gain also, and I thought I would calculate the numbers for the cases we're talking about.

For a network of 4 equal 330K/1uF sections, the theoritical required gain is -18.3878

For the four sections plus the 10uF/4.3Meg the required gain is -20.0796

For the four sections plus the 10uF/4.3Meg and with 11 Megs additional to ground at the
gate, the required gain is -20.7562

For the four sections plus 1uF/4.3Meg the required gain is -21.7218, so changing the 10
uF to 1 uF raises the required gain by 21.7218/20.0796, or 8.2%.

And, of course, the frequency of oscillation changes, about +7.7% from the first to
last case described above.


I wanted you to measure the gain in the circuit as it
is. I suspect leakage from this electrolytic may be causing some of
your instability problems.

Instability? Inability - to sustain oscillations. Before with the
larger leaky cap, I couldn't get the drain more than a half volt above
the source, the leakage was causing the gate to be too 'open' and let
too much current thru the FET. Now, after a half hour,
You've really piqued my interest now. I can't imagine what would aspect of this
circuit would have a time constant on the order of 1/2 hour!

the oscs damp
out and the drain voltage is in the 6 or 7V area, which means that the
FET's gate is doing a good job of 'closing', IOW the neg voltage
(measured between source and gate) is sufficient. This leads me to
conclude that there isn't appreciable leakage into the gate.

(I just grabbed several 10 uF electrolytic caps, with voltage
ratings from 15 to 63 volts. With 5 volts applied I get around 1 uA
of leakage current. You have a DC path to the 10 uF cap through your
330K resistors, and 1 uA of leakage could raise the voltage across the
4.3 Meg resistor to several volts if it weren't for its tendency to
forward bias the gate of the (junction) FET. And, of course, the
leakage changes slowly with time as you apply voltage to the 10 uF
cap. Then, when the circuit is powered down, the capacitor de-forms,
as it were, and the leakage starts out higher and then decreases again
the next time you power it up.)

I put the DMM on .2VDC range across one of the 330k resistors. It
measured under 100mV when I powered on, and after maybe 4 or 5 minutes
it measured under 30mV, when the readings started to fluctuate as it
began oscillating. So choosing the 33mV point, .033V / 330,000 gives
1/10 uA, which when multiplied by 4.3Megs gives .43V, which isn't enough
to upset the bias and is more than the actual value, when the 10uF
finally gets charged up.
Well, I guess that eliminates that issue. My capacitors came out of the parts drawers
and hadn't been used for years, if ever. Yours has been getting plenty of power-up use,
and the leakage has gotten comfortably low. Darn.

This is another disadvantage of the lead form of the phase shift
network that hadn't occurred to me until now. With the lag form, you
would have several smaller caps in series from the drain, with a
resistor at each stage to bleed off the leakage.

I think you got those reversed, above. Lead is CR, lag is RC as in the
schematic above.
Yes. That's what comes of writing this at 3:00 AM.

For the schematic above, it's a disadvantage because the JFET requires
negative bias, hence DC isolation from the lag network. If it were a
MOPSFET, the above schematic could be an advantage because it would be
self biasing, and the four 330k resistors would be part of the bias
network. IOW it would be simpler than the lead network, requiring less
resistors. But yeah, the lead network would be simpler in this case
with the JFET, and less prone to leakage. I started out with the CR
lead network, but didn't have success maintaining oiscillations. So I
switched, probably on recommendation of others here.

The one thing I like about the CR lead netork as far as BJTs go is that
the waveform is less distorted because it's a low pass filter.
But as I pointed out in another post, this also means that you have lots of feedback at
high frequencies. The MPF102 is specified as a VHF amplifier. You could more easily have
parasitic oscillations at some high radio frequency that would upset the operation of the
circuit with the lead topology.

Higher
harmonics at the collector get fed back to the base where they are
cancelled.

I think it's been on long enough to stabilize and the oscs are damped
out. BRB. Well, the oscs are almost damped out, and I measure across
one of the 330ks about 1 to 2 mV, which is about .005 uA leakage.
That's less than .02V across the 4.3M bias resistor. But now that it's
damped out and stable, I'll measure the DCV across the 4.3M. BRB.
Well, the meter is still jumping around zero, but as best as I can tell
it's swinging from neg 10mV to pos 11 or 12mV, which seems to agree
somewhat with the leakage estimate. Of course I didn't include the
DMM's resistance, but I think it's 100M on the 200mV range.

I'm convinced that the leakage isn't a prob, and changing the cap isn't
gonna help. What do you say?? Maybe I should try a 10uF tantalum, but
is that gonna be a help?
Here's a suggestion. Get rid of the components you have in the source lead now. Make
a small stiff, adjustable bias supply by connecting 3 penlight alkaline cell in series.
Put a 100 ohm (or thereabouts) trimpot across the 4.5 volt battery. Connect the most
negative terminal of the battery to ground, and connect the source of the FET to the wiper
of the trimpot. You will have gotten rid of a big capacitor and possible source of long
time constant behavior, and have an easily adjustable, low impedance bias supply.

If you have a 10 uF film cap handy, you might try putting that in
place of the electrolytic you have there now (I'm assuming it is an
electrolytic now).

I would have to use a handful of 1 uFs, but I think I will have a huge
problem with picking up a lot of extraneous noise and hum, since this
huge glob of caps will all be at very high impedance and acting like a
large antenna. :-(

So if
you put a 1 uF capacitor in series with the 10 megs and the
combination in series with the
probe tip, you will not be upsetting the bias, since there won't be
a
DC path through the
combination (neglecting the leakage of the cap, which if it is a
film
cap, will be very
low). I believe your frequency of oscillation is *about* 1 Hz.
The
impedance of a 1 uF
capacitor at 1 Hz is 159K ohms which is negligible compared to the
10
meg resistor, so you
should be able to get a usable signal to the scope.

Again, the capacitor is of no help. The problem is that the
impedance
at the gate is 4.3M, which is so high that if you put a 11M probe on
it,
the added attenuation will cause the FET to stop oscillating.

The AC impedance at the gate is essentially equal to the impedance
of the phase shifting network looking back toward the drain. At the
expected frequency of oscillation, .576 Hz, I calculate it to be
223192 ohms. This AC impedance should not be loaded very much by an
11 meg probe. On the other hand, without the 1 uF non-electrolytic
capacitor in series with the probe, I would expect the 11 megs to
change the DC bias which I am sure you have at the gate.


I'm still having problems with maintaining oscillation. But every
change I make takes the better part of an hour to find out. :-(

The change in calibration factor of
the scope won't matter, since you will measure the amplitude of the
approximately 1 Hz
sine wave at the gate and at the drain with the same probe plus 10
meg
(or more) and 1 uF
in series with the probe tip. Just take the ratio of the amplitude
at
the drain to that
at the gate and that's your amplifier gain under actual operating
conditions.


I'm thinking it might be better to put a .8M in series with the
gate
res
to make a 10:1 divider and take the measurement across that
res.

For
BJTs I've found that the lead network seems to have less
waveform
distortion than the lag.
 
"The Phantom" <phantom@aol.com> wrote in message
news:9f0vt0lgm9tr2laar3i0qtj4ra03d4pv69@4ax.com...
On Fri, 7 Jan 2005 10:18:28 -0800, "Watson A.Name - \"Watt Sun, the
Dark Remover\""
NOSPAM@dslextreme.com> wrote:


"The Phantom" <phantom@aol.com> wrote in message

Just to make sure we're talking about the same thing, is the
circuit
under discussion here?


+9V
|
.-.
| |
33k| |
'-'
|
.----------------------------------------------o----o Vout
| |
| o-------o |
.-. | | |
| | | 4.3M .-. |
| | 330k === | | +------o V
out
'-' GND | | |
| '-' |
| +|| | |-
o---/\/\---o---/\/\--o--/\/\----o---||--o--->| JFET MPF102
| | | | || |-
| 330k | 330k | 330k | 10u |
| | | | o----.
| | | | | |
| | | | .-. |
--- 1.0u --- 1.0u --- 1.0u --- 1.0u | | | +
--- --- --- --- 1.0k | | --- 2
caps
| | | | See '-' ---
3200uF
| | | | note | | total
=== === === === below === ===
GND GND GND GNF GND GND

The circuit is essentially the same, except that I've changed the
source
bias to three Si diodes in series, and a 1k resistor. I think I'll
lower the 1k even lower, to get the bias point to where the sine wave
swings are more symmetrical.

I suggested using a cap because I think you do in fact have some
DC
bias at the gate. It is possible that you are getting some slight
rectification of the AC on the gate (since it's a junction FET),
and

With the attenuation of the RC netwrok being 18, I don't see how the
signal swing could be more than 9V / 18 or 1/2V peak-to-peak.

That's why I said "slight". :)


the 10 uF capacitor looks to be an electrolytic (I infer this from
the
+ sign on the left plate), and probably has enough leakage to give
some gate bias.

I used a larger cap before, and it was leaky, which upset the bias.
I
changed it to 10uF, and the leakage problem went away. I'm not
saying
that the 10 uF has none, just that it seems that it's much, much less
than the larger cap. As a precaution, I could change it to a
different
cap. However I don't have a 10 uF in a non-'lytic that's anything
reasonable in size. I can parallel a few 1 uFs instead. The
reactance
of the 10 uF is about 24k at .67Hz. If I go to a 1 uF the reactance
will be 240k, which is more than 5 percent of the 4.3M gate resistor,
and adds appreciably to the attenuation. In this circuit, with its
damped osc problem, that can make the difference between sustained
oscillation and damped.

In another posting John pointed out that the reactive and resistive
components combine
in quadrature, so that the ratio of 240K to 4.3 Meg doesn't by itself
indicate what the
change in gain requirement will be for a change to 1 uF. As you
pointed out to him in
response, there is the changed phase shift to consider. One really
has to analyze the
full phase shift network. The 10 uF and 4.3 Meg you have there now
changes the required
gain also, and I thought I would calculate the numbers for the cases
we're talking about.

For a network of 4 equal 330K/1uF sections, the theoritical
required gain is -18.3878

For the four sections plus the 10uF/4.3Meg the required gain
is -20.0796

For the four sections plus the 10uF/4.3Meg and with 11 Megs
additional to ground at the
gate, the required gain is -20.7562

For the four sections plus 1uF/4.3Meg the required gain
is -21.7218, so changing the 10
uF to 1 uF raises the required gain by 21.7218/20.0796, or 8.2%.

And, of course, the frequency of oscillation changes, about +7.7%
from the first to
last case described above.
I may put a couple 1 uF mylars in parallel to see if there's any diff,
but I don't think the lower leakage will make any diff.

One thing I found out is that if I put the DMM leads on those high Z
points, it perturbs the oscillations, so if it's oscillating, it tends
to damp out, or if it's damped out, the noise I introduce starts to make
it try to start oscillating again.

I wanted you to measure the gain in the circuit as it
is. I suspect leakage from this electrolytic may be causing some
of
your instability problems.

Instability? Inability - to sustain oscillations. Before with the
larger leaky cap, I couldn't get the drain more than a half volt
above
the source, the leakage was causing the gate to be too 'open' and let
too much current thru the FET. Now, after a half hour,

You've really piqued my interest now. I can't imagine what would
aspect of this
circuit would have a time constant on the order of 1/2 hour!
Well, there's 3200 uF across the source resistor, and the currenmt thru
the FET is only about 100 uA with the 33k drain resistor. The FET
starts out low resistance but as it gets biased it starts to have a
substantial resistance so it slows down the charging of the source byp
cap. It just takes a long time to reach equilibrium. And by that time,
what oscillation it had has then damped out.

[snip]

I put the DMM on .2VDC range across one of the 330k resistors. It
measured under 100mV when I powered on, and after maybe 4 or 5
minutes
it measured under 30mV, when the readings started to fluctuate as it
began oscillating. So choosing the 33mV point, .033V / 330,000 gives
1/10 uA, which when multiplied by 4.3Megs gives .43V, which isn't
enough
to upset the bias and is more than the actual value, when the 10uF
finally gets charged up.

Well, I guess that eliminates that issue. My capacitors came out
of the parts drawers
and hadn't been used for years, if ever. Yours has been getting
plenty of power-up use,
and the leakage has gotten comfortably low. Darn.
I made up a jig with a socket for the FETs. I used two 9V batts, one
for the drain supply and the other for the neg bias on the gate. Below
are the values I got for the Vgs(off). The data sheet uses 15V on the
drain, but I used only 9VDC, so it isn't exactly the same, but close.
It was really difficult to get the 100k neg V adjust pot to stay put at
2 nA (which was 2 mV across a 1M rsistor). I measured a total of 26
MPF102s, some Moto's, some Signetics, some not marked with a logo.

MPF102 (26 total measured) Jan 7, 2005
Vgs(off) @ Vds=9V, Id=2nA (2mV across 1M)
(all voltages negative. Datasheet specs use Vds=15V)

3.56, 3.34, 1.90, 3.46, 2.44, 3.69, 3.97, 3.21, 3.58,
3.44, 2.20, 2.96, 2.39, 4.65, 3.47, 4.06, 3.28, 4.02,
3.76, 2.62, 1.92, 2.85, 3.05, 3.14, 3.55, 2.10**

**The 2.10V is the JFET I have been using for the oscillator.

As you can see, altho there was a somewhat wide variation, most of them
were in the 2 to 4V range.

This is another disadvantage of the lead form of the phase shift
network that hadn't occurred to me until now. With the lag form,
you
would have several smaller caps in series from the drain, with a
resistor at each stage to bleed off the leakage.

I think you got those reversed, above. Lead is CR, lag is RC as in
the
schematic above.

Yes. That's what comes of writing this at 3:00 AM.


For the schematic above, it's a disadvantage because the JFET
requires
negative bias, hence DC isolation from the lag network. If it were a
MOPSFET, the above schematic could be an advantage because it would
be
self biasing, and the four 330k resistors would be part of the bias
network. IOW it would be simpler than the lead network, requiring
less
resistors. But yeah, the lead network would be simpler in this case
with the JFET, and less prone to leakage. I started out with the CR
lead network, but didn't have success maintaining oiscillations. So
I
switched, probably on recommendation of others here.

The one thing I like about the CR lead netork as far as BJTs go is
that
the waveform is less distorted because it's a low pass filter.

But as I pointed out in another post, this also means that you have
lots of feedback at
high frequencies. The MPF102 is specified as a VHF amplifier. You
could more easily have
parasitic oscillations at some high radio frequency that would upset
the operation of the
circuit with the lead topology.
Well, with impedances of megohms and a load resistor of 33k, the
parasitic capacitances make a low pass filter that makes it difficult to
oscillate at those freqs. With BJTs, the usual method is to put a 47 pF
from the collector to base, or an even larger value across the collector
load resistor.

Higher
harmonics at the collector get fed back to the base where they are
cancelled.

I think it's been on long enough to stabilize and the oscs are damped
out. BRB. Well, the oscs are almost damped out, and I measure across
one of the 330ks about 1 to 2 mV, which is about .005 uA leakage.
That's less than .02V across the 4.3M bias resistor. But now that
it's
damped out and stable, I'll measure the DCV across the 4.3M. BRB.
Well, the meter is still jumping around zero, but as best as I can
tell
it's swinging from neg 10mV to pos 11 or 12mV, which seems to agree
somewhat with the leakage estimate. Of course I didn't include the
DMM's resistance, but I think it's 100M on the 200mV range.

I'm convinced that the leakage isn't a prob, and changing the cap
isn't
gonna help. What do you say?? Maybe I should try a 10uF tantalum,
but
is that gonna be a help?

Here's a suggestion. Get rid of the components you have in the
source lead now. Make
a small stiff, adjustable bias supply by connecting 3 penlight
alkaline cell in series.
Put a 100 ohm (or thereabouts) trimpot across the 4.5 volt battery.
Connect the most
negative terminal of the battery to ground, and connect the source of
the FET to the wiper
of the trimpot. You will have gotten rid of a big capacitor and
possible source of long
time constant behavior, and have an easily adjustable, low impedance
bias supply.

I could just use the 9V supply and a resistor and zener to do that,
instead. Same diff and it saves batteries. ;-) Thanks.

[snip]
 
On Sun, 20 Feb 2005 18:37:26 +0000, Fred Abse
<excretatauris@cerebrumconfus.it> wrote:

On Sun, 20 Feb 2005 18:09:59 +0000, Clarence_A wrote:

Massachusetts is so backward they still re-elect Ted Kennedy every
six years.

Maybe because he's one of the few who can spell "Chappaquiddick"

;-)
Or pronounce "Worcester" ;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.
 
On Mon, 21 Feb 2005 07:16:36 -0500, jason b
<electric_chaos.deletemeplease@cogeco.ca> wrote:

snip

I tried this Pete and it seems to be the problem. I moved it towards
the screen and it got worse and visa versa. Thanks alot for the help. ;)

j b
It's hard to believe this is caused by fields from the microwave
power transformer which has a ferromagnetic core for the express
purpose of containing the field within a closed magnetic path of
least resistance. Yes, there is some magnetic field leakage but
for the transformer to be efficient that must be kept small.
There is also, during the on cycle, a countering field generated
by the transformer's load.

In addition, isn't the whole thing encased in steel? The only
magnetic leakage would be through the internal micowave
window and the microwave door. An easy test would be to shield
that door with steel plate or reorient the microwave.

I think a likely source of magnetic interference would be the
wiring in the walls. A microwave oven draws a lot of pulsed
current.
 
"H. Dziardziel" <hdzi@zworg.nospamcom> wrote in message
news:8vpn11lotvforovdmgn2bceni4esofnspp@4ax.com...

It's hard to believe this is caused by fields from the microwave
power transformer which has a ferromagnetic core for the express
purpose of containing the field within a closed magnetic path of
least resistance. Yes, there is some magnetic field leakage but
for the transformer to be efficient that must be kept small.
There is also, during the on cycle, a countering field generated
by the transformer's load.
It may be hard to believe, but as I noted in my other response
here today, it doesn't take that much field to cause a problem
for a CRT.

In addition, isn't the whole thing encased in steel? The only
magnetic leakage would be through the internal micowave
window and the microwave door. An easy test would be to shield
that door with steel plate or reorient the microwave.
Unfortunately, magnetic fields are not that easily contained.
Simply saying that "the whole thing is encased in steel" does
NOT mean that there is zero magnetic field outside the
unit.

I think a likely source of magnetic interference would be the
wiring in the walls. A microwave oven draws a lot of pulsed
current.
It's certainly A likely source, but probably not the only
possible source.

Bob M.
 
On Wed, 23 Feb 2005 13:12:23 -0700, "Bob Myers"
<nospamplease@address.invalid> wrote:

snip


It may be hard to believe, but as I noted in my other response
here today, it doesn't take that much field to cause a problem
for a CRT.
Yes I know,

In addition, isn't the whole thing encased in steel? The only
magnetic leakage would be through the internal micowave
window and the microwave door. An easy test would be to shield
that door with steel plate or reorient the microwave.

Unfortunately, magnetic fields are not that easily contained.
Simply saying that "the whole thing is encased in steel" does
NOT mean that there is zero magnetic field outside the
unit.
But this is supposedly a very small normal leakage from a standard
consumer source, the microwave transformer, encased in steel
located at least several feet away. I did overlook the front
panel controls area on the microwave. That may have large
internal openings. Still, unlikely to be the cause I believe
but -- Ockham's Razor. Regards
..
snip
>
 
jason@eg3.com wrote:

This FAQ focuses on sources of information useful for electronics
and electronics design. It lists meta resources such as EE search
engines, FAQ's, Web resources, FTP sites, publications, trade
shows, and conferences.

* INTERNET RESOURCE PAGES
-- Artificial Intelligence
-- Ada
-- Assembly
-- Books
-- C Language
-- C++
-- (Tele)Communications
-- Compilers
-- DOS/Windows
-- Employment
-- Emulators
-- Engineering
-- FAQ's/Tech Rpts.
-- Forth
-- FTP Sites
-- Mailing Lists
-- Networking
-- News
-- Object-Oriented
-- Publications
-- Robotics
-- Shareware
-- Software Eng.
-- USENET
-- WWW Search Engines
-- 411 Marketplace
-- Windows/DOS
Were those all meant to be links?

NT
 
[sources of information useful for electronics and electronics
design]
jason @ eg3.com

Were those all meant to be links?
NT (bigcat@meeow.co.uk)
They haven't been the other 200 times he's posted it:
http://groups.google.ca/groups?&threadm=sci/electronics-search-faq_1114144353@rtfm.mit.edu
 

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