Clock Edge notation

[Jonathan Bromley]

On 29 Jun 2005 16:20:49 -0700, "dwerdna" <dwerdna@yahoo.com> wrote:

I was after a TK simulation for a common 2-line LCD panel that you
might find on FPGA development boards or the like. I want to plug it
into a VHDL simulation. (I am not so much of a hack that I cant get my
LCD working, I just want a more comprehensive testbench)

Juan Carlos's link shows how you could make a display. The
trickier problem, though, is how to get the data out to your
Tk display. One useful possibility is to get the VHDL simulation to
write the data to a file - then the Tk program can poll the file
and read newly added text out of the end of it. Even better is
to use a pipe interface from VHDL to Tk, but it's tough to get
VHDL to open a pipe or a socket.

Our polar-plot demonstration
http://www.doulos.com/knowhow/tcltk/examples/constellation/
shows a nice way to connect a Tcl/Tk visualisation program to
the ModelSim simulator so that the display shows you the data
that's under the waveform window's cursor. But a 2-line LCD
has internal state information, so that might be more difficult.
And our script works only for ModelSim, although in principle
it could be adapted for any simulator with a Tk front-end.

Our favourite way to do this stuff is to use VHDL text output
to the standard output channel. You can then hook a Tk
program to this channel. Get your VHDL to write a special
prefix to any line of text that should go to the LCD. Then
the Tk script can use any line with this prefix to update
an LCD visualiser, and other text can be displayed on a Tk
text widget and/or echoed to a transcript file by Tk.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jonathan Bromley]

On 30 Jun 2005 09:02:25 -0700, "john" <conphiloso@hotmail.com> wrote:

I am having a problem with the power up "Reset" of the 19-bit counter..
I want it to be "0000 hex", whenever, I power up my system.
It initializes it self to "0000hex" sometimes and sometimes it does not
do that. I have attached the code too. Please advice!

Are you talking about behaviour of the real hardware, or simulation?
Have you simulated? Have you run synthesis? Are you sure that signal
Reset_A is indeed asserted at startup?

Did they teach you about.....

....synthesisable clocked processes?

sec_counter<= "0000000000000000000" When Reset_A ='1' Else sec_counter
+ 1 When inc 'Event And inc= '1' And sec_stop ='0';

.... numeric comparison in the numeric_std package?

sec_stop <= '1' When sec_counter(18)='0'and sec_counter(17)='0'and
sec_counter(16)='0' and
sec_counter(15)='0'and sec_counter(14)='0'and sec_counter(13)='1' and
sec_counter(12)='0'and sec_counter(11)='0'and sec_counter(10)='1' and

sec_counter(9)= '0'and sec_counter(8)= '0'and sec_counter(7)='0' and

sec_counter(6) ='0'and sec_counter(5)= '1'and sec_counter(4)='0' and

sec_counter(3)= '0'and sec_counter(2)= '0'and sec_counter(1)='0' and
sec_counter(0)= '0'
Else
'0';
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Mike Treseler]

jiten wrote:

hi,
my problem is not with the code that how to make it executable.
i've got result without 'while' loop.

You have just answered your own question.

-- Mike Treseler




"Don't confuse me with facts,
my mind is already made up."
-------------------------------------------

 

[Timo Alho]

srinukasam wrote:

hi
i created a memory like below.and i wrote test bench for that.while doing
simulaton with model sim its giving the error..like below..

Fatal: (vsim-3421) Value -97 is out of range 0 to 255.
# Time: 25 ns Iteration: 0 Process: /mux_mem_tb/mut/line__44 File:
/disk/users2/kasam/hds_projects/Controller/controller/hdl/mux_mem_mux_mem_beh.vhd

AND MY TEST VECTORS ARE LIKE THIS
w_addr<= "00000000" after 4 ns,
"10011111" after 24 ns,
...
DESIGN STARTS HERE------------------------
...
use ieee.std_logic_signed.all;
...
ram1(conv_integer(w_addr))<= data_in;
...

I didn't read your desing too carefully so I'm just guessing here.

You have (most likely) defined w_addr to be std_logic_vector. Since you
have included package std_logic_signed, converting std_logic_vector to
integer becomes a signed integer.

Try replacing line
use ieee.std_logic_signed.all;
with line
use ieee.std_logic_unsigned.all;

-timo

 

[Jonathan Bromley]

On 1 Jul 2005 08:22:32 -0700, "john" <conphiloso@hotmail.com> wrote:

Thank you very much for your reply! I tested most of the code with the
real hardware. The reason is that I use Prochip ( Atmel) software for
their chips and their simulation software sucks.

No way can it suck as much as the idea of implementing stuff
without doing some functional simulation first. For small
designs you can use the free version of ModelSim that comes
with Xilinx WebPack, or you can use a free or nearly free
VHDL simulator such as Simili.

I am having a problem with the power up "Reset" of the 19-bit counter..

Now I read your code again, I recognise that the counter's reset
signal Reset_A is not external, but is generated by a state machine;
and this state machine has no power-up reset. So there is no
hope of your circuit ever working reliably. Add an asynchronous
reset to your state registers, and be sure that it is asserted
at startup.

You haven't answered my earlier questions: why, oh why, are
you using that disgusting coding style for state machines and
for clocked processes? People who write working VHDL usually
code their synthesisable clocked processes thus:

process (clock, reset)
begin
if reset = '1' then
registers <= reset_values;
elsif rising_edge(clock) then
registers <= next_state_value_of_registers;
end if;
end process;

You also have some nasty clock-domain-crossing issues because
an output from the state machine is used as an asynchronous reset
to the counter. Only you can decide whether that's OK in your
specific situation, but from a best-practice point of view it stinks.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Hans]

If you are using Modelsim have a look at Tcl sockets for communications and
signalspy, examine and force commands for communication with your DUT. Note
that TK is only supported on Modelsim SE, however, Activestate makes a great
free Tcl/TK interpreter,

Hans.
www.ht-lab.com


"dwerdna" <dwerdna@yahoo.com> wrote in message
news:1120087249.361278.314820@z14g2000cwz.googlegroups.com...

Hi all

I was after a TK simulation for a common 2-line LCD panel that you
might find on FPGA development boards or the like. I want to plug it
into a VHDL simulation. (I am not so much of a hack that I cant get my
LCD working, I just want a more comprehensive testbench)

Thanks

Andrew

 

[Mike Treseler]

Pasacco wrote:

What does this 'X' (forced unknown) imply?
Usually a node driven by an

initialized register or ram.
The node is driven, but the value
cannot be determined by the simulator.

Is it problematic?
Not always, but connect up a reset if you can.

It will make your simulation easier.

Does it "always" meaning that the value is conflicting (from the
beginning)?

Most often it's just unknown from the beginning
until the register gets some know data.

-- Mike Treseler

 

[Mike Treseler]

Mike Treseler wrote:

Pasacco wrote:

What does this 'X' (forced unknown) imply?
Usually a node driven by an
initialized register or ram.
-----------

uninitialized
-- Mike Treseler

 

[Aki Hyyryläinen]

"Pasacco" <pasacco@gmail.com> wrote in message
news:1120328106.499842.276300@f14g2000cwb.googlegroups.com...

hi

During some debugging in my simulation, it is found that one signal is
'X' from the beginning (from time 0) until that signal has some value
(1 or 0).

What does this 'X' (forced unknown) imply?

Could be that you are driving the signal from several places at the same
time; simulator cannot know which value to use and shows X, or it is an
output from say an uninitialised memory model.

Is it problematic?

If you use it to generate other signals, the X will propagate in all those
signals. If you don't use it until it has a known value, there is no
problem.

Does it "always" meaning that the value is conflicting (from the
beginning)?

The value is simply unknown.

-Aki

 

[valentin tihomirov]

How the state machine resgister will be intialized, if there is
no externel RESET available. Please advice!

May be you ask the inventor of such machine? I know that FPGA chips supply
internal reset activating it during configuration time.

 

[Mike Treseler]

Analog_Guy wrote:

Are there any active conferences out there specific to VHDL and digital
design/verification?

I don't think there are enough people
interested to pay for a hall.

Also there are alternatives that
don't involve airport parking and security.

http://www.google.com/search?as_q=vhdl+slides&as_qdr=m6

-- Mike Treseler

 

[Mike Treseler]

Error: Node instance "U1" instantiates undefined entity "hw3a"'

Try compiling hw3a.vhd into your work directory
if you are siming or add it to the file list
if you are synthing.

-- Mike Treseler

 

[Eric Smith]

googlinggoogler@hotmail.com writes:

anyway heres my question, in the below code (found on this group), they
define A and B - I would like to know that if theses are ports? not
pins, how would I just access an individual pin?

You can attach the ports to FPGA pins using attributes or a user constraint
file (UCF). There's a constraint editor in the software that makes this
easy.

or would I just review
the bits at the port kinda like A = 10101111 (if you see that i mean,
similar to in BASIC),

The ports in your example are only one bit each. If you want to deal
with multi-bit data, use std_logic_vector.

Best regards,
Eric

 

[David Bishop]

I see that somebody already posted a fix, but I'll put my own spin on
it.

First, we now have documentation for the fixed and floating point packages:
http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/Fixed_ug.pdf
and
http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/Float_ug.pdf

Also, for VHDL-2002 and VHDL-93 I created special versions of these packages
which synthesize and simulate without using any of the VHDL-2005 tricks:
http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/fixed_pkg_c.vhd
http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/fphdl_base_pkg_c.vhd
These are designed to be compiled into an "IEEE_PROPOSED" library.

I am in the middle of making some changes to these packages. When I am done,
the IEEE (IEEE_PROPOSED) library will have the following packages in it:

fixed_pkg
float_pkg

These packages will be instances of "fixed_generic_pkg" and "float_generic_pkg",
and will look like this (in VHDL-2005):

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.fixed_pkg.all;

package float_pkg is new ieee.float_generic_pkg
generic map (
fp_round_style => round_nearest; -- round nearest algorithm
fp_denormalize => true; -- Use IEEE extended floating
-- point (Denormalized numbers)
fp_check_error => true; -- Turn on NAN and overflow processing
fp_guard_bits => 3 -- number of guard bits
);

Where the type "float" will need to be constrained by the user. "float32",
"float64", and "float128" will be predefined. For "fp16" the user will have to say:

subtype fp16 is float (9 downto -6);

I will create VHDL-93 compatable versions of these packages, but the
"fphdl16_pkg" will not be in the next release.

 

[srinukasam]

hello
thank you very much for giving reply to my problem.
i tried with your solution( user defined function) ,eventough its giving
the same warnings..
here iam giving my test bench also..if you have time please try once (the
souce code i already sent in my first req.)
thank you


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY mux_ge_stim IS

port( input : out std_logic_vector(15 downto 0);
tctrl : out std_logic_vector(23 downto 0);
out_fmux : in std_logic_vector(5 downto 0));


END ENTITY mux_ge_stim;

ARCHITECTURE mux_ge_stim_beh OF mux_ge_stim IS
BEGIN
stimuli: process
begin
input<="0000000000000000" after 0 ns,
"1111111111111111" after 14 ns,
"0000000011111111" after 24 ns,
"1111111100000000" after 34 ns,
"1111000011110000" after 44 ns,
"0000111100001111" after 54 ns;

tctrl<="000000010010001101000101" after 0 ns,
"011001111000100111001101" after 14 ns,
"000100110101011110011101" after 24 ns,
"000000100100011010001100" after 34 ns,
"111110101110100101110000" after 44 ns,
"000001010111100100111101" after 54 ns;



wait;
end process stimuli;

controlrocess
begin
--wait for 3 ns;
-- assert(mux_out="000000")report "z is false at 3 ns" severity
failure;
wait for 5 ns;
assert(out_fmux="000000")report "out_fmux is false at 5 ns" severity
failure;
wait for 10 ns;
assert(out_fmux="111111")report "out_fmux is false at 15 ns" severity
failure;
wait for 10 ns;
assert(out_fmux="111100")report "out_fmux is false at 25 ns" severity
failure;
wait for 10 ns;
assert(out_fmux="000011")report "out_fmux is false at 35 ns" severity
failure;
wait for 10 ns;
assert(out_fmux="101010")report "out_fmux is false at 45 ns" severity
failure;
wait for 10 ns;
assert(out_fmux="100110")report "out_fmux is false at 55 ns" severity
failure;

wait;
end process control;
end mux_ge_stim_beh;
----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY mux_ge_tb IS
END ENTITY mux_ge_tb;

--
ARCHITECTURE mux_ge_tb_stru OF mux_ge_tb IS

component mux_ge_stim
port(
input : out std_logic_vector(15 downto 0);
tctrl : out std_logic_vector(23 downto 0);
out_fmux : in std_logic_vector(5 downto 0));

end component;
component mux_ge
port(
input : in std_logic_vector(15 downto 0);
tctrl : in std_logic_vector(23 downto 0);
out_fmux : out std_logic_vector(5 downto 0));

end component;


signal input:std_logic_vector(15 downto 0);
signal tctrl:std_logic_vector(23 downto 0);
signal out_fmux:std_logic_vector(5 downto 0);

BEGIN
stimuli : mux_ge_stim port map(input,tctrl,out_fmux);
mut: mux_ge port map(input,tctrl,out_fmux);
END mux_ge_tb_stru;

configuration mux_ge_tb_config of mux_ge_tb is
for mux_ge_tb_stru
for stimuli:mux_ge_stim
use entity work.mux_ge_stim(mux_ge_stim_beh);
end for;
for mut: mux_ge
use entity work.mux_ge(mux_ge_str);
end for;
end for;
end mux_ge_tb_config;

 

[Ralf Hildebrandt]

srinukasam wrote:

I designed a mux which gives multiple outputs. but at the time of
simulation with model sim iam getting some warning with generate command.
And my testbench is working for my design.the only problem is warning.i
want to get rid of those warnings.pls help me.

Warnings..

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).

Do you read my answers or do I post into a black hole?

If possible: Don't try to convert any signal of a type, that may be 'U',
'X', 'W', 'Z' or '-' (e.g. std_(u)logic_(vector), signed, unsiged) to
integer, because the integer data type cannot carry such values. Convert
the integer to the more complex type instead.

Another option may be to convert any signal, that is to be converted to
integer first to bit_vector. Because the type bit is eigther '1' or '0',
it can be converted to integer everytime. Conversion to bit_vector does
not output such warnings.


And again - yes - AGAIN! Shall I repeat it? *AGAIN*!
Do /not/ use

USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

but take

use ieee.numeric_std.all;

instead, because the first two libraries are not standard libraries.

Ralf

 

[Ralf Hildebrandt]

methi wrote:

entity shifting is
generic ( left : integer );
Port ( shift_in : in std_logic;
clk_input : in std_logic;
shift_out : out std_logic);
end shifting;

architecture Behavioral of shifting is

signal shift_register : std_logic_vector ( (left-1) downto 0 ):=
(others => '0');

begin


process(clk_input)
begin
if rising_edge(clk_input) then
shift_register <= shift_register( (left-2) downto 0 ) & shift_in;
shift_out <= shift_register(left-1);
end if;
end process;

end Behavioral;

While doing generic map and port map of this components instantiation,
I dont want to assign a fixed value to "left".
I need my "left" changing every time another signal "h" changes

What hardware may provide a 3-bit shift register as well as a 3000-bit
shift register? A 3000-bit shift register I guess... ;-)

I tried doing this in the generic map:

generic map ( left => h)

But this gives me an error.

Shure, because generic parameters have to be fixed at compile time.

Any ideas about how I can do this?

Model a shift register wide enough for your worst case. (Note, that then
everytime all these filpflops will be included.)

Additionally model a multiplexer, that selects the shift_out bit out of
these flipflops. The multiplexer has to be controlled by an input signal
(similar to your "left" parameter).


Ralf

 

[Jim Lewis]

Analog_Guy wrote:

Are there any active conferences out there specific to VHDL and digital
design/verification?

It looks like HDLCon doesn't exist anymore.

HDLCon became DVCon. Focus is now HDL + HVL, so VHDL
is one of the topics as is the larger picture of verification.

There is also DesignCon (with a West, East, and Euro flavors).
Historically its focus was on the physical design side and has
been slowly adding tracks on design and verification, however,
there are not any VHDL specific tracks.

I would review past conference topics to see which meets
your needs best.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[valentin tihomirov]

signal shift_register : std_logic_vector ( (left-1) downto 0 ):= (others
=> '0');

Natural std_logic_vector range is (1 to length). It is up to you, just some
std functions may malfunction on you vectors.

if rising_edge(clk_input) then
shift_register <= shift_register( (left-2) downto 0 ) & shift_in;
shift_out <= shift_register(left-1);
end if;

I would expell the shift_out line from the procedure as you risk to infere a
FF there, writing it at clk edge. The subject have been answered by others -
you have to allocate a register of sufficient length at compile time and
consume the output from the proper register's cell (addressed by some
integer index input).

 

[Ralf Hildebrandt]

methi wrote:

entity shifting is

Port ( shift_in : in std_logic;
clk_input : in std_logic;
left : in integer;
shift_out : out std_logic);
end shifting;

I am not able to synthesize this because:

signal shift_register : std_logic_vector ((left-1) downto 0 ):= (others
=> '0');

This signal delcaration is giving me a synthesis error...It says that
left needs to be a constant instead...

Any other method to work around this idea?

No other method, but a different description is needed. As I told you,
you need to model a shift register and a multiplexer. For synthesis it
is often a good option, to model such things in an explicit way.

Ok, what is a multiplexer? A real simple description is

process(sel,shift_vector)
begin
case sel is
when 0 => shift_out<=shift_vector(0);
when 1 => shift_out<=shift_vector(1);
....
end case;
end process;


As you can see, this description becomes ugly, if there are a lot of
possible options.

Then there may be the following option (but I am not shure if this will
synthesize well - just test it):

process(sel,shift_vector)
begin
for N in 0 to 99 loop -- assuming a 100 bit shift register
if (N = sel) then
shift_out<=shift_vector(N);
end if;
end loop;
end process;

You may extend this to a size determined by a generic parameter.


Ralf