Clock Edge notation

what about this 'struct' solution: no in, no out, no hassle!

type data_t is record
d1 : std_logic;
d2 : std_logic;
d3 : std_logic;
d4 : std_logic;
end record;

entity MY_ENT is
....
data: inout data_t;
....

ajahn wrote:
Hi,
I just want to know if I missed something...
If you have a toplevel entity with say a bus of single std_logic
signals of inout mode and want to use this within a component, you
can't really combine the signals to a std_logic_vector... right? That
means you have to use the single inout signals on the component as well
and use the toplevel entity signal names as actuals for the component
instantiation.
Two reasons:
- if you use a signal assignment to map the signals into a vector, its
only one direction...
- u can't use array aggregates as actuals, beause they're not locally
static, so a concatenation of type data => d4 & d3 & d2 & d1 would
not work...
Click to expand...
no, but you workaround:
signal data_in: std_logic_vector(3 downto 0);
signal data_out: std_logic_vector(3 downto 0);
begin
....
data_out <= d4 & d3 & d2 & d1;
din1 <= data_in(0);
....
--instanciation:
....
data_out=>data_out,
data_in=>data_in,
....


I prefer the 'record' solution, but some tools don't seem to !

Do you guys agree or did I miss a possibility?
Cheers
Andreas
Click to expand...
 
ajahn wrote:

If you have a toplevel entity with say a bus of single std_logic
signals of inout mode and want to use this within a component, you
can't really combine the signals to a std_logic_vector... right?

- if you use a signal assignment to map the signals into a vector, its
only one direction...
- u can't use array aggregates as actuals, beause they're not locally
static, so a concatenation of type data => d4 & d3 & d2 & d1 would
not work...
Click to expand...
Using ports of type inout is often not a good way in deeper hierarchy of
the design. Split every inout signals into one signal for input and one
for output direction.

Ralf
 
janbeck@gmail.com wrote:

Hi all, I need some help, if anyone has the time to explain what I am
doing wrong

I am trying to use the fixed point package fixed_pkg and am having
trouble with synthesis

I have a process with just a few lines of code that seems to need
forever to map - it wont finish even over night on a 3Ghz machine.

I am using Synplify Pro with Xilinx ISE.
Click to expand...
My test case for the fixed point packages uses Synplify Pro.

I have removed all the code lines from the process that do not seem to
make a difference with this problem.

Here is the code snippet that causes me trouble (all variables are
declared like):
shared variable m1: sfixed (32 downto -32) := to_sfixed (50, 32, -32);
Click to expand...
Yipe! a 64 bit shared variable! Sure you need it that big?
How about just a variable? Or better yet a signal.
This will synthesize, but I doubt it would run at more tha 0.7 MHz.

process(src_clk_1)
begin
if (src_clk_1'event and src_clk_1='1') then
ykm2 := ykm1;
ykm1 := yk;
yk := to_sfixed (arg => to_integer(unsigned(val1)),
left_index => 32,
right_index => -32,
round_style => false,
overflow_style => true);
uk := to_sfixed (arg => to_integer(unsigned(val2)),
left_index => 32,
right_index => -32,
round_style => false,
overflow_style => true);
Click to expand...
Filled with lots of zeros

m1 := resize(ykm2*p11, m1'high,m1'low);
m2 := resize(ykm1*p21, m2'high,m2'low);
m3 := resize(uk*p31, m3'high,m3'low);
Click to expand...
64 bit multiply (3 of them), producing a 128 bit result which needs to
be cut down. This is a lot of 18x18 multiplier blocks.

m4 := resize(m1+m2, m4'high,m4'low);
t1 := resize(m3+m4, t1'high,t1'low);
Click to expand...
Two 64 bit adders.

m1 := resize(t1*t1, m1'high,m1'low);
Click to expand...
Another multiply

p11 := resize(p11 - m1, p11'high,p11'low);
end process;

Any insight or pointers would be appreciated
Click to expand...
1) cut down the size of your variables. 64 bits is a great deal of
precision that is probably what is slowing down Synplify.
2) If you are going to resize to 64 bits after every operation, then
a multiply with two 32 bit inputs will work as well and make much less
logic.
 
anil wrote:
I have a question relating to Clocks. If i have a clock with
frequency Fs . I want to generate another clock with frequency N*Fs.
How is this done in VHDL.

or is it that i must have another clock input with this frequency.

also suggest me which method is the better of the above two .
Click to expand...
IMHO, if you're targetting an FPGA, you're better of having your highest
frequency clock come straight in - you can multiply clocks using hard IP
blocks (DCMs, PLLs etc), but certainly in the case of Xilinx DCMs, you
increase the jitter, sometimes quite dramatically. It's a lot easier to
divide the clocks down afterwards.

The other point is that you can write a synthesisable desciption of
something that will multiply your clocks, but practically this would
require particularly special attention to layout and design (ie feedback
etc), and would generally be considered to be a Bad Idea (Depends too
much on PVT and requires very careful analysis in order to both specify
and get what you want). This would not so much be a pure 'vhdl'
description though, as it would be dependant on factors like the
physical delay of LUTS and routing.

my 2c
Jeremy
 
On 17 Jun 2005 05:30:38 -0700, charles.elias@wpafb.af.mil wrote:

I have been thinking of making generic gates for a library. These
would be single N-input gates. A gate is easy enough to code, but I
have not been able think of a way to do this using a generate or other
loop statement so that a single component declaration would work for
each gate type (and, or, etc.). An instantiated component would look
like this (I might put some extras in to set polarity of each input and
the output):

and_gate_1 : and_gate
generic map( N => 3 ) -- positve
port map( input => gate_1_in, -- std_logic_vector(0 to N-1)
output => gate_1_out ); -- std_logic
Click to expand...
Why the generic? How about an unconstrained input port? Then
you don't need to specify N, but simply connect up any old vector
to the input and the gate will automatically re-size itself:

entity poly_and_gate is
port (A: in std_logic_vector; Y: out std_logic);
end;
architecture P of poly_and_gate is
begin
process (A)
variable result: std_logic;
begin
result := '1';
for i in A'range loop
result := result and A(i);
end loop;
Y <= result;
end process;
end;

Or, probably even better, a function with an unconstrained
input parameter.

Verilog, of course, has the reduction operators that do the
same thing, to say nothing of its primitive gates.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On 17 Jun 2005 07:38:48 -0700, charles.elias@wpafb.af.mil wrote:

Charles,

Excellent idea!
Click to expand...
Thanks for the nice reply, but I forgot to mention the bad news:
some synthesis tools don't understand unconstrained ports -
mostly the big-bucks ASIC tools whose origins are firmly rooted
in Verilog, which has no such concept. For these tools you must
either use a function with an unconstrained parameter, or supply
a generic in the way you suggested.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Weng Tianxiang wrote:

Hi,
I need a standard function name to do (Bool and Vector).

For example:

A(2 downto 0) <= (C1 and B1(2 downto 0))
or (C2 and B2(2 downto 0))
or (C3 and B3(2 downto 0));

C1, C2 and C3 are boolean.
Click to expand...
You will find the new versions of the packages at:
http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html

Looking at what has been done here, you can't do this with
"boolean_vector", but you can do this with bit and bit_vector.
 
Pasacco wrote:

Problem is that it is not working when the 'execution process below' is
rising edge clocked.
Click to expand...
Consider running a simulation and looking
at the waveforms. Sounds like clock
and data are changing on the same tick.
Maybe you need a wait state.

-- Mike Treseler
 
Charles,
The vhdl-200x working group has a proposal for exending standard
logic operators as unary reduction operators. It would work as follows:

signal Y : std_logic ;
signal A : std_logic_vector(7 downto 0) ;

Y <= and A ;

or more exciting:

EvenParity <= xor Data ;

Cheers,
Jim


I have been thinking of making generic gates for a library. These
would be single N-input gates. A gate is easy enough to code, but I
have not been able think of a way to do this using a generate or other
loop statement so that a single component declaration would work for
each gate type (and, or, etc.). An instantiated component would look
like this (I might put some extras in to set polarity of each input and
the output):

and_gate_1 : and_gate
generic map( N => 3 ) -- positve
port map( input => gate_1_in, -- std_logic_vector(0 to N-1)
output => gate_1_out ); -- std_logic


Suggestions?

Best regards,

Charles
Click to expand...

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
On 17 Jun 2005 05:30:38 -0700, charles.elias@wpafb.af.mil wrote:


I have been thinking of making generic gates for a library. These
would be single N-input gates. A gate is easy enough to code, but I
have not been able think of a way to do this using a generate or other
loop statement so that a single component declaration would work for
each gate type (and, or, etc.). An instantiated component would look
like this (I might put some extras in to set polarity of each input and
the output):

and_gate_1 : and_gate
generic map( N => 3 ) -- positve
port map( input => gate_1_in, -- std_logic_vector(0 to N-1)
output => gate_1_out ); -- std_logic



Why the generic? How about an unconstrained input port? Then
you don't need to specify N, but simply connect up any old vector
to the input and the gate will automatically re-size itself:

entity poly_and_gate is
port (A: in std_logic_vector; Y: out std_logic);
end;
architecture P of poly_and_gate is
begin
process (A)
variable result: std_logic;
begin
result := '1';
for i in A'range loop
result := result and A(i);
end loop;
Y <= result;
end process;
end;

Or, probably even better, a function with an unconstrained
input parameter.

Verilog, of course, has the reduction operators that do the
same thing, to say nothing of its primitive gates.
Click to expand...
As Jonathan mentioned (later thread), to make it synthesizable
you need a generic, but its addition is trivial (sorry for starting
in the middle, but the code I want to copy from is here):


entity poly_and_gate is
generic ( N : integer );
port ( A : in std_logic_vector(N-1 downto 0); Y: out std_logic);
end;

Then to parameterize your instantiation use 'length:
and_gate_1 : and_gate
generic map( N => gate_1_in'length ) -- positve
port map( input => gate_1_in, -- std_logic_vector(0 to N-1)
output => gate_1_out ); -- std_logic

Cheers,
Jim
P.S.
Don't forget as I mentioned in my earlier post, we plan to
add this sometime during one of the VHDL-200X revisions.
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
Pasacco wrote:

That is correct that clock and data transit at the same time. Thankyou
for comment.
Click to expand...
You are welcome.

BTW, how is the coding style of the 3rd process in FSM above. 3rd
process is for combinational execution (generating output) block.
Click to expand...
Consider combining everything into one clocked process.

Is it okay to use falling edge clock in the process ?
Click to expand...
Your life will be simpler with one clock.
For FPGAs flops come free with the gates.
Might as well use them.

Compared to non-clock or rising edge clock, what is advantage or
disadvantage ? Maybe falling edge clock in 3rd process is not a good
coding :)
Click to expand...
The advantage of using one clocked process is
that all outputs are automatically registered.
There is no internal wiring to worry about.
It just works, and you don't have to think so much.

-- Mike Treseler
 
I am woundering if you have completed your project
and if you are satisfied with it .
 
Vikas,
i'm new to VHDL, my aim is to overload airthmatic and shift operators
for STD_LOGIC_VECTORs/STD_LOGICs.
Don't do this. Shift operators are planned to be added in
Click to expand...
the next revision of VHDL. Let your vendor know that you
want this feature supported (we need their funding to support
our standards work).

For now, use concatenation for shifting:

signal ShiftLeft, uShiftRight, sShiftRight, A : std_logic_vector(7 downto 0) ;
signal ShiftInVal : std_logic ;

ShiftLeft <= A(6 downto 0) & '0' ;
uShiftRight <= '0' & A(7 downto 1) ; -- unsigned
sShiftRight <= A(7) & A(7 downto 1) ; -- signed


In general I prefer concatenation as it allows me also to shift
something in while shifting a direction:
ShiftLeft <= A(6 downto 0) & ShiftInVal ;

It also works for arrays of arrays.


I'm confused which library package i should consult, wether to use
STD_LOGIC_SIGNED or STD_LOGIC_UNSIGNED. what's the nature of
STD_LOGIC_VECTOR, How it behaves i.e. SIGNED or UNSIGNED??.
Click to expand...
My rules are:
For all new designs
* use the types signed and unsigned from package numeric_std
for math operations.
* package std_logic_unsigned and std_logic_vector may be used
for testbenches that apply algorithms to non-numeric types
(such as incrementing address).
* When I am lazy, I will use std_logic_unsigned for
incrementers/decrementers
* Never use std_logic_signed. If you mean signed, you are clearly
doing math and should be using the type signed because of the value
of it documenting your design.

** note, use numeric_std_unsigned for new designs once it is
standardized.

** note some who follow a more rigorous design methodology, forbid
the use of std_logic_unsigned and math with std_logic_vector.
In this case you would use types unsigned or signed and use
type conversions (mainly similar to casting) where necessary.


For updating older designs
* Try to stay consistent with the packages that that design uses.
Use std_logic_arith only if it is used in the rest of the design,
otherwise, use numeric_std as noted for new designs.


Best Regards,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
ALuPin@web.de wrote:

And yet I cannot see any output registers for the "best speed"
optimized one. I can go down the hierachy until I see the
RAM block but there are no additional flipflops between the
RAM block and the outputs of the SCFIFO.
Click to expand...
Speed/Area constraints are just hints.
If you know what you want, skip the wizard
and write your own code.

-- Mike Treseler
 
yaseenzaidi@NETZERO.com wrote:

I have a situation where Post Translate timing is significantly
different from behavioral/RTL simulation. I am not not speaking of
simple delays, the outputs/data are different than what they should be.
Click to expand...
Gate level sims are more complex than functional.
I expect your error is here.
However, if static timing is ok and the thing works
I wouldn't bother performing or debuging a gate sim.

-- Mike Treseler
 
Hi Andre,

The outp[ut registers are an optional component in the M4K blocks.

To illustrate this, create a dual-port memory using the Plug-in manager. At
a certain point you get to the page where you can select which ports to
register. One of them is the Q output. These output registers are inside
the M4Ks, so you won't see them. If you look at the parameter with which
the SCFIFO instantiates the M4K, you should see a difference.

If not...

Best regards,



Ben
 
This is common to have a gate-level problems whi;le the design is working on
the board.
If your design is not high-speed and your statis timing analysis is alright,
then running gate-level simulation is really almost meaningless, as this is
FPGA and not ASIC.

Vladislav

<yaseenzaidi@NETZERO.com> wrote in message
news:1119327236.103890.308980@g14g2000cwa.googlegroups.com...
Greetings,

I have a situation where Post Translate timing is significantly
different from behavioral/RTL simulation. I am not not speaking of
simple delays, the outputs/data are different than what they should be.


What is interesting is that the design works on the FPGA board.
I implemented a serial port in loopback mode in Xilinx, if I type a
character on Hyperterm I get the same returned from the FPGA.

I have set timing constraints but to no effect.

YZ
Click to expand...
 
yaseenzaidi@NETZERO.com wrote:

Greetings,

I have a situation where Post Translate timing is significantly
different from behavioral/RTL simulation. I am not not speaking of
simple delays, the outputs/data are different than what they should be.


What is interesting is that the design works on the FPGA board.
I implemented a serial port in loopback mode in Xilinx, if I type a
character on Hyperterm I get the same returned from the FPGA.

I have set timing constraints but to no effect.

YZ
Click to expand...
In a real design where correctness matters, I wouldn't discard
this discrepancy without taking a closer look...

It could mean that your design does't work at worst case timing,
or it could hide some unwelcome asynchronous feature or incorrect
clock domain crossing etc...
A couple of characters through Hyperterminal is not a good "proof"
of design correctness.
If you use Quartus, you could take a look at the Design Assistant's
report, or investigate the problem a bit further.
A potential error might create havoc much later.

Bert Cuzeau
 
jiten wrote:
hi,
i've found that + operator doesn't work with std_logic values.
it works only with std_logic_vector.
Click to expand...
Not even. You'd need Synopsys' std_logic_unsigned (eg) which use
is deprecated (with reasons) against numeric_std which requires
signed or unsigned types.

i've checked if a,b & c are std_logic values than
c <= a + b; gives compile time errors.
why it happens?
cann't we use + operator with single std_logic values.
regards
jitendra.
Click to expand...
Lots of things the VHDL Jedi needs to learn ;-)

Unlike Verilog, VHDL is strongly typed.

Btw, I think a one bit adder is just an xor, so
c <= a xor b;
is probably what you're looking for.
Alternatively, you could use one-bit vectors (0 downto 0).

Bert Cuzeau
 
jiten wrote:

if (rst='1') then
mplr := (others=>'0');
st <= idle;
i <= "000";
elsif (clk'event and clk='1') then
case st is
when idle => tmc := "00000000" & mc;
st <= add;
when add => if (mp(conv_integer(i))='1') then
mplr := mplr + tmc ;
end if;
st <= shift;

when shift => tmc := tmc(14 downto 0) & '0';
i <= i + 1;
st <= add;
if (i = "111")then
-- from here i want that i shoud come out of
states, bcoz i've got the output.
Click to expand...
Seems to me, that you are thinking like sofware and you are looking for
a similar thing to the ANSI C "break;".

VHDL case has different behavoir than ANSI C switch. You don't need a
"break;".

Just test
if (i /= "111") then
and do there all the stuff you need and don't use an else clause. ->
Nothing will then be done in the state "shift".



Generally: Don't program VHDL! Model hardware with it. VHDL is not a
software language.

Ralf
 
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