Clock Edge notation

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[Allan Herriman]

On 29 Sep 2004 07:06:36 -0700, ALuPin@web.de (ALuPin) wrote:

[snip]

Then I changed "rising_edge(Clk)" back to "Clk'event and Clk='1'" and
I got the same result as in the original design.

So why is there a difference at all?

http://groups.google.com/groups?selm=3d63466b.185967697%40netnews.agilent.com

Regards,
Allan

 

[Martin Bishop]

In my experience, if you use anything other than Std_Logic(_Vector) for IOs
from a device your Vital simulation wont work; plain fact. Therefore Xilinx
are simply following "best" practice.

Equally, I would take a lot of persuasion that any types beyond
Std_Logic(_Vector), Std_ULogic (for resolved signal implementations),
Unsigned, Signed, enumerated types, and perhaps a few "specials" have a
serious role in synthesis.

Martin

"mep" <mpe@metanic.dk> wrote in message
news:41574395$0$238$edfadb0f@dread14.news.tele.dk...

Hi there
I teach classes in VHDL and uses Xilinx Webpack as a tool for this.
Unfortunately, the new module wizard always set type std_logic for
I/O-lines. This makes it very hard to learn the students about the other
types.
Does anybody know if this can be changed - and how?
Mogens

 

[Mike Treseler]

Niv wrote:

We would then write the state machine so that it passed through all
spare states after reset before reaching the "idle" or "start" state.
We would use binary encoding.
This forces the synth to produce only N FF's, with all possible states
declared and used, albeit fleetingly for the spare states.

Interesting.

Do you do the same sort of thing
for counters with unused values?


-- Mike Treseler

 

[Nicolas Matringe]

ALuPin a écrit:

Hi,

I have a PLL in my design. This PLL generates two clocks which are
used in my design.
Now I want to cut these clocks from the design and generate my own
clocks for simulation.
The testclocks 'l_sdram_clk' and 'l_sdram_clk_90' are going to run
when the PLL is locked so that I use the 'l_pll_locked' signal to
enable the generation of the clocks.
I try that by using GENERATE. But the simulation shows that
'l_sdram_clk' and 'l_sdram_clk_90' remain undefined.

generate allows to instantiate different components or pieces of code
depending on a generic or constant parameter. It is evaluated at
elaboration time, not during run time so you can't use it for what you
want to do.

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 

[Jim Lewis]

Nachiket,
It is called VHDL-200X. You can find more information at:
http://www.eda.org/vhdl-200x

Cheers,
Jim Lewis

is there any effort to extend VHDL into something similar to what's
happening in the Verilog world..i.e. systemVerilog. it would be really
unfortunate if VHDL just got replaced with some Verilog clone without
a fight from the VHDL camp.

nachiket.

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Sylvain Munaut]

Hi

Another thing which has confused me is: If I wish to write an
entity(below) for Spartan II, does the programmer worry about
generating the signal for "clk" input? Or simply connect it to the
correct pin of FPGA and I should get the signal of 200MHz?

I'm not sure I understand the question but :

The CLK input MUST be provided by external means like a Crystal Oscillator and must be directed
to an appropriate pin on the FPGA.

Then you must use constrainsts so that your VHDL nets that should be connected to the outside are
locked onto the right pads of the FPGA (depends on your board design).


Sylvain

 

[Nicholas Weaver]

In article <415e8938$0$2840$cc9e4d1f@news-text.dial.pipex.com>,
Leon Heller <leon_heller@hotmail.com> wrote:

The "WAIT..." statement is not synthesisable. You simply need a counter
(ripple counter will do) to divide the clock down to 400 Hz or so. Write the
VHDL for a toggle flip-flop and string lots of them together - not very
elegant but it should work.

I know XST will infer a counter from

reg [31:0] ctr
always @(posedge clk)
begin
reg = reg + 1
end

Far easier than stringing flops to get a binary countdown.

--
Nicholas C. Weaver. to reply email to "nweaver" at the domain
icsi.berkeley.edu

 

[Ken Smith]

In article <eb4ab45b.0410021355.1acfcb@posting.google.com>,
Mike Delaney <mmdst23@pitt.edu> wrote:

Does anyone have any suggestions on how to do Logs and Powers?
Part of the design I'm working on has "log(1 + B^d)", and we're pretty

If this is the only log and power you need to do and if either "B" or "d"
is a constant, I'd be suggest trying to do the whole function in one go.
I'd be very tempted to come up with a function that is sort of close and
then use a Taylor series to fix it.

If "d" is the only variable, breaking it into 2 ranges, one for each sign
of "d" would be a natural thing to do.

--
--
kensmith@rahul.net forging knowledge

 

[Laurent Gauch]

Hi Bruce,

I am interesting to know if you have a full description of the SN74ACT8990.

Since I am working on a USB2.0 JTAG emulator, I would be able to write
the VHDL code of the SN74ACT8990 very quickly if I know the complet
description of the SN74ACT8990.

Regards,
Laurent
www.amontec.com

Bruce Sam wrote:

I am considering using EPM7128 to implement SN74ACT8990,which is a
JTAG TAP controller.And the work is so hard and interesing.Is it
possible what I do?Are there VHDL code has been implemented JTAG TAP
controller?

 

[Laurent Gauch]

Bruce Sam wrote:

Hi Laurent,
SN74ACT8990 is linked
here:http://www-s.ti.com/sc/ds/sn74act8990.pdf.

There are no way to write VHDL code with the sn74act8990.pdf.

The sn74act8990.pdf is not a complet description of sn74act8990, but
only a description of the device interface. All other things you need to
describe VHDL register level of the sn74act8990 is skipped in the
sn74act8990.pdf. With sn74act8990.pdf you are using a black-block.

Larry
www.amontec.com

 

[Hans]

After receiving a few emails I have now placed a compiled version of the
8086 processor on my website.

http://ht-lab.com/freecores/cpu8086/cpu86.html

Regards,
Hans.
www.ht-lab.com

"mep" <mpe@metanic.dk> wrote in message
news:41575306$0$284$edfadb0f@dread14.news.tele.dk...

Hi Hans,
Yes to me there is. I am working at the technical university of Denmark
and
we have for many years used a 8088-based system to teach microprocessor
design. The hardware is worn out and have to be replaced by a FPGA-based
board. But all our examples, projects, drills etc. are based on this
system.
To make the transition easier, we are looking for an IP-core, which can
execute 8088-compatibel code and make it possible to use the old
"software"
at least for a period..

Is your core for sale?

Mogens

 

[Laurent Gauch]

gda wrote:

what are the properties of cisc and risc?

go back to the classroom !

 

[Pieter Hulshoff]

ALuPin wrote:

process(Reset, Clk_90)
begin
if Reset='1' then
l_valid_h1 <= '0';
l_valid_h2 <= '0';
l_valid_h3 <= '0';

elsif rising_edge(Clk_90) then
l_valid_h1 <= l_valid_48;
l_valid_h2 <= l_valid_h1;
l_valid_h3 <= l_valid_h2;
end if;
end process;

process(l_valid_h2, l_valid_h3)
begin
l_valid_90 <= '0';

if ((l_valid_h2='1') and (l_valid_h3='0')) then
l_valid_90 <= '1';
end if;
end process;

The 3 FF approach is a good one, but you should create the i_valid_90 on the
clock as well. Just put the combinatorial statements within your clocked
process, and I think it should work just fine.

Regards,

Pieter Hulshoff

 

[Brian Drummond]

On Tue, 5 Oct 2004 22:32:46 -0400, "Analog Guy" <analog_guy@hotmail.com>
wrote:

As part of my testbench, I want to verify that unused I/O are tri-stated (as
per design). Some of the
unused I/O are vectors, specified as STD_LOGIC_VECTOR with various sizes.

An alternative approach would be to weakly drive the I/O bus from your
testbench (i.e. with 'H' then 'L' instead of '1' then '0') and see what
you get. Tri-stated elements will be resolved to the weak drive signal,
others will not.

This approach would also work in hardware, while testing for 'Z'
obviously will not!

- Brian

 

[Pieter Hulshoff]

Viswan wrote:

I am designing a hardware unit that can be used as an interface to a
sensor and the FPGA on which my rest of the hardware exists. I have
to generate some synchronizing clock signals at certain delays, to
start the communication.

for example 2 siignals are needed to be sent to sensor as follows.
data is bidirectional.

data <---> ----| |-------
|----------|
|-----| |----|
sclk <---- --| |----| |-----

I thought it would be better if I could generate it using delays..
ANother idea I have in my mind is to use counters and generate these
waveforms. But i doubt if there is any other good idea for this.

Do you have any information on how stable your clock should be? I think it's
probably wisest to put a clock crystal on your board, and either use that
clock or derive a clock from that clock. Creating one directly from logic
within your FPGA will most likely not give you a workable clock, unless you
have a very very loose timing specification.

Regards,

Pieter Hulshoff

 

[Ralf Hildebrandt]

Mike Treseler wrote:

I prefer to use direct instances for
structure and generic constants for options.

This is impossible, if one tries to insert a number of instances of a
subcomponent and this number depends on the generic parameter - but in
general: ACK.



O.k., many thanks to you and to Pieter for help!
Ralf

 

[Alan Fitch]

"Thomas Stanka" <usenet_10@stanka-web.de> wrote in message
news:ef424d2c.0410062226.3b320d6d@posting.google.com...

Hi all,

I'm searching a good overview about all changes between those three
(or at least two of them).
Does anyone know good urls or books where I can find all
differences?
I know, that the faq contains implicite some of them, but I like to
have a complete overview.

I'm pretty sure there was a site containing all the changes between
87
and 93 some years ago, but couldn't even find that site when
searching
it now.

bye Thomas

If you can buy or borrow the 2002 LRM it lists the changes made
between
that and VHDL 2000 Edition. If you get VHDL 2000 Edition it lists the
changes from VHDL 93, and so on.

Our latest VHDL Golden Reference Guide contains a summary of the
differences between the language versions

http://www.doulos.com/webshop

regards

Alan

--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.

 

[Paul Uiterlinden]

Analog Guy wrote:

Per my search of the newsgroup, I tried: IF (test = (test'RANGE => 'Z'))
THEN

The actual warning message from ModelSim is:

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
operand, the result will be 'X'(es).

You might see this warning, but it is not caused by the IF statement, as
it does not contain any arithmetic operand.

To get the line number in the warning message, put the following in your
modelsim.ini file (one line):

AssertionFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I File:
%F Line: %L\n\n"

It's probably already there, commented out.

As for your original question: the test should work, but you must be
sure that there are no other drivers overriding the Z value of any bit.

Paul.

 

[Jim Lewis]

Paulo,
Actually, as a working group member, I have seen
significant progress. Proposals have to be made,
analyzed, and then integrated into the standard.
Four months ago, most were just conceptual proposals.
Now most of the proposals have detailed analysis
associated with them and many have been reviewed.

IEEE standards working groups do not get any support
from IEEE or IEEE-SA. 90% of the work done by a
working group is done on a volunteer basis.
While many members come from EDA companies, many others
do not. Some people get supported by their company to
spend time participating and others do it in their
spare time (taking away from their family).

Bottom line, if you want standards to move at a faster
pace, you need to volunteer. You need to earn the right
to complain. If you are not happy with the direction a
standards group goes, you need to participate, otherwise,
again, you have no right to complain. People working
on standards are not claravoint and may not think of the
great idea you have - unless you either share it or
help develop it by participating.

The final step in getting the standard done is to
integrate the proposals into the standard. This is work
that is typically done by one individual (to ensure
continunity). Unfortunately the amount of time it takes
implies that it is not feasibile to do this on a voluntary
basis - as a result, since we are not funded by IEEE,
we also need to raise funds to support this effort.

Best Regards,
Jim Lewis
co-team leader VHDL-200X Fast Track
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

It seems like this they haven't had any progress since 4 months ago!
This new standard is so overdue!!!

Anyways what is VHDL 2002?? Where can I find what is exactly new with
this standard??

- Paulo Valentim

Jim Lewis <Jim@SynthWorks.com> wrote in message news:<10lrs5e3mbmvv50@corp.supernews.com>...

Nachiket,
It is called VHDL-200X. You can find more information at:
http://www.eda.org/vhdl-200x

Cheers,
Jim Lewis



is there any effort to extend VHDL into something similar to what's
happening in the Verilog world..i.e. systemVerilog. it would be really
unfortunate if VHDL just got replaced with some Verilog clone without
a fight from the VHDL camp.

nachiket.