Clock Edge notation

[Alex]

Hi,

The software approach is obvious in here . The thing is that you don't
go out of the state machine
- simple implement some idle(dummy) state.
In your case it won't make a problem as you have already have 2
flops(unless you want to use on-hot coding), so forth state
will be fine.
p.s. VHDL is not a programming language- it is descrptive one
Regards,
Alex

if (rst='1') then
mplr := (others=>'0');
st <= idle;
i <= "000";
elsif (clk'event and clk='1') then
case st is
when idle => tmc := "00000000" & mc;
st <= add;
when add => if (mp(conv_integer(i))='1') then
mplr := mplr + tmc ;
end if;
st <= shift;

when shift => tmc := tmc(14 downto 0) & '0';
i <= i + 1;
st <= add;
if (i = "111")then
-- from here i want that i shoud come out of
states, bcoz i've got the output. i m coming out by taking one more
state. is there any other way of coming out from the state machines
without taking one more state. of course 'exit' doesn't work here.

--

Using Opera's revolutionary e-mail client: http://www.opera.com/mail/

 

[Mike Treseler]

dwerdna wrote:

I'm trying to create a selection of files for a testbench, but the
compiler is failing on the brackets.

Declare an array of files type and an instance, something like:
type selection_t is array(1 to 4) of file;
variable vec_rd_file : selection_t;
file vec_rd_file(1) : text open READ_MODE is "ReadF1.txt";
file vec_rd_file(2) : text open READ_MODE is "ReadF2.txt";

-- Mike Treseler

 

[Mike Treseler]

Mike Treseler wrote:

Declare an array of files type and an instance, something like:
type selection_t is array(1 to 4) of file;
variable vec_rd_file : selection_t;
file vec_rd_file(1) : text open READ_MODE is "ReadF1.txt";
^

syntax error

Sorry, I got it wrong.
Arrays of files are illegal.

-- Mike Treseler

 

[info_]

methi wrote:

Hi,

I have some questions regarding the following piece of code...

In the AHDL code, the following variable is declared as below:

HDET_REG : DFF;

Its been used in the code as follows:

HDET_REG.CLK = DIGRESET;
HDET_REG.D = VCC;
HDET.REG.CLRN = !HDET;

Probable typo :
HDET_REG.CLRN = !HDET;

Sounds like :

process (DigReset, Hdet)
begin
if Hdet ='1' then
HDET_Reg <= '0';
elsif rising_edge(DigReset) then
HDET_Reg <= '1';
end if;
end if;
end process;


Asynchronous rising edge detector.
Bad practice. Probably from a very small PLD, old design.

Bert Cuzeau

 

[info_]

Have you checked the documentation waveform that Quartus II
Megawizzard does generate for you to illustrate the behavior
of the generated macro ?

Simulating is still definitely a good idea...
however, I think you are changing rdreq just at the clock's rising edge,
which might be legit if you don't have any delta delay (which is hard
to assess in a macro model) but which makes the waveform harder to
interpret anyway.
I suggest you change your inputs at the clock's inactive (falling) edge.

Bert Cuzeau

 

[Jonathan Bromley]

On 24 Jun 2005 07:36:14 -0700, praveen.rajaretnam@gmail.com wrote:

Hi all, how can we implement logarithm of a number in VHDL.
any tips ??? thanx

A normaliser counts leading zeros and extracts the mantissa,
so giving the logarithm to within 6dB. Typically you can
then do table lookup on the top few bits of the normalised
result, to get some more accuracy.

Obviously, it depends on the precision you need.

Standard methods such as Taylor series and CORDIC may also
be useful if you want really high precision. Once again,
it's MUCH easier if you normalise the number first, so that
you only need to find the log of a number in the range
0.5 to 1.0
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[David Bishop]

praveen.rajaretnam@gmail.com wrote:

Hi all, how can we implement logarithm of a number in VHDL.
any tips ??? thanx

You'll find one is the floating point algorithms:

http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html
The file is:
http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/fphdl_base_alg_pkg.vhd

 

[Dave Higton]

In message <1119665201.750733.191160@f14g2000cwb.googlegroups.com>
"Neil" <zjneil@gmail.com> wrote:

Hi, All,
While programming UART, I encounter a problem: if the baud rate is
9600, how to calculate the ferequence for receive/transmit data of
UART? I get a expression: freq = 9600/(systemClock * 16). but where
the 16 comes from? why it is 16? How to get...? Thank you!

It's conventional to clock the receiver at 16 times the baud rate,
to make it easy to sample the bits close to the middle. Remember
that the receiver is not normally synchronised to the transmitter.

There's no need to clock the transmitter faster than 1 times (or 2
times if you need one and a half stop bits, but no-one has used
that in years), but you only usually want to provide one clock rate
for both Rx and Tx.

Dave

 

[Mirko Liss]

praveen.rajaretnam@gmail.com:

Hi all, how can we implement logarithm of a number in VHDL.
any tips ??? thanx

Use the shift-and-add Algorithm or maybe the variant used in
D E Knuth volume 1.

 

[Duane Clark]

Brandon wrote:

I have a set of generated instances and I'd like to OR all their ports
of type std_logic. The structures are generated according to a
parameter, so I can't manually write out the logic equation, which
would be quite tedious anyways. How could I go about doing this?

I think that it's probably possible to use a for loop and do an OR
accumulation. I've compiled the following successfully:

SNIP

Yep, that works fine. I have used that exact technique before. The
synthesis tool I have used handled it just fine.

 

[Ralf Hildebrandt]

blarg wrote:

I am having an issue with synthesizing the code below using Synopsys
design analyzer.

---
clkproc_12: process(clk)
begin

for index in 0 to num_stg12_sad_regs-1 loop
if (rising_edge(clk)) then

Whoops - what is this?

You can eighter
* have an outside for-generate statement having inside a process, to infer a
number of similar ressources (described by the process)
XOR
* have a process beeing edge-sensitve and inside the edge-sensitve if-clause a for-loop
doing some stuff

In other words: Edge-sensitive statements are not allowed inside a for-loop by your
synthesis tool - and I guess by any other synthesis tool.


Ralf

 

[Kim Enkovaara]

nitinyogi80@yahoo.com wrote:

the "end process" statment is executable and Modelsim lets me place a
breakpoint on the "end process" statment. However if I have the
following code:

P3: process (A , B)
begin
result <= ('0' & A)+('0' & B);
end process;

the "end process" statement is not executable and hence I cannot place
a breakpoint on the line. Does anybody have any idea why this happens.

Have you tried to use lower optimisation setting, for example start with
-O0. That should preserve all the information for debugging.

--Kim

 

[Kim Enkovaara]

nitinyogi80@yahoo.com wrote:

Hi,
Kim, your suggestion worked! You were right, it was doing some
kind of optimizations. When I tried "vcom -O0 adder.vhd", all "end
process" statments are now executable. I'll have to see now whether

Modelsim at least in SE versions merge the processes in some cases
with higer optimisation levels. You can see that for example if you
try to force something inside merged process. The path contains merged
word i.e.

change /foobar/#MERGED#proc1,proc2,proc3/var 16#0

--Kim

 

[Mike Treseler]

Kim Enkovaara wrote:

Modelsim at least in SE versions merge the processes in some cases
with higer optimisation levels. You can see that for example if you
try to force something inside merged process. The path contains merged
word i.e.

change /foobar/#MERGED#proc1,proc2,proc3/var 16#0

Yes. This is very common with multiple synchronous
processes on the same clk,rst,enable.

This is one reason I started merging processes
myself at the source level.

-- Mike Treseler

 

[Mike Treseler]

ALuPin@web.de wrote:

After the FIFO is empty I could reset my design within my testbench.

Yes, just push more data in using the testbench.

But the contents of the RAM should also be resetted or rather
be initialized again with zeros.

That's not what will happen on the bench.
A fifo can only access data it has pushed in.
You want 'U's elsewhere to make sure your
head and tail counters are working ok.

-- Mike Treseler

 

[Jonathan Bromley]

On 28 Jun 2005 15:48:08 -0700, "--Ross" <rossandbeth@hotmail.com>
wrote:

Hi,
Can I access a std_logic signal attribute that is the signals name as a
string?

Yup: my_signal'SIMPLE_NAME (or 'PATH_NAME or 'INSTANCE_NAME).

Say for example I had a proceduure that did a check on various signals
and I wanted to 'report' the condition and the signal name; then I
would have to have two inputs, the signal and a string of the signal
name. (?)

No. A signal-class formal parameter is a reference to a real
signal, so life is good for you. Try this:

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity name_attrib is end;

architecture A of name_attrib is
signal SIG: std_logic;
procedure P (signal S: in std_logic) is begin
write(output, "simple_name = " & S'simple_name & CR & LF);
write(output, "path_name = " & S'path_name & CR & LF);
write(output, "instance_name = " & S'instance_name & CR & LF);
end;
begin
process begin
P(SIG);
wait;
end process;
end;

Yet more stuff that's easy in VHDL but the Verilog folk didn't
think of
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Mike Treseler]

jiten wrote:

can anyone tell me while loop is synthesizable with synplify tool or
not?

Since a synthesis process loops all by
itself, every clock tick, I can't
imagine how you would use a while loop.
Let's see the code.

Sequential statements execute in zero time.
They form a testable logical description,
not a real-time program thread.

If you want a time delay, use a counter variable.

-- Mike Treseler

 

[Mike Treseler]

Ruby wrote:

Now my problem is since the circuit is too big(too many data lines),
I don't want to draw the schematic.

I wouldn't either.

So Can I write the VHDL code for
the circuit

Yes. And a testbench for it to
eliminate logical errors.

and get a netlist from the code. If I can do that, then I
can run the pathmill to find the critical path of the circuit and so as
the max. delay.

Yes, a static timing analysis is the easiest way
to find the critical paths.

-- Mike Treseler.

 

[Mike Treseler]

Ruby wrote:

What is the testbench and how to write it, Could you please mention in
more detail.

You need a vhdl tutorial, a book and a simulator to get started.
Google this group for details. Do some research of your own.

I guess to get nelist, vhdl code should be structural.

No. You need synthesis software.
You need to learn to write and test
vhdl code for synthesis.
Here is an example:
http://home.comcast.net/%7Emike_treseler/uart.vhd

And a testbench:
http://home.comcast.net/%7Emike_treseler/test_uart.vhd

Good luck.

-- Mike Treseler

 

[Egbert Molenkamp]

But the while loop is not terminating!
Notice that 'i' is a signal. That means that it is updated after a delta
delay.

Assume the initial value of 'i' is 0.
Then in the while the line i <= i+ 1; is executed
But it remains 0 (it will update after a delta delay).
so in the next loop iteration i is still 0.
I think during simulation you did not see any progress.

Egbert Molenkamp

"jiten" <jitendra.scorpio@gmail.com> wrote in message
news:1120120426.864655.260630@g47g2000cwa.googlegroups.com...

hi the code is like this

process(cnt,tmp,rst)
begin
if rst='1' then
cnt <= "0000";
tmp <= "000";
i <= 0;
else
w : while i< 8 loop
tmp <= tmp+1;
cnt <= cnt+1;
i <= i + 1;
end loop w;
end if;
end process;