Clock Edge notation

"Weng Tianxiang" <wtx@umem.com> writes:
I fully agree with your opinions

and I don't understand why you agree with all reasons stated by Kai.

"Just make sure that you are using a PLL to extract and stabilizing
the receive clock."
Click to expand...
IIRC, I said I'd agree with the reasons, *not* with the conclusions
that were drawn. Kai was pointing out (although indirectly) that the
recovered clock is unreliable.

The additional effort to switch back and forth between internal and
recovered clock is IMHO pointless since in either case you'd have to
maintain the internal clock. Why not use it to begin with? Behavior of
the chip will be much more predictable, too. I wouldn't want to think
about verifying the two-clock-system.

I guess working with all sorts of 10GB SerDes stuff in the past made
me read more into the message that I was following up to than what had
actually been written. Sorry about that.

Best regards,
Marcus
 
ALuPin wrote:

But in my situation I have a clock that is 7-8 times faster.
Please clarify ...
Click to expand...
Please reread my posting.
The idea is as clear as I have time to make it.

-- Mike Treseler
 
I just reread your post. Where does the 16 MHz clock come from? Rereading
Andre's original post, he only has 16 MHz (sic) data. ;-)
Cheers, Syms.
"Mike Treseler" <mike_treseler@comcast.net> wrote in message
news:3cl11lF6kuiooU1@individual.net...
ALuPin wrote:

But in my situation I have a clock that is 7-8 times faster.
Please clarify ...

Please reread my posting.
The idea is as clear as I have time to make it.

-- Mike Treseler
Click to expand...
 
Here's an example of saving or wasting output
registers by matching or mixing reset schemes:

http://home.comcast.net/~mike_treseler/var_synth.vhd
http://home.comcast.net/~mike_treseler/var_synth.pdf

-- Mike Treseler
 
Its already part of the standard. If your tool is up-to-date is supports the
example given in your link.
(http://www.eda.org/isac/IRs-VHDL-93/IR1077.txt).
Make sure to enable VHDL 2002 mode, if required

Egbert Molenkamp

"Peter Ballard" <pballard@ozemail.com.au> wrote in message
news:9d5509fa.0504191917.4df11a59@posting.google.com...
Hi all,

I don't like the way that port types "buffer" and "out" can't connect,
and in fact the issue was officially raised in 1994, in Issue Request
1077 (http://www.eda.org/isac/IRs-VHDL-93/IR1077.txt).

With a bit of googling, I can't find any more information on this IR,
except that it was assigned low priority in the minutes of a 1995
meeting.

Is this issue request still unresolved?

Is it possible to find a list of all issue requests, and their status
(accepted, rejected or unresolved).

Thanks in advance.

--
Peter

p.s. if you feel the need to reply by email, replace "ozemail" with
"radlogic" to get my work email. And put "Peter" in the 1st line to
get thru the spam filter.
Click to expand...
 
-- Concatenation of Low and High to form 32 Control Word
Data32_Out <= unsigned(data_out_high & data_out_low); -- ERROR IS IN
THIS LINE...
Click to expand...
-- just try
Data32_Out <= unsigned(data_out_high) & unsigned(data_out_low);

regards,
laurent gauch
www.amontec.com
 
Hello,

Can you be more specific as to the exact message that Quartus gives? You
can cut ans paste the Quartus message in the reply. Also can you describe
what is meant by "implictly constrainedwhile instanciating" in the post?

Subroto Datta
Altera Corp.

"Mohammed A khader" <am.imak@gmail.com> wrote in message
news:1114002116.636763.217170@g14g2000cwa.googlegroups.com...
Hi all,

I am having a component Multiplier with unconstrained ports. But this
is not my top_level_entity and ports are implicity constrained while
instanciating this component.

It simulates well but while synthezing Quartus says that ports must be
constrained. I think that Quartus could infer it from instanciation
syntax. Is there any solution to get around it

Thanks.

-- Mohammed A Khader.
Click to expand...
 
Mohammed A Khader wrote:

Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(26):
ports must be constrained

-- My Multiplier component is .........
entity Multiplier_Synth is
port(
Op1 : in signed; -- Operator 1
Op2 : in signed; -- Operator 2
Mult_Out : out signed -- Multiplication Result
);
end entity Multiplier_Synth;
Click to expand...
Use generic parameters - e.g.:


entity Multiplier_Synth is
generic(
width : integer:=16 );
port(
Op1 : in signed(width-1 downto 0);
Op2 : in signed(width-1 downto 0);
Mult_Out : out signed(width*2-1 downto 0)
);
end entity Multiplier_Synth;


Generic parameters are overridden, if a generic mapping is used during
instantiation. (Otherwise the given default value is used.)
Because you have to define the bitwidth somewhere in your design, it
does not matter where and how. Therefore Generic paramters are suitable.
You can feed them from the very bottom to the top entity.

Ralf
 
On 20 Apr 2005 03:48:55 -0700, Mohammed A khader wrote:

-- Concatenation of Low and High to form 32 Control Word
Data32_Out <= unsigned(data_out_high & data_out_low); -- ERROR IS IN
THIS LINE...

Whats wrong with the last statment. I expect '&' operator to
concatenate the two signals. What could be the other meaning of '&'
operator. I think I am doing a silly mistake some where . Please help
me in resolving this..
Click to expand...
With '&' you can (1) concatenate two arrays. For example, when using two
arrays of std_login (aka std_logic_vector):
"000" & "111"
This will create a 6 element long array.
With '&' you can (2) append or (3) prepend a single element to an array:
"000" & '1'
'0' & "111"
This will create a 4 element long array. Note that it is syntactically
different from "0" & "111", which I described in (1).
With '&' you can (4) create a new array by concatenating two elements:
'0' & '1'
This will create a 2 element array.


Now, this works not only with std_logic_vector, but with any array. For
example, with this one:

type Regfile is array (natural range<>) of WORD;
Click to expand...
Now we have two different interpretations of
data_out_high & data_out_low
It can either produce a signed(0 to 31) (VHDL-93) according to (1), or a
Regfile(0 to 1) according to (4).


Laurent showed one way to avoid this problem. My first guess would have
been something like
Data32_Out <= unsigned(signed(data_out_high) & signed(data_out_low));
which is closer to your original code. Maybe the following would work:
Data32_Out <= unsigned(signed'(data_out_high & data_out_low));
But I'm not sure. (Please note the tick.)


[xp and f'up2 comp.lang.vhdl]

Sebastian
 
Mohammed A khader wrote:
But both are logically equal.
What was my mistake ?
Click to expand...
Using & on your own array types
without writing an overload for "&".
Probably easier to use the predefined &
for unsigned as Laurent suggests.

If these are process statements, you could also say:

Data32_Out(31 downto 16) <= unsigned(data_out_high);
Data32_Out(15 downto 0) <= unsigned(data_out_low);

-- Mike Treseler
 
During the development of the new version anyone can contribute.
Have a look at: http://www.eda.org/vhdl-200x/

But you are right that after the ballot you have to buy the standard.

Egbert Molenkamp

"Peter Ballard" <pballard@ozemail.com.au> wrote in message
news:9d5509fa.0504201750.43c41cf8@posting.google.com...
"Egbert Molenkamp" <remove_funny_molenkam@cs.utwente.nl> wrote in message
news:<d44vu4$ffh$1@ares.cs.utwente.nl>...
Its already part of the standard. If your tool is up-to-date is supports
the
example given in your link.
(http://www.eda.org/isac/IRs-VHDL-93/IR1077.txt).
Make sure to enable VHDL 2002 mode, if required

Thank you, you are correct.

I guess the answer to my wider question (where can I find information
on language updates?) is that the spec is not free (in either sense of
the word), so I can't expect to find update information on the web.
Correct?

--
Peter
Click to expand...
 
Hi, hier sind meine geilen Bilder!
My nude Pics!!!
http://www.geile-tipps.info/go/

--
Posted by News Bulk Poster
Unregistered version
 
"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0504202323.342f42e4@posting.google.com...

<snip>

I am NOT talking of DQ with regard to DQS.

I am talking about the bits of the bus DQ and the bits of the bus
DQS ! They have different tCO.
I already know DDR basics ;o)
Click to expand...
I'm still not answering your question but posing you another question:

Are the clock-to-out times different by about 1/4 of your DDR clock period?

I know that timing analysis from other vendors tend to illustrate timing
from the positive edge of the appropriate clock. If the Lattice
implementation uses a 2x clock for the data signals, the DQ "bus" and the
DQS "bus" (neither of which are a bus, really - they're coupled into byte
lanes) would be clocked on opposite edges of that clock. If the
clock-to-out timing is referenced to the rising edge only, the difference
would be half the 2x clock period. Is that what you're seeing?

Either a Lattice FAE or timing report numbers published here might give
others a better idea of what's happening.
 
Mohammed A khader wrote:

Hi all,

I am having a component Multiplier with unconstrained ports. But this
is not my top_level_entity and ports are implicity constrained while
instanciating this component.

It simulates well but while synthezing Quartus says that ports must be
constrained. I think that Quartus could infer it from instanciation
syntax. Is there any solution to get around it

Thanks.

-- Mohammed A Khader.



I do not believe the Quartus compiler supports unconstrained ports.
Click to expand...
Either use generics to size the port, or use a synthesizer such as
synplify that does support unconstrained ports.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
Divyang M wrote:


I have created three buffers components (bufferA, bufferB, bufferC)of
varying lengths and instantiate bufferA inside MyEntity. Now, I want
to create another instance of MyEntity but use bufferB instead of
bufferA.

Is there a way that I can use some configuration script in the VHDL
file to let it know which buffer to instantiate?
Click to expand...
What about a generic parameter and using the if-generate statement?

If bufferA and bufferB have the same entity, you may also use one entity
and two architectures, while a VHDL configuration specifies which one
has to be chosen.

Ralf
 
Mohammed A khader wrote:

my signals 'data_out_high' and 'data_out_low' are subtype of signed.
Hence I expect that sysnthesis tool does'nt consider it as a new type.
Click to expand...
When you declare an array type like Regfile,
you automatically get new "&" functions
to combine arrays and to add
an element to the array.
In this case, an element of Regfile
is indistinguishable from a WORD.

Data32_Out <= unsigned(data_out_high) & unsigned(data_out_low);

Works in all cases
because & for unsigned
is the only possibility

Data32_Out <= unsigned'(data_out_high & data_out_low);

Works only if you change the
WORD declaration to
unsigned(31 downto 0)
otherwise:
Ambiguous type: 'regfile' or 'signed'.


Data32_Out <= unsigned(data_out_high & data_out_low);

Ambiguous type: 'regfile' or 'signed'.
No easy way to make this do what
you expect without removing the
Regfile type declaration.

-- Mike Treseler
 
"Praveen" <sams235@gmail.com> wrote in message
news:1114229027.522626.39810@g14g2000cwa.googlegroups.com...
Hi all,

I have been looking at some code that raised a basic question. If we
have process like

process
begin
wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;

when trigger is true are the 4 signal assignment statements executed
sequentially or concurrently ?
Click to expand...
Concurrently.

What happens when they are variable assignments like below

process
begin
wait on TRIGGER;
variable1 := Variable2;
Variable2 := Variable1 + Variable3;
Variable3 := signal2;
RESULT <= Variable1 + Variable2 + Variable3; -- RESULT is of
type signal
end process;


I tried simulating both of them and the results are different (because
of the variable/signal differnce on assignment).

The website where this example is cited
http://www.seas.upenn.edu/~ee201/vhdl/vhdl_primer.html#_Toc526061350
says ..when they are declared as variables they are executed
sequentially and when declared as signals are executed concurrently.
The book that I usually follow says (and I agree) that the signal
assignments are sequentially executed. Is'nt that the reason why
processes were created in the first place?
Click to expand...
Inside a process, the later assignments take precedence. E.g.,

process
begin
wait on clk='1';
dummy0 <= '1';
dummy0 <= not dummy0;
end process;

This toggles dummy0 (which yes, should be initialized somewhere.) Even
though the first dummy0 assignment is scheduled, it get's overwritten. The
last assignment takes precedence. For example, the following process
synchronously resets dummy0 when reset is '1', and synchronously sets dummy0
when reset is '0';

process
begin
wait on clk='1';
dummy0 <= '1';
if reset = '1' then
dummy0 <= '0';
end if;
end process;

If they are executed sequentially, why do we get the different values
when they are declared as variables/signals.

Could someone help me out?

Thanks.
Click to expand...
 
"Praveen" <sams235@gmail.com> schreef in bericht
news:1114229027.522626.39810@g14g2000cwa.googlegroups.com...
Hi all,

I have been looking at some code that raised a basic question. If we
have process like

process
begin
wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;

when trigger is true are the 4 signal assignment statements executed
sequentially or concurrently ?

What happens when they are variable assignments like below

process
begin
wait on TRIGGER;
variable1 := Variable2;
Variable2 := Variable1 + Variable3;
Variable3 := signal2;
RESULT <= Variable1 + Variable2 + Variable3; -- RESULT is of
type signal
end process;


I tried simulating both of them and the results are different (because
of the variable/signal differnce on assignment).

The website where this example is cited
http://www.seas.upenn.edu/~ee201/vhdl/vhdl_primer.html#_Toc526061350
says ..when they are declared as variables they are executed
sequentially and when declared as signals are executed concurrently.
The book that I usually follow says (and I agree) that the signal
assignments are sequentially executed. Is'nt that the reason why
processes were created in the first place?
Click to expand...
I copied a part of the document you refere to:
*************
It is important to understand the difference between variables and signals,
particularly how it relates to when their value changes. A variable changes
instantaneously when the variable assignment is executed. On the other hand,
a signal changes a delay after the assignment expression is evaluated. If no
delay is specified, the signal will change after a delta delay. This has
important consequences for the updated values of variables and signals. Lets
compare the two files in which a process is used to calculate the signal
RESULT [7].
*************

Notice that also the last line "has important consequences..".

The statement in both processes you give are exectured sequentially. However
in the first proces signal signal1 is not updated immediatly (it takes one
delta). Therefore the second sequential statement in that process "signal2
<= signal1 + signal3" uses the not updated value of signal1.
When is signal1 updated? When all concurrent statements have finished there
execution. Due to this mechanism concurrency is possible.

Egbert Molenkamp
 
Rainer wrote:
Hi,
i am searching for software (freeware maybe) which is able to manage a
huge number of hdl modules for reuse. the software shoult archive a
reuseable hdl module and support an easy find of archived modules.
Click to expand...
I use emacs vhdl-mode port and compose functions
for that sort of thing.

-- Mike Treseler
 
xiibweb@hotmail.com wrote:


I am interested to write a code where one input is user defined and the
other input is fixed to some value....

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Click to expand...
Hint: These libraries are not recommended, because their implementation
depends on the tool. Use IEEE.Numeric_Std.ALL instead.


entity multo is
Port ( p1 : in std_logic_vector(1 downto 0);
w1 : in std_logic_vector(1 downto 0);
ou : out std_logic_vector(3 downto 0));
end multo;

architecture Behavioral of multo is

begin

ou <= w1 * p1;

end Behavioral;
Click to expand...
If you synthesitze this, you will get a standard multiplier. Only if you
include this in a higher level component and make it clear for the
synthesis tool, that one input is fixed, you will get an efficient
implementation.
Try to use this (Numeric_Std.ALL included):

entity multo is
generic(
p1 : integer:=2 );
port (
w1 : in std_logic_vector(1 downto 0);
ou : out std_logic_vector(3 downto 0) );
end multo;

architecture Behavioral of multo is
begin

ou <= (unsigned)w1 * p1; -- signed or unsigned?

end Behavioral;

Hint: Multiplication by two is nothing more than a shift. With the
suggested approach using the generic parameter the synthesis tool is
able to see this and will infer a simple shifter.

Ralf
 
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