Clock Edge notation

[Sebastian Weiser]

On Wed, 20 Apr 2005 11:14:59 -0700, Mike Treseler wrote:

Using & on your own array types
without writing an overload for "&".

Hmm, that differs from my explanation.

I've never seen an explicit overloading of the "&" operator, since it is
AFAIK implicitly given for any array type.


Sebastian

 

[info_]

Jim Huang wrote:

Can I write the if condition like this? Assume

signal A std_logic_vector(29 downto 0);

if A = (others => '0´) then
.................
end if;

if this syntax is invalid, how should I write it?

One clean solution is to use subtypes and qualified expression :

subtype SLV30 is std_logic_vector(29 downto 0);

signal A : SLV30;

if A = SLV30'(others=>'0') then -- will work

As you noticed , hexadecimal notation isn't for fun except
on exact multiple of four bits...

Other solution :

if (unsigned(A)=0 then

etc...

Bert Cuzeau

 

[info_]

Mohammed A khader wrote:

Hi John,

To have a fixed input it must be a constant (not a input port). So you
have to change your code to
================================================================

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity multo is
Port ( w1 : in std_logic_vector(1 downto 0);


ou : out std_logic_vector(3 downto 0));
end multo;

architecture Behavioral of multo is

constant p1 : std_logic_vector(1 downto 0):= "10";

begin

ou <= w1 * p1;

end Behavioral;

================================================================



There are other things to correct in code. You have included the
package for unsigned and arithmetic but have not used it.

Yes he did !
that's what std_logic_unsigned is about :
it treats std_logic_vectors as unsigned.

Hence your declarations must be

w1 : in unsigned(1 downto 0); .....

-- Mohammed A Khader.

Not necessary. see above.

But I think everyone should give up synopsys arith packages and
switch to numeric_std instead.

Bert Cuzeau

 

[Mike Treseler]

Sebastian Weiser wrote:

I've never seen an explicit overloading of the "&" operator, since it is
AFAIK implicitly given for any array type.

I agree.
The OP's problem was
too many overloads,
not too few.

-- Mike Treseler

 

[info_]

Marco wrote:

My name is Marco and I'm working on my final year project, one subblock of
my project is a fft.
I would like to develope it myself (the fft) , but their is no time for that
because i have only 12 weeks for the hole project.
I got the cf_fft 512(vhdl version) on opencores.org but i have problems with
it,
the only thing that i get on the output_0_o is zero!
Is their a special pattern that i have to plug in at the three control
inputs
(enable_i,reset_i,sync_i<= i tested all 8 pattern) or do i need a special
clock ???

It would be very nice of you to give me a short introduction what i have
to do to bring the fft to run.

Greetings Marco

You have the source code (and probably some documentation), then you should
probably read it and try to understand how it works (big lines at least).
And simulation will let you actually "see" it work, though automatically
generated code isn't great for this...
Don't forget that FFTs are deep memories. In other words, they have a large
latency, by construct.
You may try to inject some noise (random values are good for that), run for
sufficient length, and check that you have "something" coming out after a while.
Then, you may inject a sinewave + noise, and see that you see the proper bin
standing out. etc...
Be ready to handle complex numbers (I/Q pairs).
Hint : you can use math_real in your test bench to generate the stimuli.
Hardware DSP is fun.

If you don't like the confluence version, you may go for a more traditional
radix-4 and radix-2 based approach. (I think it's what cf does generate anyway)
I don't like this code very much, especially the unsigned(0 downto 0) for the
control signals which is just an unnecessary pain. But it's free.

You need a pulse on sync_i to start the FFT calculation, some random data on the
inputs, and some (well many) clock cycles to see data coming out.

----
Just tried it : it works. You have a latency of ~2610 clock cycle.
(512 points FFT from the archive name)
The stimulus for the pins you ask for is trivial :


signal done : boolean;
constant Period : time := 10 ns;

begin

Reset <= '1', '0' after Period;
Clock <= '0' when done else not Clock after Period / 2;
Enable <= '1';

Sync_in <= '0', '1' after 4 * period, '0' after 5 * Period;
Done <= true after 4096 * Period;

For the data, as i said, you can use the UNIFORM function as a random nbr generator.
The output is "UUUU.....UUU" until sync_out goes up, followed by the data.

My complete test bench is just about 60 lines.

It's an 1/2 hour effort to get the source and make it produce some data...
but I think you should invest a little time in understanding how hardware
FFTs are implemented, the various ways to do it with respective advantages, etc...
In a final year project, I guess the idea is to learn as much as possible,
and using the confluence FFT (really a black box) probably won't teach you a lot.
But that's my view of it.
FFTs are probably becoming like multipliers : nobody cares anymore how they are
built internally, provided that they work as expected...

On FPGA targets, I would rather use the vendor's macros, which are now
nearly unbeatable in most cases.

Bert Cuzeau

 

[Mike Treseler]

Rainer wrote:

thanks, but it should be for more than 100 engineers , like a know how data base

Consider setting up a CVS server.

-- Mike Treseler

 

[tpi]

true
Uzytkownik "tom" <tom1@launchbird.com> napisal w wiadomosci
news:1113942836.716708.188290@f14g2000cwb.googlegroups.com...

VhdlArch-0.1.1 is now available. Still only handles syntax checking,
but includes several bug fixes (thanks for the feedback!).

http://www.confluent.org/wiki/doku.php?id=vhdlarch

-Tom

 

[m]

On 25 Apr 2005 12:17:27 -0700, jakob_chr@yahoo.com (Christian) wrote:

Hi,
i am trying to implement a fixpoint square root in vhdl.
The radicant consists of integer as well as fractional bits like 4.23 - dec.
Does anyone know a synthesiable algorithm ?
Thanks in advance
Christian

The first link here seems nice:
http://www.google.com/search?hl=en&q=fixed+point+square+root

 

[Duane Clark]

ALuPin wrote:

Hi,

what does have more advantages when trying to synchronize an incoming external
datastream:

1. Synchronize the data bus with some (two or three) register stages
and feed the sychronized data into a FIFO which is an additional
synchronization stage (write clock of FIFO has a different frequency
than the read clock)

It makes no sense to say that you are going to "synchronize the data bus
with some register stages". What will invariably happen when you try to
do that is that some of the portions of the data bus will occasionally
exit the last stage on different clocks. Each individual bit of the bus
may be synchronized correctly, but the bus as a whole will not, without
taking additional measures.

2. Feed the data bus directly into the FIFO and synchronize the data coming
out of the FIFO into some (two or three) register stages ?

Why do you need to synchronize the data coming out of the fifo? As you
pointed out, the read clock is different from the write clock. So the
work of synchronizing is already done for you. This is in fact a very
good way of synchronizing a bus.

 

[Mike Treseler]

Dan Nilsen wrote:

12 bits. I have a component to strip away the redundant bits from the
divider, if the result of the division is, say an int value of 6, I
don't want to use all 12 bits.

If you don't use all 12 bits,
how can you tell where one result
ends and the next begins?

-- Mike Treseler

 

[KCL]

just another guy that come from software...


"Dan Nilsen" <dan.nilsen@gmail.com> a écrit dans le message de news:
50a67599.0504260257.6c83de8e@posting.google.com...

Hi all!

I have a problem that someone here might have the answer to. I have a
divider that takes inputs of 13 and 12 bits, and produces an output of
12 bits. I have a component to strip away the redundant bits from the
divider, if the result of the division is, say an int value of 6, I
don't want to use all 12 bits. This circuit is a part of an MPEG-4
device, a quantizer, so I want to compress as much as possible. My
question is then, how do I declare the ports on the component that
strips away the bits to output an std_logic_vector that is not fixed
in size, but dynamic? This must be synthesizable. Guess there are many
ways of doing this, and I hope someone has got an answer to me.

Thanks,

Dan Nilsen

 

[Mike Treseler]

Neo wrote:

I am not able to install the linux x86 version on cygwin. its giving
the error "./vhdlarch: 1: Syntax error: "(" unexpected" when I run
vhdlarch -help after gunzip.

I have found cygwin to be more trouble
than adding a linux partiton to a windows machine.

But for just a syntax check, vcom.exe will do
the job from a dos or modelsim prompt.
Unlike vsim, vcom runs without a license.

-- Mike Treseler

 

[Ben Twijnstra]

Hi Peter,

It is much safer to use a proven circuit designed by experts. It may
sometimes be overkill, but it works, and lets you spend your energy on the
really important and unique parts of your design.

As commercially biased as I am, I have to agree with you.

Designing a good dual-clock FIFOs can take many weeks of devising
algorithms, testing them, throwing them out of the (for stress relief,
preferrably closed) window etc. When I designed my first cross-clock bus it
was on OTP parts, so I truly learned to simulate before burning, and even
then it took me six or seven failing designs (equalling 3 fully equipped
worth about $800 each) before getting it Right.

If you have three or four weeks of spare time and a powerful computer to
research the subject, then by all means, please do find an efficient way to
build a dual-clock FIFO construct we haven't thought of. Otherwise, please
use $VENDOR's implementation. Project pressure usually is way too high to
waste on a FIFO.

Best regards,


Ben

 

[info_]

Peter Alfke wrote:

Berty, I disagree.
While it is good for every young engineer to learn the basic skills,
designing an asynchronous FIFO is far from "basic".
Using a dual-ported RAM makes most of the design trivial, but the EMPTY
and FULL detection and arbitration at high asynchronous clock rates is
far from simple. I have a few patents and several magazine articles,
and Clifford Cummings has published extensively. It is still considered
wizardry, and grown men can get into deep arguments, since this
involves Gray counter decoding and metastability. It is much safer to
use a proven circuit designed by experts. It may sometimes be overkill,
but it works, and lets you spend your energy on the really important
and unique parts of your design.
Peter Alfke, Xilinx Applications

Excellent post IMO.
We (who spend weeks coding complex designs) are _so_ happy that gifted
engineers took the pain to build asynchronous stuffs that _work_,
guaranteed
Clock domain crossing isn't usually a problem thanks to these
little "cores" that we use everyday without thinking.

Interestingly, it seems that, today, fewer and fewer engineers are
even curious to know how modern FFT cores are implemented internally !

Well, I believe there is still room for creativity and clever engineering,
but the level of abstraction is just moving up one other notch.
The challenge also moved towards verification, but I think there is no
verification methodology which will ever fix a poor design.

But thanks again anyway to the creators of the async Fifos !!!

Bert Cuzeau

 

[Kolja Sulimma]

Your port is a bunch of wires that represent your results. If you want
to transmit the result in one clock cycle and you have 4096 different
results from your 12-bit divider there is no way you can get along with
less than 12 bits, you need them to distinguish the different results.
In that case a 0 bit is not unused: It is used to tell the receiver that
it is not 1.

If you know in advance that ALL your results are allways less than 2**N
you can get along with less bits.
To be exact: If you know that you will have less than 2**N different
results you can get along with N bits, no matter how large the results are.

Kolja Sulimma

Dan Nilsen wrote:

Hello,

Thanks for the responses.

The reason I need to do it is because I get a (signed) quotient from a
divider in a range I already know. I divide a 8x8 DCT by 1 out of 2
preset Quantization matrices, which in turn are scaled by an integer
ranging from 1-32. Sometimes I will get a 0 from the divider, during
this case I don't want to transmit "too many" bits. I do however
realise that this might be impossible, but I appreciate answers given
me here.

Thanks,

Dan

 

[Bert Cuzeau]

Mohammed A Khader wrote:

Hello,

When synthezing the design with Synplify Pro 8.0 it gave the
follwoing Warning.

CL209 Input port bit <4> of spi_addrs(4 downto 0) is unsed.
CL209 Input port bit <3> of spi_addrs(4 downto 0) is unsed.
CL209 Input port bit <2> of spi_addrs(4 downto 0) is unsed.
CL209 Input port bit <1> of spi_addrs(4 downto 0) is unsed.


I am sure that I am using the slice (4 downto 1) as an input to the
mux.

I tried by assigning this slice to an intermediate wire (signal) and
then to the mux input . But again it is giving the same error.

Following is the relevant piece of code....
ntity Ctrl_Ram is
port(
Ctrl_Data_In : in WORD;
Ctrl_Addrs : in unsigned(3 downto 0);
Spi_Addrs : in unsigned(4 downto 0);
Ctrl_Wr : in std_logic;

Intl_Rst : in std_logic;
Clk : in std_logic;

Reset : in std_logic;

Data32_Out : out DWORD;
Data16_Out : out WORD
);
end entity Ctrl_Ram;

Architecture arch of Ctrl_Ram is
begin
spi_addrs_intl <= Spi_Addrs(4 downto 1);
Addrs_Muxrocess(Ctrl_Addrs,spi_addrs_intl,Intl_Rst)
begin
case Intl_Rst is
when '0' => Addrs_In <= spi_addrs_intl;
when '1' => Addrs_In <= Ctrl_Addrs;

when others => Addrs_In <= (others =>'X');
end case;
end process Addrs_Mux;


Thank you.

-- Mohammed A Khader.

1. Why this complex code and not simply :

Addrs_In <= Spi_Addrs(4 downto 1) when Intl_Rst='0' else Ctrl_Addrs;

2. I don't think we see enough of the code to tell you where
exactly you got it wrong.
Maybe Addrs_In is not used when Intl_Rst='0' ?

Have you checked with simulation that somehow Spi_Addrs is
effectively used ?


Bert Cuzeau

 

[Duane Clark]

ALuPin wrote:

Duane Clark wrote:

It makes no sense to say that you are going to "synchronize the data bus
with some register stages". What will invariably happen when you try to
do that is that some of the portions of the data bus will occasionally
exit the last stage on different clocks. Each individual bit of the bus
may be synchronized correctly, but the bus as a whole will not, without
taking additional measures.


Thank you for your answers.
The external data stream I am talking about comes form an USB transceiver
which sends the data synchronous to 60MHz clk which I can use in my FPGA
as FIFO write clock. Under this assumption of synchronous data stream
the portions of the data bus will NOT occasionally exit the last stage
on different clocks, will they ?

That should work fine (assuming of course the FIFOs are designed right).
In this case, the FIFOs are doing the synchronizing, not the registers.

 

[Mike Treseler]

ALuPin wrote:

The external data stream I am talking about comes form an USB transceiver
which sends the data synchronous to 60MHz clk which I can use in my FPGA
as FIFO write clock.

Consider running your FPGA on the same clock.
Maybe you could collect the serial data
and handshake the bus synchronously.

-- Mike

 

[info_]

Berty wrote:

Peter,
While I understand your point I'm afraid this is why you see so many
Eng that know just about nothing except copy paste of IP module.
Of course Async FIFO is not as simple as shift register. And of course
it involve some thinking and I would strongly recommend anyone who want
to design such thing or for that matter any new design to have DR of
more experience Eng to see how he did what he did and see how to
improve or fix the wrong.
I'm fully aware of the Empty Full having designed several FIFO of all
type and flavor.
Except for the obvious of the advantage of knowing what you do and
example as for why you should know to design by yourself can be that
Some FIFO depend on the implementation when they have one last entry
will toggle the empty while other will not.
Sometime this toggle can be more useful however if you know Zilch about
how the FIFO was design you can do nothing and have to adapt yourself
to what ever the core give even if this is not the best for the design
you do.
And talking about synconizers and Gray counter etc while to use them
correctly is important this is not rocket science, Sure to give
complete and full explanation of what Metastable is and the effect of
it in clear way and not just using "wave hand" explanation can be
challenging but the actual implementation once you understand the
meaning of it is not so difficult that one have to pass it aside and
use other proven code.
I guess it all boil down to are you an Eng who want to be a copy/paste
one or are you an Eng who want to know how to do thing and yes ONCE you
know use other if they make sense, but even for this to tell if it make
sense you need to understand and not just be another copy/paste-Eng as
more and more I for one encounter.

And all those who might give example on how they saved money, time etc
by using other FIFO and not learning how to do it the right way are
just an example as why you SHOULD learn and not just be copy paste one
and use this as example to why to use other code.

Back to Math using your own logic is equivalent to say to Eng you
should learn how to do 1+1 however to do integral of X^2 from 0 to 2 is
to complex so use calculator, I do hope university will not go with
this logic and those that do well maybe from there we get all the
copy-paste Eng's.

Remember that any minute you "Waste" today for learn how to do it
will pay thousands time in your future, when you have design which are
not simple and there is no IP and you need to draw from your own
experience, which if it involve only/mainly copy-paste without the
knowledge mean you will never become ASIC leader or Architect of new
complex designs and you will stay basic simple Designer, as no
knowledge mean poor capability.

Interesting post too... however...
I sure am always extremely frustrated when I see people coding in HDL and
not knowing the basics, calling their VHDL code a "program", not knowing
what crossing clock domains is about, etc !

But on the other hand, we are in a competing world, and as a Project Manager
I would be VERY unhappy to see one engineer spend a week trying to write
his own dual clock Fifo and SOMEWHAT scared about the result (through
a synthesis tool in particular). As of what he would learn in the process
(no pun intended) I'm not very sure (verification of such a beast is not
obvious either). And the customer wouldn't see any advantage vs a
design using ready-made Fifo, but he WILL see a tangible advantage if we
spent an extra week implementing new innovative features (for the same budget).

But I sure taught my team all the many tricks I use when designing with FSMs.
We designed our own FFTs, they used to be superior to the vendors' in many
situations, but that's less and less the case, so we drop this know-how
(for FPGA) and we more and more use the standard megafunction.

I would say that there is room in-between these extremes (knowing nothing
and knowing everything)

In our courses, we do our best to teach really solid foundations and
stay focused on the issues that will make a difference between good
and poor design.
To me it's safe enough if the engineer clearly understands the issues,
& knows the principles of what the cores are made of and why, and
knows which to use in each situation.
I'm not sure it's so important anymore to fully understand the RISC
instruction set in the context of SOPC. It's a long time I didn't
code in assembly language.

My opinion indeed...
Thanks anyway for this exchange of views.


Bert Cuzeau

 

[David R Brooks]

If you need the component label to (for example) apply an attribute,
you put the attribute inside the lpp. Thus:

for n in RANGE generate
-- attributes here
begin -- Note we now need a "begin"
-- as before

"avishay" <avishorp@yahoo.com> wrote:

:Hi
:This is the code you need:
:
:for n in SWMMBSIZE_IN_ROW-1 downto 0 generate
: swmsram: mbbankinswm
: port map(
: address => std_logic_vector(addr),
: datain => din,
: write => write,
: dataout => dout, -- <== Note this!
: clk => clk
: );
:end loop;
:
:Notes:
:1. You should use the GENERATE statement. This is a concurrent
:statement (not within a process).
:2. At elaboration time, a numbered sufix is appended to each component
:label. I
:don't know if this suffix is standart among all
:simulators/synthesizers, but this is not a problem unless you need to
:refer a component's label.
:3. Some port mappings (at least outputs, usually) must be dependent on
:the loop variable, or else all your generated components will be
:connected in parallel.
:
:Hope it helps,
:Avishay
:
:boku wrote:
:> Dear all,
:> I'm trying to use For-loop or generate to instantiate RAM
:> components but am stuck. I don't know how to assign each instance
:name
:> so I can reference each individual component. Or generate statement
:> can achieve this? Looking forward to ur answer. Thanks a lot!~
:>
:> --------------------------------------------
:> for n in SWMMBSIZE_IN_ROW-1 downto 0 loop
:> swmsram: mbbankinswm
:> port map(
:> address => std_logic_vector(addr),
:> datain => din,
:> write => write,
:> dataout => dout,
:> clk => clk
:> );
:> end loop;