Clock Edge notation

[Brian Drummond]

On Tue, 02 Dec 2014 01:44:11 -0800, Muhammad wrote:

On Monday, January 7, 2002 11:08:40 PM UTC+1, pacific ocean wrote:
Looking for links to interleaver design for Turbo codes.

THX Fredj

hi,
i need the code for interleaver can u give me plz..

thanks

Well he's had 12 years to finish the assignment so maybe he'll give
you teh codez.

Good luck!

 

[AA]

On Sunday, December 7, 2014 4:29:20 AM UTC+3, KJ wrote:

On Saturday, December 6, 2014 12:26:26 PM UTC-5, AA wrote:
hi,
How to calculate the throughput in Mbps of the design under Quartus II ?

Thank you,

Quartus does not calculate Mbps. Use a spreadsheet.

KJ

What do you mean by spreadsheet?
May you please give me some details?

 

[Andy Bartlett]

"AA" <ahmedablak0@gmail.com> wrote in message
news:1ccdec9a-5f41-427e-928b-fd5297e11528@googlegroups.com...

hi,
How to calculate the throughput in Mbps of the design under Quartus II ?

Thank you,

Use the TimeQuest timing analyzer. This will give you the maximum internal
clock rate you can run your design at. It will calculate the longest
register-register prop. delay and include register setup and hold times. You
can also get it to list all the internal props. starting at the longest of
you want to sift through manually.

As usual, RTFM.

Andy

 

[KJ]

On Sunday, December 7, 2014 9:24:53 AM UTC-5, Andy Bartlett wrote:

"AA"
hi,
How to calculate the throughput in Mbps of the design under Quartus II ?

Thank you,

Use the TimeQuest timing analyzer. This will give you the maximum internal
clock rate you can run your design at.

That will not give you "throughput in Mbps", it will only give you clock rate in MHz. Not at all the same thing.

KJ

 

[Nikolaos Kavvadias]

Hi Rick and Jon,

Please educate me on what a BFM is? I know a BFS is a type of large
screwdriver.

@Rick: BFM stands for Bus Functional Model. It is an approach for modeling ..read() and .write() transactions from/to the system bus. SystemC/TLM is a popular approach for developing BFMs and probably the right thing to do is design a SystemC/TLM BFM and cosimulate with VHDL.

A BFM generation tool would be beneficial. On a second thought, ArchC (www.archc.org) fits the bill at least partially, is open/free and has a tractable learning curve. It is an architecture description language for generating SystemC simulators (functional and cycle-accurate) of processors, but also has been extended to generating models with TLM ports (e.g. for accessing a memory via the bus), a binary utilities port, and even an LLVM compiler backend [there is a prototype for that called accgen).

So in this sense, ArchC is the closest thing to automating BFM generation since you can include TLM ports in an ArchC model and generate a SystemC simulator from it (and then you can tweak it according to your aim).

@Jon: A VHDL package for easily designing BFM models would also be of interest. I don't think such thing exists, but again you can have a look at: http://opencores.org/project,axi4_tlm_bfm

This is an AXI (AMBA 4.0) transactor and BFM by Daniel Kho of Tauhop Solutions (www.tauhop.com). It is fairly well documented and maybe you could reuse some of the code for your purpose.


Best regards
Nikolaos Kavvadias
http://www.nkavvadias.com

 

[rickman]

On 12/10/2014 6:57 AM, Jon Skull wrote:

Hi VHDL fans,

I've been slowly taking up the various enhancements provided in VHDL2008, and I find some very useful for testbench construction, particularly generic packages.

However, am I missing something, or is there still no elegant way to create a pin-wiggling BFM driven by a transaction level (procedural) interface?

Verilog has always supported this because it is possible to call a procedure from outside the module in which it is declared.

For years I've approximated this in VHDL by using an inout "transaction" record port on the BFM, with some horrible bidirectional handshaking to transfer the transactions. I then define a package of procedures which take this transaction record as an inout argument. I think other people use this approach too, but it's far from ideal as you are forced to use resolved signal types for all of the record elements.

Has anyone found a better way using (supported!) VHDL2008 features?

Please educate me on what a BFM is? I know a BFS is a type of large
screwdriver.

I assume you mean some sort of an interface you wish to control via
commands. I'm not sure what the problem is. I've done this many times
in VHDL. I typically have a file with commands that define the action
to take and the time to perform those actions. For example, an MCU
interface has read and write transactions with address and data to be
written on writes or verified on reads. I read a line from the file,
parsed the information, waited for the time to match the simulation time
and then passed the command to the function that handled bus transactions.

Where is the problem? Oh, this was long before VHDL2008.

--

Rick

 

[rickman]

On 12/12/2014 2:15 AM, Nikolaos Kavvadias wrote:

Hi Rick and Jon,

Please educate me on what a BFM is? I know a BFS is a type of large
screwdriver.

@Rick: BFM stands for Bus Functional Model. It is an approach for modeling ..read() and .write() transactions from/to the system bus. SystemC/TLM is a popular approach for developing BFMs and probably the right thing to do is design a SystemC/TLM BFM and cosimulate with VHDL.

A BFM generation tool would be beneficial. On a second thought, ArchC (www.archc.org) fits the bill at least partially, is open/free and has a tractable learning curve. It is an architecture description language for generating SystemC simulators (functional and cycle-accurate) of processors, but also has been extended to generating models with TLM ports (e.g. for accessing a memory via the bus), a binary utilities port, and even an LLVM compiler backend [there is a prototype for that called accgen).

So in this sense, ArchC is the closest thing to automating BFM generation since you can include TLM ports in an ArchC model and generate a SystemC simulator from it (and then you can tweak it according to your aim).

@Jon: A VHDL package for easily designing BFM models would also be of interest. I don't think such thing exists, but again you can have a look at: http://opencores.org/project,axi4_tlm_bfm

This is an AXI (AMBA 4.0) transactor and BFM by Daniel Kho of Tauhop Solutions (www.tauhop.com). It is fairly well documented and maybe you could reuse some of the code for your purpose.

That is what I did some 15 years ago. I don't get why this is a big
deal. It seems like a pretty straight forward thing to me. The only
work involved was writing the code to parse the text file to drive the
bus. Am I missing something?

--

Rick

 

[Jim Lewis]

Hi Jon,
Still using records myself, however, ...

VHDL 2008 introduces generic packages. Allows generic packages to be passed on entity interfaces. Allows generic instances within an architecture. Has always allowed signals to be defined in packages. This would solve the BFM connection, however, when calling the transaction subprogram, the subprogram still needs to pass the signals it needs to drive - for the time being, I plan on using a record reference for that.

When vendors support these features, it will offer us a feature similar to SystemVerilog interfaces (without the concurrent region of the interface and modports (which allow constraint checking on who is allowed to drive which signals and who is allowed to call which subprograms)).

I have prototypes and such. I have submitted bug reports. I need others to indicate they would like such features supported.

Best Regards,
Jim

 

[Brian Drummond]

On Sat, 13 Dec 2014 08:11:08 -0800, Jim Lewis wrote:

Hi Jon,
Still using records myself, however, ...

VHDL 2008 introduces generic packages. Allows generic packages to be
passed on entity interfaces. Allows generic instances within an
architecture. Has always allowed signals to be defined in packages.
This would solve the BFM connection, however, when calling the
transaction subprogram, the subprogram still needs to pass the signals
it needs to drive - for the time being, I plan on using a record
reference for that.

When vendors support these features, it will offer us a feature similar
to SystemVerilog interfaces (without the concurrent region of the
interface and modports (which allow constraint checking on who is
allowed to drive which signals and who is allowed to call which
subprograms)).

I have prototypes and such. I have submitted bug reports. I need
others to indicate they would like such features supported.

Best Regards,
Jim

If you have simple testcases ... I'd be interested to see them - or talk
to Tristan. He seems to be on a roll these days.

ghdl (not 0.31 but 0.32 which is in the pre-release stage, anyone can
build it from source) supports enough VHDL-2008 to run OSVVM 2014.01 now.

If you have a prototype or testcase requiring additional VHDL-2008
support beyond that, it would be great to get that into the next release.

- Brian

 

[Andy]

Records work pretty well when you understand what the initializer does on a signal or port declaration. It can be used to keep the signal benign until/unless someone drives it.

Another approach I have used is to declare a package procedure(s) with separate in/out/inout signal ports, that provides your procedural interface(s) to the BFM.

Then in the process where you want to call the package procedure(s), you can overload the package procedure(s) so that only pertinent, per-call info is passed to the local procedure(s). A procedure declared in a process can access/drive signals visible to the process without them having to be explicitly passed to the local procedure. Just have the body of the local procedure call the package procedure with the full interface.

Andy

 

[Simon Thijs de Feber]

The following books I recommend :
1. The Designer's Guide to VHDL by Peter Ashenden
2. VHDL-2008, just the new stuff, by Peter Ashenden and Jim Lewis

and my personal favorite
3. Embedded DSP Processor Design by Dake Liu

and still very informative
4. The Design Warrior's Guide to FPGAs, by Clive Maxfield

grtz

ST

 

Thank you for this answer. It was helpful to me.

 

[Daniel Kho]

On Wednesday, 10 December 2014 19:57:11 UTC+8, Jon Skull wrote:

Hi VHDL fans,

I've been slowly taking up the various enhancements provided in VHDL2008, and I find some very useful for testbench construction, particularly generic packages.

However, am I missing something, or is there still no elegant way to create a pin-wiggling BFM driven by a transaction level (procedural) interface?

Verilog has always supported this because it is possible to call a procedure from outside the module in which it is declared.

For years I've approximated this in VHDL by using an inout "transaction" record port on the BFM, with some horrible bidirectional handshaking to transfer the transactions. I then define a package of procedures which take this transaction record as an inout argument. I think other people use this approach too, but it's far from ideal as you are forced to use resolved signal types for all of the record elements.

Has anyone found a better way using (supported!) VHDL2008 features?

Jon

As Nikolaos pointed out, do take a look at the AXI4 TLM/BFM project on OpenCores. If you're not into AXI, you still can reuse some of the packages from there. I've written it in a very reusable way - the pkg-tlm.vhdl generic package can even be reused without any changes (possibly minor changes, if you would) for any other protocol. The pkg-axi-tlm.vhdl is an instance of this generic package, so you can create other instances for other protocols.

The project even uses OS-VVM to do coverage-driven constrained randomisation of test vectors.

Cheers, dan

 

[Daniel Kho]

On Friday, 5 December 2014 22:24:15 UTC+8, HT-Lab wrote:

On 05/12/2014 12:48, Anssi Saari wrote:

Is Modelsim still not implementing VHDL 2008? I have some code with the
"new" if ... generate with else branch but Modelsim 10.1e doesn't seem
to support that. Or is it just that the Altera's Starter Edition doesn't
support that? I don't have a Modelsim PE or SE installed right now... I
tried case in generate as well but it didn't work any better.

Modelsim 10.1e was released in June of 2013. Your code compiled OK in
the latest 10.3d release.

Modelsim SE is an obsolete product and replaced by Questa core.

Regards,
Hans
www.ht-lab.com




Example code, vcom -2008 says
** Error: generate_prob.vhdl(20): near "else": syntax error
(line 20 is the else generate line.)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity dummy is
generic (
some_boolean_generic : boolean := false);
port(
clk : in std_logic;
reset_n : in std_logic;
dout : out std_logic
);
end dummy;

architecture dummy_arch of dummy is

begin

some_label: if some_boolean_generic = false generate
dout <= '0';
else generate
dout <= '1';
end generate some_label;

end dummy_arch;

The ModelSim-Altera version 10.1b (Apr 2012) supports VHDL-2008 pretty well. It's free (as in beer) - you can get it from Altera's website.

-dan

 

[KJ]

On Monday, February 2, 2015 at 2:00:45 PM UTC-5, ann.1...@gmail.com wrote:

hello,

how to write the vhdl coding for finding the image centroid using following eqaution

scalar (greyscale) image with pixel intensities I(x,y)
http://en.wikipedia.org/wiki/Image_moment#Raw_moments

M{ij} = sum_x sum_y x^i y^j I(x,y)
Centroid: { x, y } = {M10/M00, M01/M00 }

the pixel value have to be taken/read such that they are stored in the bram.my fpga have 8 bram of 18kb.kindly share the code

thank you.

Perhaps you can post the code that you've written over the past two weeks, that will give us a better idea of where you're having trouble http://www.edaboard.com/thread330375.html

Don't ask people to do your work unless you're paying them to do so.

KJ

 

On Thursday, July 10, 1997 at 10:00:00 AM UTC+3, Tim Holmes wrote:

Could anyone tell me how to create a "random" number generator in
VHDL. I imagine that the only method is to use a LFSR approach with
a seed.

If there are any other ideas, then please let me know.

Cheers.

Tim
Hewlett Packard

This page explains how I randomize the delay between packet injections to the DUT. To generate random numbers from within the VHDL test-bench, I used a random function in the following way.

....
library my_lib;
use my_lib.my_package.all;
....
signal rand_packet_delay : std_logic_vector(3 downto 0) := "1000";
signal rand_packet_delayi: integer;
....
rand_packet_delay <= f_my_rand f_my_rand (4, rand_packet_delay);
--write(my_line, rand_packet_delay'path_name);
--write(my_line, string'(" "));
--hwrite(my_line, rand_packet_delay);
--write(my_line, string'(" "));
--write(my_line, now);
--writeline(output, my_line);
--packet send ended
if(unsigned(rand_packet_delay) > 3) then
rand_packet_delayi <= conv_integer(rand_packet_delay);
else
rand_packet_delayi <= conv_integer(rand_packet_delay) + 3;
end if;
for j in 1 to rand_packet_delayi loop
wait until rx_clk'event and rx_clk = '1';
end loop;

Recently I have improved the random generation using c code and VHPI. First some links , which show simple examples of c code interface for GHDL.

Please visit me at
http://bknpk.ddns.net/my_web/SDIO/ip_ttl_filter_d_b_packets_rand.html

 

On Tuesday, August 4, 1998 at 10:00:00 AM UTC+3, Jon Eirik Sternang wrote:

Does anyone have a random generator that returns
integers between [a,b] (i.e. returns a integer
value between a and b)

thanks

Jon Eirik

This page explains how I randomize the delay between packet injections to the DUT. To generate random numbers from within the VHDL test-bench, I used a random function in the following way.

....
library my_lib;
use my_lib.my_package.all;
....
signal rand_packet_delay : std_logic_vector(3 downto 0) := "1000";
signal rand_packet_delayi: integer;
....
rand_packet_delay <= f_my_rand f_my_rand (4, rand_packet_delay);
--write(my_line, rand_packet_delay'path_name);
--write(my_line, string'(" "));
--hwrite(my_line, rand_packet_delay);
--write(my_line, string'(" "));
--write(my_line, now);
--writeline(output, my_line);
--packet send ended
if(unsigned(rand_packet_delay) > 3) then
rand_packet_delayi <= conv_integer(rand_packet_delay);
else
rand_packet_delayi <= conv_integer(rand_packet_delay) + 3;
end if;
for j in 1 to rand_packet_delayi loop
wait until rx_clk'event and rx_clk = '1';
end loop;

Recently I have improved the random generation using c code and VHPI. First some links , which show simple examples of c code interface for GHDL.

Please check
http://bknpk.ddns.net/my_web/SDIO/ip_ttl_filter_d_b_packets_rand.html

 

On Saturday, January 20, 1996 at 10:00:00 AM UTC+2, Lynn West wrote:

Is there a simple way to generate random numbers (preferably both
itegers and bit_vector or std_logic_vector type) in VHDL. I seem to
vaguely remember such but cannot find it in my books. (I have not yet
figured out how to master access to the FAQ for this newsgroup, so
cannot look there).

Obvously something could be conjured up with a set of differently-timed
clocks, but I am hoping for something simpler than that.

Thanks,

Lynn West
This page explains how I randomize the delay between packet injections to the DUT. To generate random numbers from within the VHDL test-bench, I used a random function in the following way.

....
library my_lib;
use my_lib.my_package.all;
....
signal rand_packet_delay : std_logic_vector(3 downto 0) := "1000";
signal rand_packet_delayi: integer;
....
rand_packet_delay <= f_my_rand f_my_rand (4, rand_packet_delay);
--write(my_line, rand_packet_delay'path_name);
--write(my_line, string'(" "));
--hwrite(my_line, rand_packet_delay);
--write(my_line, string'(" "));
--write(my_line, now);
--writeline(output, my_line);
--packet send ended
if(unsigned(rand_packet_delay) > 3) then
rand_packet_delayi <= conv_integer(rand_packet_delay);
else
rand_packet_delayi <= conv_integer(rand_packet_delay) + 3;
end if;
for j in 1 to rand_packet_delayi loop
wait until rx_clk'event and rx_clk = '1';
end loop;

Recently I have improved the random generation using c code and VHPI. First some links , which show simple examples of c code interface for GHDL.

Please read also
http://bknpk.ddns.net/my_web/SDIO/ip_ttl_filter_d_b_packets_rand.html

 

On Wednesday, November 22, 2000 at 10:00:00 AM UTC+2, Kai Troester wrote:

Hi

In a package I have a procedure which should print the time, the
instance and a message (I don't want to use the assert statements). My
problem is getting the name of the instance which is calling this
procedure without passing an additional parameter beside the message.
For time one can use 'now', but for the instance ? Does somebody have a
clue ?

Thanx, Kai
--
----- Dipl. Ing. Kai Troester -------------------------------------
Design Engineer -- System Design
IMMS - Institute of microelectronics and mechatronic systems
Langewiesener Strasse 22, 98693 Ilmenau, Germany
Tel: +49(3677)6783-52 | Fax: +49(3677)6783-38
mailto:kai.troester@imms.de | http://www.imms.de/~troester
-------------------------------------------------------------------

While it is simple in VERILOG (%m in the display system function), in VHDL a bit more code writing is required.
$display("dbg instance name %m at %d", $time);
An example how to print an instance name in systemc is also available on this site.


The importance of such debug information is when a design contains many instances of the very same component.

First text IO library has to be called and line variable should be declared. Please refer to print example to see details.

Next you have to select between two options: One is: instance name only in debug string and the other option gives more information such as entry and architecture names.

Syntax example is given below:

if(newByte = '1') then
write (my_line, string'("path "));
write (my_line, clk'path_name);--short
write (my_line, string'(" "));
writeline(output, my_line);
write (my_line, string'("inst "));
write (my_line, clk'instance_name);--long
write (my_line, string'(" "));
writeline(output, my_line);

Please see a detailed explication at
http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_path_name_print.html

 

On Wednesday, November 29, 2000 at 9:00:00 PM UTC+13, e...@riverside-machines.com.nospam wrote:

Srini wrote:

I am not sure if I understand the reasoning well here. I thought it
would be possible to "freeze" the "instance name" during Elaboration
(When the complete design hierearchy is known). So why should it be
known during Compilation itself (as an example Generics can be changed
during elaboration - isn't it?)

This was just my guess as to why it's implemented this way. In
general, you can't determine a complete hierarchical path to a named
item until runtime. Consider that subprograms are only elaborated at
runtime. It could be a real headache for a simulator to work out a
path to an item in a recursive procedure, for example, at runtime.

Evan

A procedure call is a statement. A function call is an expression. Subprogram calls collectively use dynamic elaboration (Today we push the parameters on a calling stack leaving space for a return value, and pop the whole mess when the call is complete and any return value has been evaluated).

The only way to get the calling location is through a passed parameter on the calling stack.

There is a proposal to pass the calling_path in a hidden fashion on the call stack (as an attribute which is a basic operation). That would require a significant amount of overhead putting some potentially long string on the calling stack impacting performance tremendously.

You could abstract that away to making a call a pseudo object, where you only pass an index that tells you were to find it. Not sure if a 32 bit value would be large enough. Somewhere there'd be a table of instance paths, path names, calling paths and the calling overhead for the index would still be enough to significantly impact performance when all operators are functions and all other operations of a type are basic operations. You could exempt predefined operators, but VHDL would still pay a heavy price because of it's strong typing.

The value proposition doesn't appear to be there leaving user space solutions.

The alternative would be either to bite the bullet and pass the path as a parameter or restructure to use the equivalent of a POSIX logging call allowing the calling location to report the path. For the former you could use default values allowing the parameters to only be passed for debugging. The default values would be a zero length string for the path and a possibly a boolean for determining whether or not report the path.

Detecting error conditions is tough for function calls, strong typing doesn't allow in band error reporting, requiring either a returned record or mirror functions returning an error condition separately. The idea here is to determine when the calling location reports it's instance path.

What this boils down to is that VHDL isn't like other languages. It serves for hardware descriptions that can be readily formally proven and that relies on strong typing. Despite rumors to the contrary it isn't a general purpose programming language, you can't bend it to other purposes readily. For instance you couldn't implement a VHDL simulator in VHDL without describing the simulation cycle in terms of hardware. The good news is you could put it in an FPGA.