Clock Edge notation

[MBodnar]

On Mar 30, 4:21 am, Tricky <Trickyh...@gmail.com> wrote:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_arith.ALL;

Std_logic_arith and numeric_std packages clash and will cause you problems if you try and use unsigned or signed types. std_logic_arith is non-standard VHDL and should not be used. Numeric_std is the real standard.

The story is origionally VHDL had no way to handle signed/unsigned arithmatic. Synpopsys wrote std_logic_unsigned/signed and std_logic_arith, which became a defacto standard across the industry. The VHDL working group then wrote numeric_std and released it as part of the IEEE VHDL standard in 1993.. Unfortunatly it took a while for vendors to latch on to the real standard, as well as many many engineers and text book writers.

My biggest advice is to the OP is to always remember to think in terms
of circuits and not in terms of programming language (with the obvious
and necessary exceptions: "events" and "sensitivity lists" and "when
you become experienced enough that there's no difference" etc.).
Circuit behavior is inherently parallel ... electrons just flow (or
don't flow), man.

I don't know what the target hardware is, so I won't make any
assumptions about your true intention for this code. Envision your
code as gates; while languages like VHDL are supposed to abstract this
somewhat, there's always reality, which is in our case is usually
something physical. (This is course in contrast to an arbitrary
sequence of finite/fixed operations.)

 

[Andy]

On Mar 29, 8:39 pm, KJ <kkjenni...@sbcglobal.net> wrote:

- The "if rising_edge(clock)" must be the outermost statement
- Don't use rising and falling edges (this is a digital design rule, not VHDL)

Other than that, you never stated exactly what problem you're having so I'm not going to try to figure it out for you.

Kevin Jennings

As long as the same variable/signal is not updated on two different
clocks/edges, most synthesis tools worth using will accept a single
process with both, as is the case here. Simulation does not care.

Assuming this is a simulation model (inout data port), you need to
define the output as (others => 'Z') when not performing a read. That
will allow someone externally driving the data to control the value.
Likewise, when they are not writing, they need to assign the signal
with (others => 'Z').

If this is intended to be a synthesizable component (e.g. in an FPGA
or ASIC), then I strongly urge you not to use bidirectional inout mode
ports unless this port is bound to a primary device level port, where
tri-state logic is an option. Some synthesis tools will automatically
transform internal tri-state drivers into multiplexers and decoders as
required to implement the logical behavior of the bus.

Also, if this is a synthesizable module, most FPGA BRAMs can have
independent clocks, so I don't think that is an issue for this
example, assuming your target is a BRAM. However, the output register
on some FPGA BRAMs does not have a clock enable, so that could be an
issue if you are not getting BRAMs inferred by the synthesis tool. In
most cases, simply reading a BRAM has no side effect, so it should be
no problem to remove the condition from the read, and simply always
read it (not withstanding the inout port mode issues mentioned above).

However, as KJ mentioned, the evaluation of the instr should be moved
inside the rising/falling_edge sections. Since these are effectively
clock enables, than can also be combined with their respective rising/
falling_edge() statement (e.g. if rising_edge(clk) and instr = write
then...)

You do not need the other "elsif instr = ... then null; end if;
statements in a clocked process.

Ditto on not using std_logic_arith package(s). I would go one step
further, and if this is not the device level interface, I would
declare the addr port as unsigned(6 downto 0), since it will always
have an unsigned numeric interpretation.

As a side note, define the range of the page array index based on the
range of the addr port (e.g. 2**addr'length - 1 downto 0) so the array
and port sizes are forever linked together.

Define the subtype for wordsize as positive so that errant values for
the generic are caught as early and directly as possible.

I strongly urge you to define constants for the different instr
values, rather than relying upon comments and bit string literals.
Meaningfully named constant definitions can be their own comments for
the reader, with the added benefit that they are checked/enforced by
the compiler. Assuming these values are used in different modules,
define the constants in a package accessible to each module that reads
or writes instr so that all are "singing the same hymn".

Andy

 

[Nicholas Paul Collin Glou]

On March 28th, 2012, Doubler <raul90ro@Yahoo.com> sent:

|--------------------------------------------------------------------------------------------------------------------|
|"hello all. |
|I have to make a VHDL sound generator using SPKR1 module. Can you give me some ideas how should I do this? Thnk you"|
|--------------------------------------------------------------------------------------------------------------------|

VHDL has no notion of "SPKR1 module". Perhaps this university problem
is for a particular evaluation board or other kit in a laboratory in
the university, and perhaps something called SPKR1 has been declared
for you, which controls a speaker.

We do not have the documentation for this. You do.

Perhaps changing the value assigned to SPKR1 from '0' to '1' or vice
versa would create a noise. Is any sound acceptable? Then maybe play
with it, deciding how often you will toggle the speaker by trying it.

 

[Nicholas Paul Collin Glou]

On March 29th, 2012, Matthew Jeschke <weinerschizel@GMail.com> sent:
|---------------------------------------------------------------------|
|"8 years ago I studied VHDL quite extensively in college. |
| |
|Now I've been hired by a small company as their resident expert and |
|I'm finding I have to relearn everything all over again..." |
|---------------------------------------------------------------------|

Welcome back!

|---------------------------------------------------------------------|
|" I'm sure |
|my mistakes are novice but I'm not even sure where to go for help." |
|---------------------------------------------------------------------|

This newsgroup is excellent.

|---------------------------------------------------------------------|
|"[. . .] |
|[. . .] I'm not sure where else to start. Are there any |
|good reference books you guys would recommend? |
| |
|[. . .]" |
|---------------------------------------------------------------------|

Read this newsgroup. There are partial archives on the Internet.

Post to this newsgroup.

Read the FAQ on


Read books. Get the latest edition
of "The Designer's Guide to VHDL" by Peter J. Ashenden:
WWW.Ashenden.com.Au
Also read (later) the
book "VHDL Answers to Frequently Asked Questions"
by Ben Cohen which is different from the FAQ on
WWW.VHDL.org/comp.lang.vhdl/
but is well worth reading.

 

[GaborSzakacs]

f.kazemnia@gmail.com wrote:

On Friday, November 10, 2000 12:00:00 AM UTC-8, frederic thierry wrote:
has anyone got a VHDL source or information for a MP3 encoder for a
student project ?

Thanks

http://lmgtfy.com/?q=VHDL+MP3+encoder

--Gabor

 

On Friday, November 10, 2000 12:00:00 AM UTC-8, frederic thierry wrote:

has anyone got a VHDL source or information for a MP3 encoder for a
student project ?

Thanks

 

Looking for design engineers in Michigan - mail to allen.pegasys@gmail.com


On Sunday, June 14, 1998 3:00:00 AM UTC-4, Umesh D. Painaik wrote:

Dear Sir/Mam,

I am applying for a full time job position of design engineer in your
company.

I am currently pursuing a Master's degree in Electrical engineering
at Michigan Technological University and will be graduating in
July '98. I have been working with the VLSI group in MTU on various
modelling and design aspects of VLSI interconnections. I am also a teaching
assistant in Michigan tech.

My coursework at Michigan Tech and Vivekanand Institute of technology (my
undergraduate school) has prepared me well to contribute to your
organisation. My analytical and logical skills have been
sharpened by several design projects which are a part of the
course curriculum.

A strong personal work ethic, an outgoing personality, and a desire
to excel combined with my work experience assures that I will be a
suitable candidate. A call to my references will assure that I have
the technical and interpersonal skills to make working enjoyable as
well as productive.

I have enclosed my resume with this letter and I would greatly
appreciate an oppurtunity to further discuss my qualifications with
you at your convenience. I can be reached by phone at "906-487-6154"
and also by e-mail at "udpainai@mtu.edu"

Thank you for your consideration. I look forward to hearing from you.

Sincerely,
Umesh Painaik



OBJECTIVE :
Application for a design engineer position.


NAME : Umesh D. Painaik

HOME ADDRESS : 225 Hubbel St. ,apt 1
Houghton ,MI 49931-1533
phone- 906-487-6154

WORK ADDRESS : Michigan Technological University
1400 ,Townsend drive
Houghton ,MI 49931-1533

E-Mail : udpainai@mtu.edu


EMPLOYMENT HISTORY :1) Worked in Patni Computer Services as a Junior
Design Engineer from 2/96 to 8/96
2) Teaching Assistant at Michigan Tech. University
From 10/96 to till date.
Recitation in pspice network analysis, Magic and
VLSI design.


EDUCATIONAL BACKGROUND : 1)B.E. ELECTRONICS ,VESIT ,BOMBAY,1996. GPA 3.6
2)Currently in Second year M.S.E.E. with VLSI
option in Michigan Tech univ.,GPA 3.7.


ADDITIONAL SKILLS : 1) Knowledge of VHDL,MAGIC,VIEWSIM,Schematics,
Verilog(Learning),Powerview,Xilinx
(Learning),Cadence Valid, Altera MAX+PLUS2,
Smartspice,Spice,Athena,Atlas,TCAD
2) Knowledge of C,HTML,Java(Learning),UNIX,DOS
3) Taken courses in
-- Advanced electronic design
-- VLSI (GaAs)interconnections
-- Advanced semiconductor physics
-- Advanced microprocessors and memory elements
-- Computer architecture
-- Digital signal processing
-- Digital communication
-- VLSI fabrication
3) Thesis topic- `Multisectional Interconnections'


RESEARCH BACKGROUND : 1) Project leader in Developing a `DRAM
Controller' using Powerview and viewsim in
undergrad.
2) Surveys on `SiC applications' and `Ion
implantation using Lasers'.
3) Research on `Frequency variance in High speed
semiconductor interconnections' in summer
97-98.
4) Developement and simulation of `DRAM
Controller' and 'Hamming decoder'using VHDL.
5) Currently working on CADENCE VALID and TCAD.
6) Currently working on a proposal topic
`High Speed Multisection interconnections and
their feasibility'


HONORS : 1) Dean's list in two successive years in
undergraduate studies.
2) Best programmer's award in undergraduate studies.


OTHER INTERESTS : 1) Treasurer of Indian students association in
Michigan Tech
2) Student body President in Undergrad University.
3) Graduate Student Council member in Michigan Tech.
4) Member of the Soccer team.
5) Member of Worldwide Indian network.

VISA STATUS : F1-Visa


AVAILABILITY : July 1998 (Willing to relocate)


REFERENCES : Available upon request

 

[John Speth]

I think Allen Pegasys shows a serious lack of professional ethics and
respect by broadcasting somebody's personal information to the world.

Once it gets on usenet, there's no getting it back.

JJS

On 4/25/2013 12:41 PM, allen.pegasys@gmail.com wrote:

Looking for design engineers in Michigan - mail to allen.pegasys@gmail.com


On Sunday, June 14, 1998 3:00:00 AM UTC-4, Umesh D. Painaik wrote:
Dear Sir/Mam,

( personal cover letter and resume deleted )

 

בתאריך יום שני, 16 בספטמבר 2002 17:55:02 UTC+2, מאת itsme:

Hi,
I like to write a techbench which
uses random numbers for input data
to test my hardware.
Does VHDL has a built in random number generator?
Is there any library?
thanks,
peter

You may find this helpful
"...
--random numbers generation
signal rand_ttl_delta : std_logic_vector(3 downto 0) := "1000";
signal rand_ttl_deltai : integer := 8;
....
rand_ttl_delta <= f_my_rand (4, rand_ttl_delta);
-- 3 2 1
-- 109876543210987654321098765
if(o_tot_cnt(31 downto 5) = "000000000000000000000000000") then
--small changes during average calculation (learning state)
gen_rand := "00" & rand_ttl_delta(1 downto 0);
else
gen_rand := rand_ttl_delta;
end if;
tmp_ptr.data := tmp_ptr.data + gen_rand;
--
write(my_line, string'("gen_rand "));
hwrite(my_line, tmp_ptr.data);
write(my_line, string'(" "));
--write(my_line, gen_ipv4);
hwrite(my_line, o_tot_cnt);
write(my_line, string'(" "));
write(my_line, now);
writeline(output, my_line);
...."
"...
--random number
function f_my_rand(width : integer; temp_2 : std_logic_vector)
return std_logic_vector is

constant temp_c : std_logic_vector(width-2 downto 0):=
temp_2(width-2 downto 0);
variable rand_temp : std_logic_vector(width-1 downto 0): '1' & temp_c;
variable temp : std_logic := '0';
variable random_num : std_logic_vector(width-1 downto 0);
variable my_line : line;
begin
temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(0) := temp;
random_num := rand_temp;

--if(DEBUG = '1') then
--write(my_line, string'("f_my_rand "));
--hwrite(my_line, random_num);
--writeline(output, my_line);
--end if;
return random_num;
end f_my_rand;
...."

http://bknpk.no-ip.biz/my_web/SDIO/ip_ttl_filter_ttl_rand.html
http://bknpk.no-ip.biz/my_web/MiscellaneousHW/vhdl_func_rand.html

This was done as part of IP filter VHDL bench and design:
"...
how I randomize the TTL field values. In this project I have already discussed the issue of generating random numbers. While previous case was merely delay between packets, this one is a little bit complex. When the DUT is in learning state (see FSM description), small changes in the TTL are required. Later an attack scenario is presented to the DUT, by vhdl bench.
...."

 

בתאריך יום שלישי, 22 בספטמבר 1998 09:00:00 UTC+2, מאת Chris Plachta:

Hello,

I've been looking for a simple way to generate random (or pseudorandom)
std_logic_vectors. I haven't found any standard random number
generation command in VHDL. All I really need to do is crank out bytes
of random data for simulation purposes.

Suggestions?

--
Chris Plachta
Alcatel USA
Phone: 707-792-7271
FAX: 707-792-6310

Take a look at bknpk vhdl:
"...
This page explains how I randomize the TTL field values. In this project I have already discussed the issue of generating random numbers. While previous case was merely delay between packets, this one is a little bit complex. When the DUT is in learning state (see FSM description), small changes in the TTL are required. Later an attack scenario is presented to the DUT, by vhdl bench.

--random numbers generation
signal rand_ttl_delta : std_logic_vector(3 downto 0) := "1000";
signal rand_ttl_deltai : integer := 8;
....
rand_ttl_delta <= f_my_rand (4, rand_ttl_delta);
-- 3 2 1
-- 109876543210987654321098765
if(o_tot_cnt(31 downto 5) = "000000000000000000000000000") then
--small changes during average calculation (learning state)
gen_rand := "00" & rand_ttl_delta(1 downto 0);
else
gen_rand := rand_ttl_delta;
end if;
tmp_ptr.data := tmp_ptr.data + gen_rand;
--
write(my_line, string'("gen_rand "));
hwrite(my_line, tmp_ptr.data);
write(my_line, string'(" "));
--write(my_line, gen_ipv4);
hwrite(my_line, o_tot_cnt);
write(my_line, string'(" "));
write(my_line, now);
writeline(output, my_line);
...."
http://bknpk.no-ip.biz/my_web/SDIO/ip_ttl_filter_ttl_rand.html

 

בתאריך יום חמישי, 10 ביולי 1997 10:00:00 UTC+3, מאת Tim Holmes:

Could anyone tell me how to create a "random" number generator in
VHDL. I imagine that the only method is to use a LFSR approach with
a seed.

If there are any other ideas, then please let me know.

Cheers.

Tim
Hewlett Packard

Take a look at bknpk vhdl:
"...
This page explains how I randomize the TTL field values. In this project I have already discussed the issue of generating random numbers. While previous case was merely delay between packets, this one is a little bit complex. When the DUT is in learning state (see FSM description), small changes in the TTL are required. Later an attack scenario is presented to the DUT, by vhdl bench.

--random numbers generation
signal rand_ttl_delta : std_logic_vector(3 downto 0) := "1000";
signal rand_ttl_deltai : integer := 8;
....
rand_ttl_delta <= f_my_rand (4, rand_ttl_delta);
-- 3 2 1
-- 109876543210987654321098765
if(o_tot_cnt(31 downto 5) = "000000000000000000000000000") then
--small changes during average calculation (learning state)
gen_rand := "00" & rand_ttl_delta(1 downto 0);
else
gen_rand := rand_ttl_delta;
end if;
tmp_ptr.data := tmp_ptr.data + gen_rand;
--
write(my_line, string'("gen_rand "));
hwrite(my_line, tmp_ptr.data);
write(my_line, string'(" "));
--write(my_line, gen_ipv4);
hwrite(my_line, o_tot_cnt);
write(my_line, string'(" "));
write(my_line, now);
writeline(output, my_line);
...."
http://bknpk.no-ip.biz/my_web/SDIO/ip_ttl_filter_ttl_rand.html

 

בתאריך יום חמישי, 17 בינואר 2002 15:10:08 UTC+2, מאת Pamm:

How can I solve this problem?

code example:
First call the text library:
use STD.textio.all;
use IEEE.STD_LOGIC_TEXTIO.all;

In the process declare a line variable like this:
variable my_line : line;


Now you can print in your code. Here is an example:
write(my_line, string'(" HMASTER_q "));
STD.textio.hwrite(my_line, HMASTER_q);
write(my_line, string'(" at "));
write(my_line, now);
writeline(output, my_line);

taken from bknpk vhdl
http://bknpk.no-ip.biz/my_web/MiscellaneousHW/vhdl_print_debug_tip.html

 

בתאריך יום ראשון, 10 במאי 1998 10:00:00 UTC+3, מאת Oscar F.:

Hello :

Where can I find information about TEXTIO functions ? (read, readline, etc)

--
------------------------------
Saludos,
Oscar Ferrero.
E-mail : oscarf@jet.es
Web : http://web.jet.es/~oscarf

Here is a simple read file example





Very simple, VHDL standalone bench, to demonstrate text file read, from a VHDL bench.
In this site I put many articles that help me in the assorted projects (design, verification). This site is also targeted to help student. Most of the stuff is free, but some are not. Projects

People who saw this page were also interested in the following work: IP TTL filter where to use and why is it required


This VHDL shows how to read text from a file. The file contains nibble in ASCII text (1101) in each line.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use STD.textio.all;

ENTITY tb_read IS
END tb_read;

ARCHITECTURE beha OF tb_read IS

signal bin_value : std_logic_vector(3 downto 0):="0000";

BEGIN

--Read process
process
file fp : text;

variable line_content : string(1 to 4);
variable line_num : line;
variable j : integer := 0;
variable char : character:='0';
begin
--0001
--0010
file_open(fp,"stim.txt", READ_MODE);
while not endfile(fp) loop
readline (fp, line_num);
READ (line_num, line_content);
for j in 1 to 4 loop
char := line_content(j);
if(char = '0') then
bin_value(4-j) <= '0';
else
bin_value(4-j) <= '1';
end if;
end loop;
wait for 10 ns; --after reading each line wait for 10ns.
end loop;
file_close(fp); --after reading all the lines close the file.
wait for 10 ns;
assert false report "end of test" severity error;
end process;

taken from bknpk vhdl
http://bknpk.no-ip.biz/my_web/MiscellaneousHW/vhdl_read_text_file.html

 

On Tuesday, 14 March 2000 13:30:00 UTC+5:30, Cheol-Min Han wrote:

Hi all.

I want get to fir or iir VHDL source.

 

I am also looking for this code, please help me ((((

Many thanks,
Hamid.

hsoleimani88@gmail.com

 

[MK]

On 15/12/2013 21:16, hsoleimani88@gmail.com wrote:

I am also looking for this code, please help me ((((

Many thanks,
Hamid.

hsoleimani88@gmail.com

Last time I did this sort of stuff (about 20 years ago) we used HCMOS
logic and some of the very early Xilinx 64 and 100 logic cell FPGAs. It
wasn't that hard.

What's your actual problem here ?

If you are looking for plug in IP I think you will need to pay for it -
if you are stuck with something then you need to explain what you are
trying to do.

Michael Kellett

 

On Saturday, September 25, 1999 2:00:00 PM UTC+7, Pradeep Rao wrote:

As part of my final year project, I'm working on designing a Reed-Solomon
codec using VHDL. We also intend to transport this design to a FPGA. I would
like to know about the resources required to acheive the above.
I would also be grateful if someone could give me tips and mention common
pitfalls to avoid, since I'm working in a limited timeframe.
Thank you.
pradeep

bạn có còn tất cả tài liệu liên quan về reed solomon ko .gửi qua mail mình được ko.mail: annguyen10111305@gmail.com

 

[Andy]

Are you sure the generics are set the same in simulation as they are in synthesis?

To protect yourself against that in your test, you might want to use to_signed(tmp_cor, tmp_cor'length).

Andy

 

15 Mayıs 2002 Çarşamba 23:07:03 UTC+3 tarihinde Christian yazdı:

Hello!
I know this newsgroup is specially ybout VHDL. But I am curently working
with Altera's derivation AHDL.
My question isn't quite language related but more general:

How would you create a decoder which generates BCD-coding from normal 8bit
binary coding?
I want to control several 7 segment displays and therefore have to use BCD
coding.

I'd be very happy to get any kind of help.
Regards
Chris.

 

I realize that this is a rather old thread, but it's still one of the first Google search results, so I think it's worth a note here.

On www.vide-software.at (or directly from Visual Studio's Extension Manager) you can download an extension for Visual Studio. It offers syntax & semantic highlighting, code completion, code snippets, enhanced navigation features, etc. etc.
It's free for students & teachers, there is a 30-day trial license, and there is a rather cheap private license for non-commercial use.

Regards,
Markus