Clock Edge notation

On Tuesday, September 17, 2002 at 12:27:21 PM UTC+3, DJohn wrote:
Hi all VHDL experts,
Is there any tools which can convert a C\C++ source file to VHDL . For
example If I have a C source code for a MP3 decoder , Can any tool can
convert it into VHDL equivalent. There is some facility in FPGA Advantage to
generate a wrapper VHDL for a C File , what exactly is that ? Does that
mean I can synthesize a C\C++ file by creating a VHDL Wrapper.
Please help

Take a look at Handel-C. All you have to do is to rewrite couple of statements so that Handel-C compiles and generates VHDL, Verilog, EDIF, and SystemC for you. Use Mentor Graphic DK Design Suite 5.
 
<ahmedablak0@gmail.com> wrote in message
news:0ae05f82-6d7f-49f9-9b00-1da23034e98c@googlegroups.com...
On Tuesday, September 17, 2002 at 12:27:21 PM UTC+3, DJohn wrote:
Hi all VHDL experts,
Is there any tools which can convert a C\C++ source file to VHDL . For
example If I have a C source code for a MP3 decoder , Can any tool can
convert it into VHDL equivalent. There is some facility in FPGA Advantage
to
generate a wrapper VHDL for a C File , what exactly is that ? Does that
mean I can synthesize a C\C++ file by creating a VHDL Wrapper.
Please help

Take a look at Handel-C. All you have to do is to rewrite couple of
statements so that Handel-C compiles and generates VHDL, Verilog, EDIF,
and SystemC for you. Use Mentor Graphic DK Design Suite 5.

Why not to have a look at Vivado HLS? Altera also has something, that will
be available soon.
 
On Sun, 27 Sep 2015 19:24:47 -0700, fl wrote:

Hi,

I remember that I see a code writing on part signal with 'not' logic as:


instance_name : complexMul0
port map (
ar => not(ar),
ai => ai,
br => br,
bi => bi,
clk => CK,
pr => pr,
pi => pi);


Today, when I write the above style and simulate with Modelsim, it gives
error:

(vcom-1436) Actual expression (prefix expression) of formal "ar" is not
globally static.



Could you help me on explain what 'globally static' is?
What VHDL standard allow/dis-allow 'not' logic prefix?

Add quotes around the not like this instead:


port map (
ar => "not"(ar),
ai => ai,
br => br,


You are not allowed to use general expressions in a port map, however
you are allowed to use function calls with at most one signal argument.
This allows type conversions, etc. but not general purpose logic
expressions of multiple signals. I'm not sure why they decided on this
limitation.

The "" quotes made a difference by turning an expression (which is
illegal) into a function call (which is legal).

Globally static roughly means that a name can be resolved at elaboration
time. C.f. locally static, which roughly means that a name can be
resolved at compilation time.
If the compiler is saying that something isn't globally static, then it
still can't work out what to do even after elaboration.

I feel that Modelsim could have given a better error message in this case.

Regards,
Allan
 
On 28/09/2015 12:45, Allan Herriman wrote:
On Sun, 27 Sep 2015 19:24:47 -0700, fl wrote:

Hi,

I remember that I see a code writing on part signal with 'not' logic as:


instance_name : complexMul0
port map (
ar => not(ar),
ai => ai,
br => br,
bi => bi,
clk => CK,
pr => pr,
pi => pi);


Today, when I write the above style and simulate with Modelsim, it gives
error:

(vcom-1436) Actual expression (prefix expression) of formal "ar" is not
globally static.



Could you help me on explain what 'globally static' is?
What VHDL standard allow/dis-allow 'not' logic prefix?


Add quotes around the not like this instead:


port map (
ar => "not"(ar),
ai => ai,
br => br,


You are not allowed to use general expressions in a port map, however
you are allowed to use function calls with at most one signal argument.
This allows type conversions, etc. but not general purpose logic
expressions of multiple signals. I'm not sure why they decided on this
limitation.

The "" quotes made a difference by turning an expression (which is
illegal) into a function call (which is legal).

Globally static roughly means that a name can be resolved at elaboration
time. C.f. locally static, which roughly means that a name can be
resolved at compilation time.
If the compiler is saying that something isn't globally static, then it
still can't work out what to do even after elaboration.

I feel that Modelsim could have given a better error message in this case.

Just use verror (cmd prompt or modelsim transcript) to get more info:

D:\>verror 1436

vcom Message # 1436:
VHDL 1993 through VHDL 2002 allowed an expression to be associated with
a formal port in a port map as long as the expression was globally
static and the port was of mode IN. VHDL 2008 now allows non-static
expressions as well. Use the -2008 switch to vcom to enable this
feature.
[DOC: IEEE Std 1076-2002 VHDL LRM - 1.1.1.2 Ports]
[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.6.3 Port clause]

Regards,
Hans
www.ht-lab.com


Regards,
Allan
 
Some small clarifications:

1) Type Conversion Functions
Between unrelated types. Requires an explicit function.

Example - Unsigned to Integer, to_integer(U)
2) Type Conversions (what many of us also call type casting)
From 1076-2008, Section 9.3.6, p 137
Explicit type conversions are allowed between closely related types. In particular, a type is closely related to itself. Other types are closely related only under the following conditions:
-- Abstract numeric types -- Any abstract numeric type is closely related to any other abstract numeric type.
-- Array types--Two array types are closely related if and only if the types have the same dimensionality and the element types are closely related\

No other types are closely related.

Example - Unsigned to signed, signed('0' & X_uv)

3) Type qualifier

Specifies type when unclear. String arrays can be a number of types, so
require a qualifier to indicate the type. There can be multiple
overloaded functions with the same input types but different return
types, again a qualifier is required to resolve the issue.

Example - Z_sv <= A_sv + signed'("1010") ;

4) Automatic Type Conversion:
Two types convert automatically when both are subtypes of the same type. Combine this with every type is a subtype of itself, and you can conclude that two types will convert automatically when one is a subtype of the other.

Hence, std_ulogic automatically converts to std_logic.

Also in VHDL-2008, std_logic_vector is defined as:
subtype std_logic_vector is {resolved} std_ulogic_vector ;

Hence, in VHDL-2008, these two also convert automatically.

This implies that in VHDL-2008 if you have an old package that includes overloading for both std_ulogic_vector and std_logic_vector, you need to remove one of them or it becomes ambiguous.


I think this lists the ways that types are converted or indicated.

Just trying to refresh my memory.

The VHDL Tricks of the Trade (from which you borrowed examples) is still available at: http://synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

Jim
 
Am Dienstag, 27. Oktober 2015 22:06:23 UTC+1 schrieb rickman:
On 10/27/2015 3:21 PM, Mark Curry wrote:
To be honest, it has been so long that I don't remember all of the
reasons.
[..]
I know there are other issues with them as well, so they are best
forgotten.

The major issue with std_logic_arith and similar (std_logic_unsigned,...) is that they are NOT standardized. They are tool dependend (original from Synopsys) and from LRM point of view illegal extensions to libray IEEE, as this library shall contain only standarized packages.
If simulation and synthesis result for these packages differ, you have nobody to complain about (beside the code autor, who dares to use non standard)..

In addition to numeric_std, there are new packages for signed and
unsigned arithmetic on SLV, (std_logic_signed and std_logic_unsigned).
These new packages will have the same issue of not working together
since they define the same operator on the same types, but otherwise
will work ok. I just use signed and unsigned types from the std_numeric
library. Life is good.

Std_logic_unsigned and std_logic_signed are not "new packages" compared to numeric_std, they are extensions from Synopsys for the std_logic_arith and usually used in combination with arith with similar issues than arith alone.

regards,

Thomas
 
On 10/28/2015 5:10 AM, Thomas Stanka wrote:
Am Dienstag, 27. Oktober 2015 22:06:23 UTC+1 schrieb rickman:
On 10/27/2015 3:21 PM, Mark Curry wrote: To be honest, it has been
so long that I don't remember all of the reasons.
[..]
I know there are other issues with them as well, so they are best
forgotten.

The major issue with std_logic_arith and similar
(std_logic_unsigned,...) is that they are NOT standardized. They are
tool dependend (original from Synopsys) and from LRM point of view
illegal extensions to libray IEEE, as this library shall contain only
standarized packages. If simulation and synthesis result for these
packages differ, you have nobody to complain about (beside the code
autor, who dares to use non standard).

In addition to numeric_std, there are new packages for signed and
unsigned arithmetic on SLV, (std_logic_signed and
std_logic_unsigned). These new packages will have the same issue of
not working together since they define the same operator on the
same types, but otherwise will work ok. I just use signed and
unsigned types from the std_numeric library. Life is good.

Std_logic_unsigned and std_logic_signed are not "new packages"
compared to numeric_std, they are extensions from Synopsys for the
std_logic_arith and usually used in combination with arith with
similar issues than arith alone.

Yes, sorry, I got my names mixed up. I meant to say
"numeric_std_unsigned and numeric_std_signed". I'm actually not sure
how widely these are supported. I only find 1600 hits on a google
search for numeric_std_unsigned and only about 100 for
numeric_std_signed. But I find them both mentioned as part of VHDL-2008
at the Doulos site, so I figure they know what they are talking about...
maybe.

--

Rick
 
hi sir.....
iam trying to understand the lookup table for 8b/10b encoder..but its not getting to how the values are come for rd- and rd+.
i have a doubt on lookup tables on 8b/10b encoder..please give me clear explanation of 8b/10b encoder and how its come 6b and 4b in table...
is there any concept of getting 6b and 4b in encoder(rd- and rd+).
 
On 1/4/2016 11:31 AM, ravalitngp@gmail.com wrote:
hi sir.....
iam trying to understand the lookup table for 8b/10b encoder..but its not getting to how the values are come for rd- and rd+.
i have a doubt on lookup tables on 8b/10b encoder..please give me clear explanation of 8b/10b encoder and how its come 6b and 4b in table...
is there any concept of getting 6b and 4b in encoder(rd- and rd+).

Wikipedia seems to explain this pretty well.

https://en.wikipedia.org/wiki/8b/10b_encoding#How_it_works_for_the_IBM_code

It appears that the 8b/10b code is actually done by concatenating a pair
of codes, 5b/6b and 3b/4b. Read the wiki page and come back with any
questions you have on it.

I have a question for you. Are rd+ and rd- differential signals or two
separate signals from your hardware? Do you know what the waveforms
look like on these signals?

--

Rick
 
iam doing project on 8b/10b encoder...idnt know how the lookup tables values came??please give me the explanation of the lookup tables..
 
On 1/11/2016 10:16 AM, ravalitngp@gmail.com wrote:
> iam doing project on 8b/10b encoder...idnt know how the lookup tables values came??please give me the explanation of the lookup tables..

You have unencoded data bits which you use as an address to fetch the
data from the encode lookup table for the encoded data. In reverse you
have encoded data which you use as an address into a decode table to
fetch the decoded data.

I'm not sure I understand your question.

--

Rick
 
Hai everyone,

i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command.
 
On 2/3/2016 9:35 AM, purnachandrarao.b@gmail.com wrote:
Hai everyone,

i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command.

You can try the assert command. When the assertion is not true it can
print a report that typically includes a time stamp by the simulator.
No need to actually code up the time I believe.

--

Rick
 
On Wednesday, 3 February 2016 16:51:52 UTC+1, rickman wrote:
On 2/3/2016 9:35 AM, purnachandrarao.b@gmail.com wrote:
Hai everyone,

i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command.

You can try the assert command. When the assertion is not true it can
print a report that typically includes a time stamp by the simulator.
No need to actually code up the time I believe.

--

Rick

thanks for the answer but the assert will use for the result which we are not expecting. But i like to print the signals with time whenever the signal changes in the given parameters. please check the $monitor verilog command for better understanding. I want the exactly the same output in VHDL too.......

Purna
 
Le 03/02/2016 23:35, purnachandrarao.b@gmail.com a ĂŠcrit :
On Wednesday, 3 February 2016 16:51:52 UTC+1, rickman wrote:
On 2/3/2016 9:35 AM, purnachandrarao.b@gmail.com wrote:
Hai everyone,

i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command.

You can try the assert command. When the assertion is not true it can
print a report that typically includes a time stamp by the simulator.
No need to actually code up the time I believe.

--

Rick

thanks for the answer but the assert will use for the result which we are not expecting. But i like to print the signals with time whenever the signal changes in the given parameters. please check the $monitor verilog command for better understanding. I want the exactly the same output in VHDL too......

Use a process:

monitor : process(monitored_signal)
begin
report "monitored_signal has changed" severity note;
end process monitor;

I think messages are time-stamped by he simulator. In case they're not,
adding a time stamp to the message is left as an exercise.

Nicolas
 
On 2/3/2016 5:35 PM, purnachandrarao.b@gmail.com wrote:
On Wednesday, 3 February 2016 16:51:52 UTC+1, rickman wrote:
On 2/3/2016 9:35 AM, purnachandrarao.b@gmail.com wrote:
Hai everyone,

i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command.

You can try the assert command. When the assertion is not true it can
print a report that typically includes a time stamp by the simulator.
No need to actually code up the time I believe.

--

Rick

thanks for the answer but the assert will use for the result which we are not expecting.

I don't know what you mean by "the assert will use for the result which
we are not expecting". If you mean the assert statement is for errors,
that is not true. It does not care what you put in the assert statement.
You can use "assert not signal_name'event report "signal changed"
severity NOTE" to give a report each time the signal changes. "signal
changed" is anything you wish to report, but I think the time is
reported always.


> But i like to print the signals with time whenever the signal changes in the given parameters. please check the $monitor verilog command for better understanding. I want the exactly the same output in VHDL too......

Rather than ask me to learn Verilog, how about you let me show you how
to use VHDL? Then you can do what you want with VHDL. Asking people to
spoon feed you is not a good way to get help.

--

Rick
 
On Thursday, 4 February 2016 03:07:27 UTC+1, rickman wrote:
On 2/3/2016 5:35 PM, purnachandrarao.b@gmail.com wrote:
On Wednesday, 3 February 2016 16:51:52 UTC+1, rickman wrote:
On 2/3/2016 9:35 AM, purnachandrarao.b@gmail.com wrote:
Hai everyone,

i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command.

You can try the assert command. When the assertion is not true it can
print a report that typically includes a time stamp by the simulator.
No need to actually code up the time I believe.

--

Rick

thanks for the answer but the assert will use for the result which we are not expecting.

I don't know what you mean by "the assert will use for the result which
we are not expecting". If you mean the assert statement is for errors,
that is not true. It does not care what you put in the assert statement.
You can use "assert not signal_name'event report "signal changed"
severity NOTE" to give a report each time the signal changes. "signal
changed" is anything you wish to report, but I think the time is
reported always.


But i like to print the signals with time whenever the signal changes in the given parameters. please check the $monitor verilog command for better understanding. I want the exactly the same output in VHDL too......

Rather than ask me to learn Verilog, how about you let me show you how
to use VHDL? Then you can do what you want with VHDL. Asking people to
spoon feed you is not a good way to get help.

--

Rick

sorry Rick, i don't mean that way.... i tried using the assert but i am getting the other results what i am not expecting. so i asked you in that way... i will try again, thanks for the response

Purna
 
On 2/4/2016 4:49 AM, purnachandrarao.b@gmail.com wrote:
On Thursday, 4 February 2016 03:07:27 UTC+1, rickman wrote:
On 2/3/2016 5:35 PM, purnachandrarao.b@gmail.com wrote:
On Wednesday, 3 February 2016 16:51:52 UTC+1, rickman wrote:
On 2/3/2016 9:35 AM, purnachandrarao.b@gmail.com wrote:
Hai everyone,

i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command.

You can try the assert command. When the assertion is not true it can
print a report that typically includes a time stamp by the simulator.
No need to actually code up the time I believe.

--

Rick

thanks for the answer but the assert will use for the result which we are not expecting.

I don't know what you mean by "the assert will use for the result which
we are not expecting". If you mean the assert statement is for errors,
that is not true. It does not care what you put in the assert statement.
You can use "assert not signal_name'event report "signal changed"
severity NOTE" to give a report each time the signal changes. "signal
changed" is anything you wish to report, but I think the time is
reported always.


But i like to print the signals with time whenever the signal changes in the given parameters. please check the $monitor verilog command for better understanding. I want the exactly the same output in VHDL too......

Rather than ask me to learn Verilog, how about you let me show you how
to use VHDL? Then you can do what you want with VHDL. Asking people to
spoon feed you is not a good way to get help.

--

Rick

sorry Rick, i don't mean that way.... i tried using the assert but i am getting the other results what i am not expecting. so i asked you in that way... i will try again, thanks for the response

Nicolas gives you a another answer and actually gives code. He skips
the assert part of the statement and only uses the report although it
has to be used in a process since report alone is only a sequential
statement. Assert is either sequential or concurrent so can be used in
a process or an architecture.

With the example I provided you should get a report every time the
signal changes. What are you seeing?

--

Rick
 
Nicolas gives you a another answer and actually gives code. He skips
the assert part of the statement and only uses the report although it
has to be used in a process since report alone is only a sequential
statement. Assert is either sequential or concurrent so can be used in
a process or an architecture.

With the example I provided you should get a report every time the
signal changes. What are you seeing?

--

Rick

Rick, Thank you very much for the suggestions. Finally i achieved what i want to implement.
 
On 2/5/2016 4:15 AM, purnachandrarao.b@gmail.com wrote:
Nicolas gives you a another answer and actually gives code. He skips
the assert part of the statement and only uses the report although it
has to be used in a process since report alone is only a sequential
statement. Assert is either sequential or concurrent so can be used in
a process or an architecture.

With the example I provided you should get a report every time the
signal changes. What are you seeing?

--

Rick

Rick, Thank you very much for the suggestions. Finally i achieved what i want to implement.

Glad it worked out.

--

Rick
 

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