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Vince
Guest
niyander a écrit :
A synthesis tool will answer to your question...
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M
Mike Treseler
Guest
On 8/21/2010 8:27 AM, niyander wrote:
Something like the template below.
-- Mike Treseler
main : process(reset, clock) is
begin -- process template
if reset = '1' then
-- init_regs;
elsif rising_edge(clock) then
-- update_regs;
end if;
-- update_ports;
end process main;
end architecture synth;
I would suggest nothing but reset and clock in the sensitivity list.I have written some vhdl code which uses internal multiplier present
in spartan-3 device. Can someone check if this code is synthesizable,
i would appreciate if someone can help me in this.
Something like the template below.
-- Mike Treseler
main : process(reset, clock) is
begin -- process template
if reset = '1' then
-- init_regs;
elsif rising_edge(clock) then
-- update_regs;
end if;
-- update_ports;
end process main;
end architecture synth;
K
KJ
Guest
On Aug 21, 11:27 am, niyander <mightycatniyan...@gmail.com> wrote:
consider downloading one. In both the short and long run you'll be
more productive. Using Quartus, the warnings reported below (*1)
represent conditions under which the logic that gets generated will
*not* match simulation results. (*2)
You should also consider getting rid of the first process and just use
concurrent signals assignments as you did when you commented out the
process portions of your second group. As a general rule you should
try to not use combinatorial (i.e. non-clocked processes) they lead to
design errors such as the ones being reported below as well as latches
if you miss an assignment to a signal under some condition in the
process.
Sometimes one really likes to use statements such as 'if' and 'case'
that are not available in concurrent assignment statements (such as in
your last process). In those cases, if making the process clocked is
not an option, then peruse the synthesis warnings for statements like
the ones listed below since they are actually potential design errors
waiting to trap you. Alternatively, consider implemeting your
'process' code as a function or a procedure instead. At least then
any compiler will flag usage of some signal (such as 'lead0') that is
not formally listed as an input parameter.
Kevin Jennings
(*1)
Warning (10492): VHDL Process Statement warning at Junk.vhd(509):
signal "lead0" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at Junk.vhd(511):
signal "lead0" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning: Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "clk"
(*2) The synthesized result will behave as if 'lead0' was listed in
the sensitivity list. Since it is not, then your simulation will
differ if 'lead0' changes but none of the other signals does not
happen to simultaneously transition. In your case, 'lead0' will
change one simulation delta cycle after product_mantissa(47 or 46)
changes so it won't be simultaneous. Your process for computing
'final_mantissa' will wake up because of the change in
'product_mantissa' (with a soon to be out of date value for 'lead0')
but will not wake up again on the next simulation delta when 'lead0'
actually gets updated.
Synthesis tools are downloadable from the supplier's web site,Hi,
I have written some vhdl code which uses internal multiplier present
in spartan-3 device. Can someone check if this code is synthesizable,
i would appreciate if someone can help me in this.
I am getting desired results in simulation, but i am not sure if this
code is 100% synthesizable.
code:http://anceop.com/vhdl.txt
Thanks
consider downloading one. In both the short and long run you'll be
more productive. Using Quartus, the warnings reported below (*1)
represent conditions under which the logic that gets generated will
*not* match simulation results. (*2)
You should also consider getting rid of the first process and just use
concurrent signals assignments as you did when you commented out the
process portions of your second group. As a general rule you should
try to not use combinatorial (i.e. non-clocked processes) they lead to
design errors such as the ones being reported below as well as latches
if you miss an assignment to a signal under some condition in the
process.
Sometimes one really likes to use statements such as 'if' and 'case'
that are not available in concurrent assignment statements (such as in
your last process). In those cases, if making the process clocked is
not an option, then peruse the synthesis warnings for statements like
the ones listed below since they are actually potential design errors
waiting to trap you. Alternatively, consider implemeting your
'process' code as a function or a procedure instead. At least then
any compiler will flag usage of some signal (such as 'lead0') that is
not formally listed as an input parameter.
Kevin Jennings
(*1)
Warning (10492): VHDL Process Statement warning at Junk.vhd(509):
signal "lead0" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at Junk.vhd(511):
signal "lead0" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning: Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "clk"
(*2) The synthesized result will behave as if 'lead0' was listed in
the sensitivity list. Since it is not, then your simulation will
differ if 'lead0' changes but none of the other signals does not
happen to simultaneously transition. In your case, 'lead0' will
change one simulation delta cycle after product_mantissa(47 or 46)
changes so it won't be simultaneous. Your process for computing
'final_mantissa' will wake up because of the change in
'product_mantissa' (with a soon to be out of date value for 'lead0')
but will not wake up again on the next simulation delta when 'lead0'
actually gets updated.
P
Pranav Pareek
Guest
On Aug 21, 10:57 pm, KJ <kkjenni...@sbcglobal.net> wrote:
Thank you ever one for your valuable comments.On Aug 21, 11:27 am, niyander <mightycatniyan...@gmail.com> wrote:
Hi,
I have written some vhdl code which uses internal multiplier present
in spartan-3 device. Can someone check if this code is synthesizable,
i would appreciate if someone can help me in this.
I am getting desired results in simulation, but i am not sure if this
code is 100% synthesizable.
code:http://anceop.com/vhdl.txt
Thanks
Synthesis tools are downloadable from the supplier's web site,
consider downloading one. In both the short and long run you'll be
more productive. Using Quartus, the warnings reported below (*1)
represent conditions under which the logic that gets generated will
*not* match simulation results. (*2)
You should also consider getting rid of the first process and just use
concurrent signals assignments as you did when you commented out the
process portions of your second group. As a general rule you should
try to not use combinatorial (i.e. non-clocked processes) they lead to
design errors such as the ones being reported below as well as latches
if you miss an assignment to a signal under some condition in the
process.
Sometimes one really likes to use statements such as 'if' and 'case'
that are not available in concurrent assignment statements (such as in
your last process). In those cases, if making the process clocked is
not an option, then peruse the synthesis warnings for statements like
the ones listed below since they are actually potential design errors
waiting to trap you. Alternatively, consider implemeting your
'process' code as a function or a procedure instead. At least then
any compiler will flag usage of some signal (such as 'lead0') that is
not formally listed as an input parameter.
Kevin Jennings
(*1)
Warning (10492): VHDL Process Statement warning at Junk.vhd(509):
signal "lead0" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at Junk.vhd(511):
signal "lead0" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning: Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "clk"
(*2) The synthesized result will behave as if 'lead0' was listed in
the sensitivity list. Since it is not, then your simulation will
differ if 'lead0' changes but none of the other signals does not
happen to simultaneously transition. In your case, 'lead0' will
change one simulation delta cycle after product_mantissa(47 or 46)
changes so it won't be simultaneous. Your process for computing
'final_mantissa' will wake up because of the change in
'product_mantissa' (with a soon to be out of date value for 'lead0')
but will not wake up again on the next simulation delta when 'lead0'
actually gets updated.
M
Mike Treseler
Guest
On Fri, Dec 10, 2010 at 4:42 PM, alessandro basili wrote:
My top entity is a collection of direct
instances of single process entities with port maps.
I use the Quartus rtl viewer to draw a block diagram
from my functional code.
I use a template to simplify the synthesis of variables.
I like to see the wired view, but I let quartus draw it for me.
I also click on on one of the top blocks on the rtl viewer
to verify the structural view of my procedural entity.
I prefer to connect large boxes at the port map level to
connecting processes at the architecture level.
using standard vhdl source code.
immediate assignments,
and letting synthesis sort out the LUTs and flops using my template.
-- Mike Treseler
Dear Mr. Treseler,
few years ago I followed quite closely the comp.arch.fpga and
comp.lang.vhdl
groups and I was fascinated by your template project especially the
testbench style, that I adopted since then.
....
Talking about your template, how do you see multiple component
instantiation
and port mapping, as opposed to your procedural template?
My top entity is a collection of direct
instances of single process entities with port maps.
I use the Quartus rtl viewer to draw a block diagram
from my functional code.
I use a template to simplify the synthesis of variables.
I agree at the top level.I believe that component instantiation offers a black-box view pretty
much
like a schematic entry and it's easy to me to follow, while I don't have
that picture through your procedural template. Am I missing something?
I like to see the wired view, but I let quartus draw it for me.
I also click on on one of the top blocks on the rtl viewer
to verify the structural view of my procedural entity.
I instance single process entities at the top level.Do you think a single process, as opposed to many of them, will
simplify the
datapath and allow for better maintainance of the code?
I prefer to connect large boxes at the port map level to
connecting processes at the architecture level.
I can write functional/procedural code for synthesisWhat is the gain of having variables as opposed to signals?
using standard vhdl source code.
I am very used to writing, siming and tracing code descriptions withI am very used
to signals since I always though that the way values are assigned to a
signal follow pretty much what happens on hardware, while for a variable
there is an abstraction that I am not accustomed to.
immediate assignments,
and letting synthesis sort out the LUTs and flops using my template.
Not a bother in the least.I hope I haven't bother you too much with my questions.
Best regards,
Al
-- Mike Treseler
A
Alessandro Basili
Guest
On 12/11/2010 7:40 AM, Mike Treseler wrote:
boundaries of a component to allow for reusability. But I got your point
of having top levels (which may as well be part of a bigger project)
populated only by components instantiation through port mapping, while
hiding the logic as much as possible.
style, I lack the overall structure view and most of the time I need to
draw down (what I call "paper simulation") the datapath.
Indeed your template collects all the flops and the assignments in one
single tidy place.
procedure template_v_rst is -- My default.
begin -- a_rst is logically equivalent
if reset = '1' then -- Assumes synched trailing edge reset pulse
init_regs; -- reg_v := init_c; Variables only, ports below.
elsif rising_edge(clock) then
update_regs; -- reg_v := f(reg_v);Variables only, ports below.
end if; -- Synchronous init optional (state_v = idle_c)
update_ports; -- will infer port wires ok for reset and clock
end procedure template_v_rst; -- out_port <= reg_v; ports only,
-- no signals
which is only saying that a reset will initialize all the registers and
the clock will update them all, instead of doing this for every single
flop/register/counter in the architecture.
functional/procedural code? and what is standard vhdl? Is there a
non-standard vhdl?
Understood. Indeed one of my biggest problem is where to put theOn Fri, Dec 10, 2010 at 4:42 PM, alessandro basili wrote:
Dear Mr. Treseler,
few years ago I followed quite closely the comp.arch.fpga and
comp.lang.vhdl
groups and I was fascinated by your template project especially the
testbench style, that I adopted since then.
...
Talking about your template, how do you see multiple component
instantiation
and port mapping, as opposed to your procedural template?
My top entity is a collection of direct
instances of single process entities with port maps.
boundaries of a component to allow for reusability. But I got your point
of having top levels (which may as well be part of a bigger project)
populated only by components instantiation through port mapping, while
hiding the logic as much as possible.
Do you know of any open-source software capable of doing that?I use the Quartus rtl viewer to draw a block diagram
from my functional code.
single flops and gates in a multi-process and concurrent assignmentsI believe that component instantiation offers a black-box view pretty
much
like a schematic entry and it's easy to me to follow, while I don't have
that picture through your procedural template. Am I missing something?
I agree at the top level.
I like to see the wired view, but I let quartus draw it for me.
I also click on on one of the top blocks on the rtl viewer
to verify the structural view of my procedural entity.
Actually this is the hardest part for me. If I see pretty well the
style, I lack the overall structure view and most of the time I need to
draw down (what I call "paper simulation") the datapath.
Indeed your template collects all the flops and the assignments in one
single tidy place.
procedure template_v_rst is -- My default.
begin -- a_rst is logically equivalent
if reset = '1' then -- Assumes synched trailing edge reset pulse
init_regs; -- reg_v := init_c; Variables only, ports below.
elsif rising_edge(clock) then
update_regs; -- reg_v := f(reg_v);Variables only, ports below.
end if; -- Synchronous init optional (state_v = idle_c)
update_ports; -- will infer port wires ok for reset and clock
end procedure template_v_rst; -- out_port <= reg_v; ports only,
-- no signals
which is only saying that a reset will initialize all the registers and
the clock will update them all, instead of doing this for every single
flop/register/counter in the architecture.
Apologize but I didn't get your answer. What do you mean withWhat is the gain of having variables as opposed to signals?
I can write functional/procedural code for synthesis
using standard vhdl source code.
functional/procedural code? and what is standard vhdl? Is there a
non-standard vhdl?
I hope I haven't bother you too much with my questions.
Best regards,
Al
Not a bother in the least.
-- Mike Treseler
M
Mike Treseler
Guest
On 12/11/2010 1:13 PM, Alessandro Basili wrote:
Note that direct instances do not require a component declaration.
That is a good starting point for a trial design.
in this schematic of a register stack:
http://mysite.ncnetwork.net/reszotzl/stack.pdf
Now compare that description to the 13 lines of code
in the update_regs procedure here:
http://mysite.ncnetwork.net/reszotzl/stack.vhd
but note that the stack code is working on an abstract array of 32 bit
registers.
vhdl code. That is different than just using vhdl source code
to do the same thing.
Good luck.
-- Mike Treseler
That's it.Talking about your template, how do you see multiple component
instantiation
and port mapping, as opposed to your procedural template?
My top entity is a collection of direct
instances of single process entities with port maps.
Understood. Indeed one of my biggest problem is where to put the
boundaries of a component to allow for reusability. But I got your point
of having top levels (which may as well be part of a bigger project)
populated only by components instantiation through port mapping, while
hiding the logic as much as possible.
Note that direct instances do not require a component declaration.
No, but the free version of quartus/modelsim has it.I use the Quartus rtl viewer to draw a block diagram
from my functional code.
Do you know of any open-source software capable of doing that?
That is a good starting point for a trial design.
Imagine a vhdl description of the muxes and registersI believe that component instantiation offers a black-box view pretty
much
like a schematic entry and it's easy to me to follow, while I don't
have
that picture through your procedural template. Am I missing something?
I agree at the top level.
I like to see the wired view, but I let quartus draw it for me.
I also click on on one of the top blocks on the rtl viewer
to verify the structural view of my procedural entity.
Actually this is the hardest part for me. If I see pretty well the
single flops and gates in a multi-process and concurrent assignments
style, I lack the overall structure view and most of the time I need to
draw down (what I call "paper simulation") the datapath.
in this schematic of a register stack:
http://mysite.ncnetwork.net/reszotzl/stack.pdf
Now compare that description to the 13 lines of code
in the update_regs procedure here:
http://mysite.ncnetwork.net/reszotzl/stack.vhd
Yes. That's the idea.Indeed your template collects all the flops and the assignments in one
single tidy place.
Yes, I still have to write the 3 procedures and run a sim to check them,procedure template_v_rst is -- My default.
begin -- a_rst is logically equivalent
if reset = '1' then -- Assumes synched trailing edge reset pulse
init_regs; -- reg_v := init_c; Variables only, ports below.
elsif rising_edge(clock) then
update_regs; -- reg_v := f(reg_v);Variables only, ports below.
end if; -- Synchronous init optional (state_v = idle_c)
update_ports; -- will infer port wires ok for reset and clock
end procedure template_v_rst; -- out_port <= reg_v; ports only,
-- no signals
which is only saying that a reset will initialize all the registers and
the clock will update them all, instead of doing this for every single
flop/register/counter in the architecture.
but note that the stack code is working on an abstract array of 32 bit
registers.
Code using variables, functions and procedures for hardware synthesis.What is the gain of having variables as opposed to signals?
I can write functional/procedural code for synthesis
using standard vhdl source code.
Apologize but I didn't get your answer. What do you mean with
functional/procedural code?
There are functional languages based on c or python that can *generate*Is there a
non-standard vhdl?
vhdl code. That is different than just using vhdl source code
to do the same thing.
Good luck.
-- Mike Treseler
T
Trygve Laugstřl
Guest
On Friday, February 11, 2011 1:37:18 AM UTC+1, Andy wrote:
http://en.wikipedia.org/wiki/Rubber_duck_debugging
--
Trygve
The concept even has a name!It is a well known fact that posting unsolved problems on the internet
improves vision. ;^)
http://en.wikipedia.org/wiki/Rubber_duck_debugging
--
Trygve
C
catherine saranya
Guest
Hey simon,
did you manage to get the code for this? I really need it too- if u do have it can u post it on the forum.
Thanks
did you manage to get the code for this? I really need it too- if u do have it can u post it on the forum.
Thanks
A
Aliaksei
Guest
http://wavedrom.googlecode.com
WaveDrom is Free and Open Source online digital timing diagram editor that uses JavaScript?, HTML5 and SVG to render WaveJSON input text description into vector graphics.
The project is in progress. Any feedback appreciated.
WaveDrom is Free and Open Source online digital timing diagram editor that uses JavaScript?, HTML5 and SVG to render WaveJSON input text description into vector graphics.
The project is in progress. Any feedback appreciated.
A
Alessandro Basili
Guest
Mr. Google did not find this article/book (I don't know what it is).
Mr. Amazon did not find this article/book (same as before...).
It is mentioned in the vmkr documentation by Bell-Northern Research VHDL
Group
(http://www.pldworld.com/_hdl/1/tech-www.informatik.uni-hamburg.de/vhdl/tools/vmkr/doc/vmkr.doc.ps)
but no other references found.
Does anyone know where I can find this article/book?
As a parting note, does anyone have any suggestion/recommendation on the
usage of vmkr?
Al
--
A: Because it fouls the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Mr. Amazon did not find this article/book (same as before...).
It is mentioned in the vmkr documentation by Bell-Northern Research VHDL
Group
(http://www.pldworld.com/_hdl/1/tech-www.informatik.uni-hamburg.de/vhdl/tools/vmkr/doc/vmkr.doc.ps)
but no other references found.
Does anyone know where I can find this article/book?
As a parting note, does anyone have any suggestion/recommendation on the
usage of vmkr?
Al
--
A: Because it fouls the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
N
nemgreen@gmail.com
Guest
ModelSim and Questa have the vmake command to build a makefile from a compiled library:
vmake
The vmake utility allows you to use a UNIX or Windows MAKE program to maintain individual libraries. You run vmake on a compiled design library. This utility operates on multiple source files per design unit; it supports Verilog include files as well as Verilog and VHDL PSL vunit files.
vmake
The vmake utility allows you to use a UNIX or Windows MAKE program to maintain individual libraries. You run vmake on a compiled design library. This utility operates on multiple source files per design unit; it supports Verilog include files as well as Verilog and VHDL PSL vunit files.
A
Alan Fitch
Guest
On 19/07/11 11:36, Alessandro Basili wrote:
http://verificationguild.com (I think, from memory). Janick started the
website, and often posts there,
regards
Alan
--
Alan Fitch
Try posting your message on the Verification GuildMr. Google did not find this article/book (I don't know what it is).
Mr. Amazon did not find this article/book (same as before...).
It is mentioned in the vmkr documentation by Bell-Northern Research VHDL
Group
(http://www.pldworld.com/_hdl/1/tech-www.informatik.uni-hamburg.de/vhdl/tools/vmkr/doc/vmkr.doc.ps)
but no other references found.
Does anyone know where I can find this article/book?
As a parting note, does anyone have any suggestion/recommendation on the
usage of vmkr?
Al
http://verificationguild.com (I think, from memory). Janick started the
website, and often posts there,
regards
Alan
--
Alan Fitch
D
Daniel Leu
Guest
On Jul 19, 3:36 am, Alessandro Basili <alessandro.bas...@cern.ch>
wrote:
bergeron":
- www.vhdl.org/misc/ModelingGuidelines.paper.ps
- pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf
Regards,
Daniel
wrote:
Google provides some links if you just search for "makefilesMr. Google did not find this article/book (I don't know what it is).
Mr. Amazon did not find this article/book (same as before...).
It is mentioned in the vmkr documentation by Bell-Northern Research VHDL
Group
(http://www.pldworld.com/_hdl/1/tech-www.informatik.uni-hamburg.de/vhd...)
but no other references found.
Does anyone know where I can find this article/book?
As a parting note, does anyone have any suggestion/recommendation on the
usage of vmkr?
bergeron":
- www.vhdl.org/misc/ModelingGuidelines.paper.ps
- pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf
Regards,
Daniel
A
Alessandro Basili
Guest
On 7/20/2011 7:14 PM, Daniel Leu wrote:
Models in a Team Environment".
Thanks for pointing them out, I'm trying to subscribe to "Verification
Guild" but I still have some problems.
This (IMHO very interesting) article is "Guidelines for Writing VHDLGoogle provides some links if you just search for "makefiles
bergeron":
- www.vhdl.org/misc/ModelingGuidelines.paper.ps
Models in a Team Environment".
This is "Managing VHDL Models with Makefiles".- pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf
Thanks for pointing them out, I'm trying to subscribe to "Verification
Guild" but I still have some problems.
A
Alessandro Basili
Guest
On 7/20/2011 1:31 AM, Alan Fitch wrote:
this one:
"Managing VHDL Models with Makefiles" by Janick Bergeron
(http://pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf)
In case somebody maybe interested, the article in the subject is indeedTry posting your message on the Verification Guild
http://verificationguild.com (I think, from memory). Janick started the
website, and often posts there,
this one:
"Managing VHDL Models with Makefiles" by Janick Bergeron
(http://pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf)
A
Alessandro Basili
Guest
On 7/25/2011 2:57 PM, hssig wrote:
In case somebody maybe interested, the article in the subject is indeed
In case somebody maybe interested, the article in the subject is indeed
http://sourceforge.net/projects/vmk/this one:
"Managing VHDL Models with Makefiles" by Janick Bergeron
(http://pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf)
Where can the tools described be downloaded ?
Cheers, hssig
H
hssig
Guest
On 24 Jul., 00:27, Alessandro Basili <alessandro.bas...@cern.ch>
wrote:
Where can the tools described be downloaded ?
Cheers, hssig
wrote:
On 7/20/2011 1:31 AM, Alan Fitch wrote:
Try posting your message on the Verification Guild
http://verificationguild.com(I think, from memory). Janick started the
website, and often posts there,
In case somebody maybe interested, the article in the subject is indeed
this one:
"Managing VHDL Models with Makefiles" by Janick Bergeron
(http://pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf)
Where can the tools described be downloaded ?
Cheers, hssig
A
Alessandro Basili
Guest
On 7/27/2011 2:36 PM, hssig wrote:
http://www.cygwin.com/
you should be able to install with a simple "make" command from the top
level directory.
I have to say I have not tried it yet. Just looking into it these days.
I think it is possible, if you have cygwin installed:Is there a possibility to use that tool under Windows (7) ? How do I
have to install it?
http://www.cygwin.com/
you should be able to install with a simple "make" command from the top
level directory.
I have to say I have not tried it yet. Just looking into it these days.
Cheers,
hssig
H
hssig
Guest
Is there a possibility to use that tool under Windows (7) ? How do I
have to install it?
Cheers,
hssig
have to install it?
Cheers,
hssig