PLL tricks

[Jeroen Belleman]

On 2014-09-26 16:53, Bill Sloman wrote:

On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the amplitude
information and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce overlapped
results (of any length) on every cycle of the 155.52 MHz clock. So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

There's no intrinsic 1944 sample latency if you are using an A/D
converter to sample the 10MHz reference sine wave at 155.52MHz.

With infinite computational resources you could do a non-linear
least-squares fit of a 10MHz-ish sine wave to anything more than about
four successive samples - since you can be pretty confident that you are
looking at a 10MHz sine wave. With a few as 16 samples - if there was
hardly any noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

The 10MHz sine wave would be described by four parameters - frequency,
absolute phase, amplitude and DC offset. The DC offset ought to be zero,
but A/D converters aren't perfect.
[...]

That's funny. Here is that weird idea again of using an FFT to close
a PLL. People seem preconditioned: To detect a frequency, use an FFT.
That's not appropriate here. An FFT is a block algorithm. For a PLL
you need a stream algorithm. OK, it can work if the loop bandwidth
is diminutive, but it's *so* overwrought.

I had that same 'conflict' when I was designing the beam trajectory
measurement of the CERN PS. From a signal processing point of view,
its core is basically a PLL following the beam around. Someone in
our group also wanted to use FFTs.

Fortunately the stream algorithm prevailed. It's very similar to
what you propose: Digitize the input signal at a high rate and
lock an NCO to some interesting spectral line using an all-
numerical PLL. Mind you, I wouldn't have bothered to digitize
the input signal if I hadn't needed to do some other processing
on it as well and I don't think that in John's case this is the
way to go.

Jeroen Belleman

 

[rickman]

On 9/26/2014 9:08 AM, Phil Hobbs wrote:

On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann

ghf@hoffmann-hochfrequenz.de> wrote:



Am 25.09.2014 um 04:40 schrieb John Larkin:



If I shaped the rising edge of the 10 MHz square wave, and digitized

that with a wideband ADC triggered at 80 KHz, I'd get an ADC code
that

was about linear on phase error with full-span of 50 ps or some
such.

Even 8 bits would get the LSB into the sub-ps range. Then do a
digital

PID loop driving a DAC into the VCO input. I do something vaguely

similar in my DDGs.



Even more radical, digitize the 10 MHz sine wave at 155.52 MHz
sample

rate and do a monstrous amount of math.



I had proposed that already for the almost all digital solution.

The filter after the 10 MHz digitizer could be a FIR and you get

zero crossings given by 2 samples 7 ns apart, each with say 16 bits.

The monstrous math would be just interpolation between 2 samples,

maybe 3 samples if you want to remove corner cases.



I didn't have in mind any filtering of the sampled 10 MHz sinewave

data; just an enormous amount of math. We'd expect the samples to have

a pattern, namely a 10M sine wave sampled at 155.52. Any deviation

from that would generate a loop error, into the VCO. I'm not sure what

the algorithm would be (maybe some sort of cross-correlation?) but it

wouldn't be edge oriented.


should be straight forward pretty much a variation of a costas loops
I guess,

quadrature DDS, multipliers and filters

http://en.wikipedia.org/wiki/Costas_loop#mediaviewer/File:Costas_loop_general_siangls.svg




-Lasse

How about "take 1944 samples, do a DFT, throw out the amplitude
information
and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce overlapped
results (of any length) on every cycle of the 155.52 MHz clock. So no
need to wait 12.5 microseconds to close the loop.


There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

That's why I said the calculations can be done with any length. No need
to average over 1944 samples...

ISTM that the main issues with the B-B loop are: (1) gross PD ripple;
(b) the huge and poorly controlled gain of the phase detector, which
will depend critically on the residual wideband jitter of the two
clocks; and (c), that all the wideband jitter of the VCXO will be
aliased down into the fundamental interval.

Any metastability worries can be got round by reclocking the PD output
from either one of the oscillators, which won't cause significant extra
latency in an 80-kHz loop. Wrapping the VCXO inside a simple wideband
fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM none
will accomplish the required long-term timing stability.)

The residual drift and low-frequency crap could be removed afterwards,
using the bang-bang PD to control a varactor phase shifter on the 10 MHz
sine wave input. The combination ought to be pretty impressive.

--

Rick

 

[rickman]

On 9/26/2014 10:53 AM, Bill Sloman wrote:

On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the amplitude
information and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce overlapped
results (of any length) on every cycle of the 155.52 MHz clock. So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

There's no intrinsic 1944 sample latency if you are using an A/D
converter to sample the 10MHz reference sine wave at 155.52MHz.

With infinite computational resources you could do a non-linear
least-squares fit of a 10MHz-ish sine wave to anything more than about
four successive samples - since you can be pretty confident that you are
looking at a 10MHz sine wave. With a few as 16 samples - if there was
hardly any noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

The 10MHz sine wave would be described by four parameters - frequency,
absolute phase, amplitude and DC offset. The DC offset ought to be zero,
but A/D converters aren't perfect.

Since John actually wants only about 500Hz bandwidth in his PLL feedback
path, worrying about a 12.5usec latency implicit in the 1944 sample
repeat cycle is probably not a useful exercise, even if it were real.

ISTM that the main issues with the B-B loop are: (1) gross PD ripple;
(b) the huge and poorly controlled gain of the phase detector, which
will depend critically on the residual wideband jitter of the two
clocks; and (c), that all the wideband jitter of the VCXO will be
aliased down into the fundamental interval.

Any metastability worries can be got round by reclocking the PD output
from either one of the oscillators, which won't cause significant extra
latency in an 80-kHz loop. Wrapping the VCXO inside a simple wideband
fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM none
will accomplish the required long-term timing stability.)

The residual drift and low-frequency crap could be removed afterwards,
using the bang-bang PD to control a varactor phase shifter on the 10 MHz
sine wave input. The combination ought to be pretty impressive.

One would be impressed that he'd got it to work, less impressed by the
fact that he hadn't been able to recognise the superiority of any of the
better schemes that have been proposed here.

My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter sampling at
155.52MHz and feeding a number cruncher embedded in a reasonably big
programmable logic device. He mentioned a Xilinx Spartan-6

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/

I'm old-fashioned - I find anything more powerful than 22V10 a trifle
intimidating, though I did some useful stuff with the PA7024 (which is a
more powerful drop-in replacement for 22V10).

Why does it need to be a "reasonably big" Spartan 6? It can be a low
power iCE40 device and have tons of room left over.

--

Rick

 

[rickman]

On 9/26/2014 11:27 AM, Jeroen Belleman wrote:

On 2014-09-26 16:53, Bill Sloman wrote:
On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the amplitude
information and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce
overlapped
results (of any length) on every cycle of the 155.52 MHz clock. So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

There's no intrinsic 1944 sample latency if you are using an A/D
converter to sample the 10MHz reference sine wave at 155.52MHz.

With infinite computational resources you could do a non-linear
least-squares fit of a 10MHz-ish sine wave to anything more than about
four successive samples - since you can be pretty confident that you are
looking at a 10MHz sine wave. With a few as 16 samples - if there was
hardly any noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

The 10MHz sine wave would be described by four parameters - frequency,
absolute phase, amplitude and DC offset. The DC offset ought to be zero,
but A/D converters aren't perfect.
[...]

That's funny. Here is that weird idea again of using an FFT to close
a PLL. People seem preconditioned: To detect a frequency, use an FFT.
That's not appropriate here. An FFT is a block algorithm. For a PLL
you need a stream algorithm. OK, it can work if the loop bandwidth
is diminutive, but it's *so* overwrought.

I had that same 'conflict' when I was designing the beam trajectory
measurement of the CERN PS. From a signal processing point of view,
its core is basically a PLL following the beam around. Someone in
our group also wanted to use FFTs.

Fortunately the stream algorithm prevailed. It's very similar to
what you propose: Digitize the input signal at a high rate and
lock an NCO to some interesting spectral line using an all-
numerical PLL. Mind you, I wouldn't have bothered to digitize
the input signal if I hadn't needed to do some other processing
on it as well and I don't think that in John's case this is the
way to go.

Where did anyone say FFT?

--

Rick

 

[Kevin Aylward]

"Bill Sloman" wrote in message news:m03ukr$n3k$1@dont-email.me...

My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter sampling at
155.52MHz and feeding a number cruncher embedded in a reasonably big
programmable logic device. He mentioned a Xilinx Spartan-6

As an analog man, this is fingernails down a blackboard...

Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

 

[Gerhard Hoffmann]

Am 26.09.2014 um 18:34 schrieb rickman:

Why does it need to be a "reasonably big" Spartan 6? It can be a low
power iCE40 device and have tons of room left over.

I took spartan6 as an example because I used it to test some filters,
and my DDS with a huge sine table compiled to run > 200 MHz without
any effort.

Gerhard

(who currently must design a prehistoric original Virtex since they
have been bought a long time ago for a space project :-( )

 

[rickman]

On 9/26/2014 11:04 AM, John Larkin wrote:

On Fri, 26 Sep 2014 09:08:31 -0400, Phil Hobbs
hobbs@electrooptical.net> wrote:

On 9/26/2014 3:02 AM, rickman wrote:

Yeah, and the calculations can very easily be done to produce overlapped
results (of any length) on every cycle of the 155.52 MHz clock. So no
need to wait 12.5 microseconds to close the loop.


There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

The problem that I see is that, if all the sinewave samples contribute
to the lock phase, then the sine wave has to be incredibly pure, and
the ADC incredibly accurate. A better algorithm would use the sinewave
samples for the HF part of the loop but something else for the DC
pull-in. And I still need to get the 1 PPS into there.

Actually when doing the phase calculations the out of band noise is
filtered out giving better resolution of the phase. The bandwidth will
be a function of the length of the data used in the calculations.

I think your 1 pps is a red herring. You are filtering to a very low
bandwidth when controlling the VCXO. So jitter in the phase measurement
is filtered out anyway. If the sine wave is handling the "HF part",
that is what will give you your ps control.

ISTM that the main issues with the B-B loop are: (1) gross PD ripple;

I think that will be OK, if the VCXO is good. Slow loop filter.

(b) the huge and poorly controlled gain of the phase detector, which
will depend critically on the residual wideband jitter of the two
clocks;

I don't care too much if it's uncontrolled, as long as it's huge!


and (c), that all the wideband jitter of the VCXO will be
aliased down into the fundamental interval.

Low VCXO jitter is the goal. I think it can be kept down in the low ps
RMS.

If you are running the control signal through a low pass filter, how
will jitter in the high sample rate phase measurement get passed through?

Wrapping the VCXO inside a simple wideband
fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM none
will accomplish the required long-term timing stability.)

The residual drift and low-frequency crap could be removed afterwards,
using the bang-bang PD to control a varactor phase shifter on the 10 MHz
sine wave input. The combination ought to be pretty impressive.

Bangbang is the ultimate timing feedback. If the loop filter can't
attenuate the bangbang noise enough to keep the jitter down, I'll need
some faster AC-coupled feedback thing to fix that, some classical
RFish thing.

The problem is your bang bang detector has a low update rate and so is
harder to filter. It provides a good measurement, but adds its own
modulation to the control signal.

The DSP approach gives as high an update rate as you would like without
a lot of complication in the processing, but it may not be as sensitive.

Bottom line is these two approaches should be analyzed to see which one
can work better. I'm not sure why this is dragging out so much. Do you
have the job or are you still working the proposal?

--

Rick

 

[rickman]

On 9/26/2014 12:52 PM, Gerhard Hoffmann wrote:

Am 26.09.2014 um 18:34 schrieb rickman:

Why does it need to be a "reasonably big" Spartan 6? It can be a low
power iCE40 device and have tons of room left over.

I took spartan6 as an example because I used it to test some filters,
and my DDS with a huge sine table compiled to run > 200 MHz without
any effort.

Gerhard

(who currently must design a prehistoric original Virtex since they
have been bought a long time ago for a space project :-( )

I just get tired of the biases many designers have against FPGAs because
they are considered to be big, power hungry and complicated to use (lots
of power voltages, humongous packages, etc).

FPGAs are available in many sizes, low power and small packages. There
still aren't many in simple packages, most are some type of fine pitch
part or BGA (or both), but that is seldom a problem these days.

--

Rick

 

[Phil Hobbs]

On 9/26/2014 10:53 AM, Bill Sloman wrote:

On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the amplitude
information and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce overlapped
results (of any length) on every cycle of the 155.52 MHz clock. So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

There's no intrinsic 1944 sample latency if you are using an A/D
converter to sample the 10MHz reference sine wave at 155.52MHz.

There's nothing magic about FFTs--each channel is equivalent to a bog
standard FIR filter. The filter has to be causal, so since it's 1944
samples wide, the delay has to be at least half that.

With infinite computational resources you could do a non-linear
least-squares fit of a 10MHz-ish sine wave to anything more than about
four successive samples - since you can be pretty confident that you are
looking at a 10MHz sine wave. With a few as 16 samples - if there was
hardly any noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

You keep ignoring drift.

The 10MHz sine wave would be described by four parameters - frequency,
absolute phase, amplitude and DC offset. The DC offset ought to be zero,
but A/D converters aren't perfect.

Since John actually wants only about 500Hz bandwidth in his PLL feedback
path, worrying about a 12.5usec latency implicit in the 1944 sample
repeat cycle is probably not a useful exercise, even if it were real.

Which it is (972 samples' worth, anyway).

ISTM that the main issues with the B-B loop are: (1) gross PD ripple;
(b) the huge and poorly controlled gain of the phase detector, which
will depend critically on the residual wideband jitter of the two
clocks; and (c), that all the wideband jitter of the VCXO will be
aliased down into the fundamental interval.

Any metastability worries can be got round by reclocking the PD output
from either one of the oscillators, which won't cause significant extra
latency in an 80-kHz loop. Wrapping the VCXO inside a simple wideband
fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM none
will accomplish the required long-term timing stability.)

The residual drift and low-frequency crap could be removed afterwards,
using the bang-bang PD to control a varactor phase shifter on the 10 MHz
sine wave input. The combination ought to be pretty impressive.

One would be impressed that he'd got it to work, less impressed by the
fact that he hadn't been able to recognise the superiority of any of the
better schemes that have been proposed here.

Most of which ignore drift. A picosecond is not a long time.

My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter sampling at
155.52MHz and feeding a number cruncher embedded in a reasonably big
programmable logic device. He mentioned a Xilinx Spartan-6

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/

A pretty big hammer to replace a single D-flop!

I'm old-fashioned - I find anything more powerful than 22V10 a trifle
intimidating, though I did some useful stuff with the PA7024 (which is a
more powerful drop-in replacement for 22V10).

Dangerous Prototypes sells some nice Xilinx XC9572XL CPLD breakout
boards with JTAG headers. The software is free, if clunky, and you can
get a programming cable from Digilent for $50. (You can also build your
own from published plans.)

Verilog is not the absolute most elegant language in history, but it
didn't take me long to get reasonably up to speed.

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[DecadentLinuxUserNumeroUn]

On Fri, 26 Sep 2014 18:52:30 +0200, Gerhard Hoffmann
<ghf@hoffmann-hochfrequenz.de> Gave us:

Am 26.09.2014 um 18:34 schrieb rickman:

Why does it need to be a "reasonably big" Spartan 6? It can be a low
power iCE40 device and have tons of room left over.

I took spartan6 as an example because I used it to test some filters,
and my DDS with a huge sine table compiled to run > 200 MHz without
any effort.

Yes, but in that application, was jitter a concern?

Or better put: Is it not true that jitter was NO concern in that
application?

 

[rickman]

On 9/26/2014 1:13 PM, Phil Hobbs wrote:

On 9/26/2014 10:53 AM, Bill Sloman wrote:
On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the amplitude
information and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce
overlapped
results (of any length) on every cycle of the 155.52 MHz clock. So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

There's no intrinsic 1944 sample latency if you are using an A/D
converter to sample the 10MHz reference sine wave at 155.52MHz.

There's nothing magic about FFTs--each channel is equivalent to a bog
standard FIR filter. The filter has to be causal, so since it's 1944
samples wide, the delay has to be at least half that.

With infinite computational resources you could do a non-linear
least-squares fit of a 10MHz-ish sine wave to anything more than about
four successive samples - since you can be pretty confident that you are
looking at a 10MHz sine wave. With a few as 16 samples - if there was
hardly any noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

You keep ignoring drift.


The 10MHz sine wave would be described by four parameters - frequency,
absolute phase, amplitude and DC offset. The DC offset ought to be zero,
but A/D converters aren't perfect.

Since John actually wants only about 500Hz bandwidth in his PLL feedback
path, worrying about a 12.5usec latency implicit in the 1944 sample
repeat cycle is probably not a useful exercise, even if it were real.

Which it is (972 samples' worth, anyway).


ISTM that the main issues with the B-B loop are: (1) gross PD ripple;
(b) the huge and poorly controlled gain of the phase detector, which
will depend critically on the residual wideband jitter of the two
clocks; and (c), that all the wideband jitter of the VCXO will be
aliased down into the fundamental interval.

Any metastability worries can be got round by reclocking the PD output
from either one of the oscillators, which won't cause significant extra
latency in an 80-kHz loop. Wrapping the VCXO inside a simple wideband
fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM none
will accomplish the required long-term timing stability.)

The residual drift and low-frequency crap could be removed afterwards,
using the bang-bang PD to control a varactor phase shifter on the 10 MHz
sine wave input. The combination ought to be pretty impressive.

One would be impressed that he'd got it to work, less impressed by the
fact that he hadn't been able to recognise the superiority of any of the
better schemes that have been proposed here.

Most of which ignore drift. A picosecond is not a long time.


My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter sampling at
155.52MHz and feeding a number cruncher embedded in a reasonably big
programmable logic device. He mentioned a Xilinx Spartan-6

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/

A pretty big hammer to replace a single D-flop!

I could have sworn there was some other stuff in that design... another
d-flop to start (fancy ECL stuff, and expensive)... a rather tricky
filter and bunches more. Most of that gets replaced with logic in the
FPGA, the ADC and a DAC.

I'm old-fashioned - I find anything more powerful than 22V10 a trifle
intimidating, though I did some useful stuff with the PA7024 (which is a
more powerful drop-in replacement for 22V10).

Dangerous Prototypes sells some nice Xilinx XC9572XL CPLD breakout
boards with JTAG headers. The software is free, if clunky, and you can
get a programming cable from Digilent for $50. (You can also build your
own from published plans.)

Wow! That is an old part and very limited. There are lots better
devices to get familiar with.

What are the published plans for FPGA programming cables? Are you
talking about the ones that require a parallel port on a PC?


--

Rick

 

[jeroen Belleman]

On 26/09/14 18:35, rickman wrote:

On 9/26/2014 11:27 AM, Jeroen Belleman wrote:
On 2014-09-26 16:53, Bill Sloman wrote:
On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the amplitude
information and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce
overlapped
results (of any length) on every cycle of the 155.52 MHz clock. So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

There's no intrinsic 1944 sample latency if you are using an A/D
converter to sample the 10MHz reference sine wave at 155.52MHz.

With infinite computational resources you could do a non-linear
least-squares fit of a 10MHz-ish sine wave to anything more than about
four successive samples - since you can be pretty confident that you are
looking at a 10MHz sine wave. With a few as 16 samples - if there was
hardly any noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

The 10MHz sine wave would be described by four parameters - frequency,
absolute phase, amplitude and DC offset. The DC offset ought to be zero,
but A/D converters aren't perfect.
[...]

That's funny. Here is that weird idea again of using an FFT to close
a PLL. People seem preconditioned: To detect a frequency, use an FFT.
That's not appropriate here. An FFT is a block algorithm. For a PLL
you need a stream algorithm. OK, it can work if the loop bandwidth
is diminutive, but it's *so* overwrought.

I had that same 'conflict' when I was designing the beam trajectory
measurement of the CERN PS. From a signal processing point of view,
its core is basically a PLL following the beam around. Someone in
our group also wanted to use FFTs.

Fortunately the stream algorithm prevailed. It's very similar to
what you propose: Digitize the input signal at a high rate and
lock an NCO to some interesting spectral line using an all-
numerical PLL. Mind you, I wouldn't have bothered to digitize
the input signal if I hadn't needed to do some other processing
on it as well and I don't think that in John's case this is the
way to go.

Where did anyone say FFT?

DFT, actually. Lasse, four or five levels up.

Jeroen belleman

<food for aieo>
<food for aieo>
<food for aieo>
<food for aieo>
<food for aieo>
<food for aieo>
<food for aieo>

 

[Bill Sloman]

On Saturday, 27 September 2014 02:34:10 UTC+10, rickman wrote:

On 9/26/2014 10:53 AM, Bill Sloman wrote:
On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the amplitude
information and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce overlapped
results (of any length) on every cycle of the 155.52 MHz clock. So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

There's no intrinsic 1944 sample latency if you are using an A/D
converter to sample the 10MHz reference sine wave at 155.52MHz.

With infinite computational resources you could do a non-linear
least-squares fit of a 10MHz-ish sine wave to anything more than about
four successive samples - since you can be pretty confident that you are
looking at a 10MHz sine wave. With a few as 16 samples - if there was
hardly any noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

The 10MHz sine wave would be described by four parameters - frequency,
absolute phase, amplitude and DC offset. The DC offset ought to be zero,
but A/D converters aren't perfect.

Since John actually wants only about 500Hz bandwidth in his PLL feedback
path, worrying about a 12.5usec latency implicit in the 1944 sample
repeat cycle is probably not a useful exercise, even if it were real.

ISTM that the main issues with the B-B loop are: (1) gross PD ripple;
(b) the huge and poorly controlled gain of the phase detector, which
will depend critically on the residual wideband jitter of the two
clocks; and (c), that all the wideband jitter of the VCXO will be
aliased down into the fundamental interval.

Any metastability worries can be got round by reclocking the PD output
from either one of the oscillators, which won't cause significant extra
latency in an 80-kHz loop. Wrapping the VCXO inside a simple wideband
fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM none
will accomplish the required long-term timing stability.)

The residual drift and low-frequency crap could be removed afterwards,
using the bang-bang PD to control a varactor phase shifter on the 10 MHz
sine wave input. The combination ought to be pretty impressive.

One would be impressed that he'd got it to work, less impressed by the
fact that he hadn't been able to recognise the superiority of any of the
better schemes that have been proposed here.

My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter sampling at
155.52MHz and feeding a number cruncher embedded in a reasonably big
programmable logic device. He mentioned a Xilinx Spartan-6

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/

I'm old-fashioned - I find anything more powerful than 22V10 a trifle
intimidating, though I did some useful stuff with the PA7024 (which is a
more powerful drop-in replacement for 22V10).

Why does it need to be a "reasonably big" Spartan 6? It can be a low
power iCE40 device and have tons of room left over.

It's got to be fast enough - coping with the output of 16-bit ADC sampling every 6.43nsec is demanding. The last time I tried to do anything like - with 100k ECL - 20nsec proved to be faster than we could manage - mainly because the ECL memory chips we could buy back then weren't all that quick.

A programmable logic chips big enough to offer a couple of thousand 16-bit wide words of static RAM memory would be attractive.

I haven't a clue why Gerhard Hoffmann singled out the Spartan 6. I last used a programmable logic device back in 1998 - and it wasn't a big one. I've thought about using the Philips - now Xilinx - Coolrunner parts for odd projects since then and actually have 25 of them in a box somewhere, but while I did - once - downloaded the Xilinx programming software, my colleague in London persuaded me that programming any digital logic would be a distraction from the work that really needed to be done at the time.

I'd have to do quite a lot of reading before I could work out any useful ideas about anything bigger or faster.

--
Bill Sloman, Sydney

 

[Phil Hobbs]

On 9/26/2014 1:57 PM, rickman wrote:

On 9/26/2014 1:13 PM, Phil Hobbs wrote:
On 9/26/2014 10:53 AM, Bill Sloman wrote:
On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the amplitude
information and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce
overlapped
results (of any length) on every cycle of the 155.52 MHz clock. So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

There's no intrinsic 1944 sample latency if you are using an A/D
converter to sample the 10MHz reference sine wave at 155.52MHz.

There's nothing magic about FFTs--each channel is equivalent to a bog
standard FIR filter. The filter has to be causal, so since it's 1944
samples wide, the delay has to be at least half that.

With infinite computational resources you could do a non-linear
least-squares fit of a 10MHz-ish sine wave to anything more than about
four successive samples - since you can be pretty confident that you are
looking at a 10MHz sine wave. With a few as 16 samples - if there was
hardly any noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

You keep ignoring drift.


The 10MHz sine wave would be described by four parameters - frequency,
absolute phase, amplitude and DC offset. The DC offset ought to be zero,
but A/D converters aren't perfect.

Since John actually wants only about 500Hz bandwidth in his PLL feedback
path, worrying about a 12.5usec latency implicit in the 1944 sample
repeat cycle is probably not a useful exercise, even if it were real.

Which it is (972 samples' worth, anyway).


ISTM that the main issues with the B-B loop are: (1) gross PD ripple;
(b) the huge and poorly controlled gain of the phase detector, which
will depend critically on the residual wideband jitter of the two
clocks; and (c), that all the wideband jitter of the VCXO will be
aliased down into the fundamental interval.

Any metastability worries can be got round by reclocking the PD output
from either one of the oscillators, which won't cause significant extra
latency in an 80-kHz loop. Wrapping the VCXO inside a simple wideband
fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM none
will accomplish the required long-term timing stability.)

The residual drift and low-frequency crap could be removed afterwards,
using the bang-bang PD to control a varactor phase shifter on the 10
MHz
sine wave input. The combination ought to be pretty impressive.

One would be impressed that he'd got it to work, less impressed by the
fact that he hadn't been able to recognise the superiority of any of the
better schemes that have been proposed here.

Most of which ignore drift. A picosecond is not a long time.


My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter sampling at
155.52MHz and feeding a number cruncher embedded in a reasonably big
programmable logic device. He mentioned a Xilinx Spartan-6

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/

A pretty big hammer to replace a single D-flop!

I could have sworn there was some other stuff in that design... another
d-flop to start (fancy ECL stuff, and expensive)... a rather tricky
filter and bunches more. Most of that gets replaced with logic in the
FPGA, the ADC and a DAC.

<man-with-only-a-hammer-alert>

The D-flop costs about $5 in unit quantity, which is pretty cheap for an
FPGA, especially since all the programming effort would be amortized
over 8 whole units.

As for the rest, the 10 MHz will have to be cleaned up in analogue
somehow, because otherwise its jitter will show up in the FPGA's
output--the analogy between DSP and real genuine analogue signal
processing stands or falls by the samples being evenly spaced. Most of
the time that's not such a worry, but for 1 ps timing accuracy, it most
emphatically is.

I'm old-fashioned - I find anything more powerful than 22V10 a trifle
intimidating, though I did some useful stuff with the PA7024 (which is a
more powerful drop-in replacement for 22V10).

Dangerous Prototypes sells some nice Xilinx XC9572XL CPLD breakout
boards with JTAG headers. The software is free, if clunky, and you can
get a programming cable from Digilent for $50. (You can also build your
own from published plans.)

Wow! That is an old part and very limited. There are lots better
devices to get familiar with.

Sure. But it was cheap, did the job, and since there's nothing very
special about different CPLDs, there's nothing obsolete about the
knowledge gained.

What are the published plans for FPGA programming cables? Are you
talking about the ones that require a parallel port on a PC?

I wasn't talking about FPGAs at all.

</man-with-only-a-hammer-alert>

Cheers

Phil Hobbs



--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Bill Sloman]

On 27/09/2014 9:58 AM, Phil Hobbs wrote:

On 9/26/2014 1:57 PM, rickman wrote:
On 9/26/2014 1:13 PM, Phil Hobbs wrote:
On 9/26/2014 10:53 AM, Bill Sloman wrote:
On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John
Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the amplitude
information and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce
overlapped results (of any length) on every cycle of the 155.52 MHz clock.
So no need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

There's no intrinsic 1944 sample latency if you are using an A/D
converter to sample the 10MHz reference sine wave at 155.52MHz.

There's nothing magic about FFTs--each channel is equivalent to a bog
standard FIR filter. The filter has to be causal, so since it's 1944
samples wide, the delay has to be at least half that.

With infinite computational resources you could do a non-linear
least-squares fit of a 10MHz-ish sine wave to anything more than about
four successive samples - since you can be pretty confident that you
are
looking at a 10MHz sine wave. With a few as 16 samples - if there was
hardly any noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

You keep ignoring drift.

The 10MHz sine wave would be described by four parameters - frequency,
absolute phase, amplitude and DC offset. The DC offset ought to be
zero, but A/D converters aren't perfect.

Since John actually wants only about 500Hz bandwidth in his PLL
feedback path, worrying about a 12.5usec latency implicit in the 1944 sample
repeat cycle is probably not a useful exercise, even if it were real.

Which it is (972 samples' worth, anyway).

Only if you let yourself be jammed into the computational
straight-jacket of the DFT or FFT.

ISTM that the main issues with the B-B loop are: (1) gross PD ripple;
(b) the huge and poorly controlled gain of the phase detector, which
will depend critically on the residual wideband jitter of the two
clocks; and (c), that all the wideband jitter of the VCXO will be
aliased down into the fundamental interval.

Any metastability worries can be got round by reclocking the PD output
from either one of the oscillators, which won't cause significant
extra latency in an 80-kHz loop. Wrapping the VCXO inside a simple wideband
fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM
none will accomplish the required long-term timing stability.)

The residual drift and low-frequency crap could be removed afterwards,
using the bang-bang PD to control a varactor phase shifter on the 10
MHz sine wave input. The combination ought to be pretty impressive.

One would be impressed that he'd got it to work, less impressed by the
fact that he hadn't been able to recognise the superiority of any of
the better schemes that have been proposed here.

Most of which ignore drift. A picosecond is not a long time.

They don't. I've got no idea where you got that idea.

My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter
sampling at 155.52MHz and feeding a number cruncher embedded in a reasonably big
programmable logic device. He mentioned a Xilinx Spartan-6

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/

<snip>

As for the rest, the 10 MHz will have to be cleaned up in analogue
somehow, because otherwise its jitter will show up in the FPGA's
output--the analogy between DSP and real genuine analogue signal
processing stands or falls by the samples being evenly spaced. Most of
the time that's not such a worry, but for 1 ps timing accuracy, it most
emphatically is.

The samples will be as evenly spaced as the clock edges coming out of
the 155.52MHz VCXO - which will be very evenly spaced indeed. The fact
that 155.52MHz is not a simple multiple of 10MHz is going to complicate
the digital signal processing, which is why you want to do it a
decent-sized and quick FPGA, but that's a number-crunching exercise, and
The A/D converter approach gives you lots of good numbers to crunch.

There will be no "jitter" on the 10MHz waveform - unless the
GSP-disciplining is done very crudely indeed.

I'm old-fashioned - I find anything more powerful than 22V10 a trifle
intimidating, though I did some useful stuff with the PA7024 (which
is a more powerful drop-in replacement for 22V10).

<snipped unnecessary advice about Xilinx parts>

Sure. But it was cheap, did the job, and since there's nothing very
special about different CPLDs, there's nothing obsolete about the
knowledge gained.

What are the published plans for FPGA programming cables? Are you
talking about the ones that require a parallel port on a PC?

Even I have heard about In-Service Programmable CPLD's, with a serial
programming port.

> I wasn't talking about FPGAs at all.

Just as well.

--
Bill Sloman, Sydney

 

[rickman]

On 9/26/2014 5:08 PM, jeroen Belleman wrote:

On 26/09/14 18:35, rickman wrote:
On 9/26/2014 11:27 AM, Jeroen Belleman wrote:
On 2014-09-26 16:53, Bill Sloman wrote:
On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John
Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the amplitude
information and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce
overlapped
results (of any length) on every cycle of the 155.52 MHz clock.
So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

There's no intrinsic 1944 sample latency if you are using an A/D
converter to sample the 10MHz reference sine wave at 155.52MHz.

With infinite computational resources you could do a non-linear
least-squares fit of a 10MHz-ish sine wave to anything more than about
four successive samples - since you can be pretty confident that you
are
looking at a 10MHz sine wave. With a few as 16 samples - if there was
hardly any noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

The 10MHz sine wave would be described by four parameters - frequency,
absolute phase, amplitude and DC offset. The DC offset ought to be
zero,
but A/D converters aren't perfect.
[...]

That's funny. Here is that weird idea again of using an FFT to close
a PLL. People seem preconditioned: To detect a frequency, use an FFT.
That's not appropriate here. An FFT is a block algorithm. For a PLL
you need a stream algorithm. OK, it can work if the loop bandwidth
is diminutive, but it's *so* overwrought.

I had that same 'conflict' when I was designing the beam trajectory
measurement of the CERN PS. From a signal processing point of view,
its core is basically a PLL following the beam around. Someone in
our group also wanted to use FFTs.

Fortunately the stream algorithm prevailed. It's very similar to
what you propose: Digitize the input signal at a high rate and
lock an NCO to some interesting spectral line using an all-
numerical PLL. Mind you, I wouldn't have bothered to digitize
the input signal if I hadn't needed to do some other processing
on it as well and I don't think that in John's case this is the
way to go.

Where did anyone say FFT?


DFT, actually. Lasse, four or five levels up.

Yes, calculating a single bin of a DFT is a great way to calculate the
phase of a sine wave. What is wrong with that? What would you use?
You said you designed something that was basically a PLL. Well that is
what we are discussing, the phase detector of a PLL. What did you use
to detect the phase?

--

Rick

 

[rickman]

On 9/26/2014 9:50 PM, Bill Sloman wrote:

On Saturday, 27 September 2014 02:34:10 UTC+10, rickman wrote:
On 9/26/2014 10:53 AM, Bill Sloman wrote:
On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the amplitude
information and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce overlapped
results (of any length) on every cycle of the 155.52 MHz clock. So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

There's no intrinsic 1944 sample latency if you are using an A/D
converter to sample the 10MHz reference sine wave at 155.52MHz.

With infinite computational resources you could do a non-linear
least-squares fit of a 10MHz-ish sine wave to anything more than about
four successive samples - since you can be pretty confident that you are
looking at a 10MHz sine wave. With a few as 16 samples - if there was
hardly any noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

The 10MHz sine wave would be described by four parameters - frequency,
absolute phase, amplitude and DC offset. The DC offset ought to be zero,
but A/D converters aren't perfect.

Since John actually wants only about 500Hz bandwidth in his PLL feedback
path, worrying about a 12.5usec latency implicit in the 1944 sample
repeat cycle is probably not a useful exercise, even if it were real.

ISTM that the main issues with the B-B loop are: (1) gross PD ripple;
(b) the huge and poorly controlled gain of the phase detector, which
will depend critically on the residual wideband jitter of the two
clocks; and (c), that all the wideband jitter of the VCXO will be
aliased down into the fundamental interval.

Any metastability worries can be got round by reclocking the PD output
from either one of the oscillators, which won't cause significant extra
latency in an 80-kHz loop. Wrapping the VCXO inside a simple wideband
fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM none
will accomplish the required long-term timing stability.)

The residual drift and low-frequency crap could be removed afterwards,
using the bang-bang PD to control a varactor phase shifter on the 10 MHz
sine wave input. The combination ought to be pretty impressive.

One would be impressed that he'd got it to work, less impressed by the
fact that he hadn't been able to recognise the superiority of any of the
better schemes that have been proposed here.

My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter sampling at
155.52MHz and feeding a number cruncher embedded in a reasonably big
programmable logic device. He mentioned a Xilinx Spartan-6

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/

I'm old-fashioned - I find anything more powerful than 22V10 a trifle
intimidating, though I did some useful stuff with the PA7024 (which is a
more powerful drop-in replacement for 22V10).

Why does it need to be a "reasonably big" Spartan 6? It can be a low
power iCE40 device and have tons of room left over.

It's got to be fast enough - coping with the output of 16-bit ADC sampling every 6.43nsec is demanding. The last time I tried to do anything like - with 100k ECL - 20nsec proved to be faster than we could manage - mainly because the ECL memory chips we could buy back then weren't all that quick.

Wow, trying to design a 200 MHz circuit in ECL would be a massive
design. I worked on a machine that used ECL gate arrays for what
amounts to the ALU of a DSP chip in a whole rack cabinet of circuitry.
That was about forty years ago. Things have changed since then... The
new big is "small". Nearly any FPGA will run multipliers with a 200 MHz
clock. So I don't think accepting inputs from a 16 bit 200 MHz ADC will
be much problem.


> A programmable logic chips big enough to offer a couple of thousand 16-bit wide words of static RAM memory would be attractive.

Nearly *any* FPGA has several thousand bytes of RAM. But they all are
clocked if that makes any difference. No more async RAMs. Many have
100's of kB of RAM on chip... the big brutes.


> I haven't a clue why Gerhard Hoffmann singled out the Spartan 6. I last used a programmable logic device back in 1998 - and it wasn't a big one. I've thought about using the Philips - now Xilinx - Coolrunner parts for odd projects since then and actually have 25 of them in a box somewhere, but while I did - once - downloaded the Xilinx programming software, my colleague in London persuaded me that programming any digital logic would be a distraction from the work that really needed to be done at the time.

I'm not trying to be negative about the Spartan 6 devices. It is just
that any time people mention FPGAs, the image that seems to come to mind
is a big, sweaty, brutish chip that is only considered when everything
else won't do the job. I'm just trying to make a point that there are
many flavors of FPGAs out there across a spectrum, much like other
device families like MCUs and even simple logic. If you say you need to
put a flipflop on your board do you automatically assume that means an
ECL device? No, there are many flavors of logic and the same is true
for programmable logic devices.

The flavor that you mentioned, coolrunner, are actually obsolete.
Coolrunner II is still made I believe, but are functionally obsolete in
that there are lots of much better choices out there.


> I'd have to do quite a lot of reading before I could work out any useful ideas about anything bigger or faster.

Programmable logic can be *very* powerful. I'm not sure why learning
about CPLDs or FPGAs would be a distraction if they could be used in
your designs. It's hard to imagine a design that can't use programmable
logic, at least for me...

BTW, nearly all logic designs are done in an HDL now. So it really
isn't so much an issue of design size. It is very much like writing
software and many of the techniques apply; modules, unit test, test
benches... You just need to be systematic about it and remember that
you aren't writing code as much as describing hardware, hence the name HDL.

--

Rick

 

[rickman]

On 9/26/2014 7:58 PM, Phil Hobbs wrote:

On 9/26/2014 1:57 PM, rickman wrote:
On 9/26/2014 1:13 PM, Phil Hobbs wrote:
On 9/26/2014 10:53 AM, Bill Sloman wrote:
On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John
Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the amplitude
information and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce
overlapped
results (of any length) on every cycle of the 155.52 MHz clock.
So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

There's no intrinsic 1944 sample latency if you are using an A/D
converter to sample the 10MHz reference sine wave at 155.52MHz.

There's nothing magic about FFTs--each channel is equivalent to a bog
standard FIR filter. The filter has to be causal, so since it's 1944
samples wide, the delay has to be at least half that.

With infinite computational resources you could do a non-linear
least-squares fit of a 10MHz-ish sine wave to anything more than about
four successive samples - since you can be pretty confident that you
are
looking at a 10MHz sine wave. With a few as 16 samples - if there was
hardly any noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

You keep ignoring drift.


The 10MHz sine wave would be described by four parameters - frequency,
absolute phase, amplitude and DC offset. The DC offset ought to be
zero,
but A/D converters aren't perfect.

Since John actually wants only about 500Hz bandwidth in his PLL
feedback
path, worrying about a 12.5usec latency implicit in the 1944 sample
repeat cycle is probably not a useful exercise, even if it were real.

Which it is (972 samples' worth, anyway).


ISTM that the main issues with the B-B loop are: (1) gross PD ripple;
(b) the huge and poorly controlled gain of the phase detector, which
will depend critically on the residual wideband jitter of the two
clocks; and (c), that all the wideband jitter of the VCXO will be
aliased down into the fundamental interval.

Any metastability worries can be got round by reclocking the PD output
from either one of the oscillators, which won't cause significant
extra
latency in an 80-kHz loop. Wrapping the VCXO inside a simple wideband
fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM
none
will accomplish the required long-term timing stability.)

The residual drift and low-frequency crap could be removed afterwards,
using the bang-bang PD to control a varactor phase shifter on the 10
MHz
sine wave input. The combination ought to be pretty impressive.

One would be impressed that he'd got it to work, less impressed by the
fact that he hadn't been able to recognise the superiority of any of
the
better schemes that have been proposed here.

Most of which ignore drift. A picosecond is not a long time.


My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter
sampling at
155.52MHz and feeding a number cruncher embedded in a reasonably big
programmable logic device. He mentioned a Xilinx Spartan-6

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/

A pretty big hammer to replace a single D-flop!

I could have sworn there was some other stuff in that design... another
d-flop to start (fancy ECL stuff, and expensive)... a rather tricky
filter and bunches more. Most of that gets replaced with logic in the
FPGA, the ADC and a DAC.

man-with-only-a-hammer-alert

The D-flop costs about $5 in unit quantity, which is pretty cheap for an
FPGA, especially since all the programming effort would be amortized
over 8 whole units.

And the rest??? Doesn't that have NRE design costs?

As for the rest, the 10 MHz will have to be cleaned up in analogue
somehow, because otherwise its jitter will show up in the FPGA's
output--the analogy between DSP and real genuine analogue signal
processing stands or falls by the samples being evenly spaced. Most of
the time that's not such a worry, but for 1 ps timing accuracy, it most
emphatically is.

Not sure which 10 MHz you are talking about, from the bang bang detector
or the signal processing based approach. I'm not sure why there would
be a 10 MHz signal in the signal processing approach.

I'm old-fashioned - I find anything more powerful than 22V10 a trifle
intimidating, though I did some useful stuff with the PA7024 (which
is a
more powerful drop-in replacement for 22V10).

Dangerous Prototypes sells some nice Xilinx XC9572XL CPLD breakout
boards with JTAG headers. The software is free, if clunky, and you can
get a programming cable from Digilent for $50. (You can also build your
own from published plans.)

Wow! That is an old part and very limited. There are lots better
devices to get familiar with.

Sure. But it was cheap, did the job, and since there's nothing very
special about different CPLDs, there's nothing obsolete about the
knowledge gained.

Sure, any port... but that really wasn't anything remotely appropriate
for the issue we are discussing. It's like saying to get familiar with
the design we are talking about by learning how to use an opamp, a good
first step.

What are the published plans for FPGA programming cables? Are you
talking about the ones that require a parallel port on a PC?

I wasn't talking about FPGAs at all.

/man-with-only-a-hammer-alert

Uh, what were you talking about building then?

--

Rick

 

[Bill Sloman]

On 27/09/2014 3:13 AM, Phil Hobbs wrote:

On 9/26/2014 10:53 AM, Bill Sloman wrote:
On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

How about "take 1944 samples, do a DFT, throw out the amplitude
information and run your VCXO from the phase information"?

Yeah, and the calculations can very easily be done to produce
overlapped
results (of any length) on every cycle of the 155.52 MHz clock. So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster. The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

There's no intrinsic 1944 sample latency if you are using an A/D
converter to sample the 10MHz reference sine wave at 155.52MHz.

There's nothing magic about FFTs--each channel is equivalent to a bog
standard FIR filter. The filter has to be causal, so since it's 1944
samples wide, the delay has to be at least half that.

I wasn't talking about FFTs, as I made perfectly clear in the next
sentence. The FFT isn't the be-all and end-all of digital signal
processing. It was always designed as a numerically efficient way of
doing a particular computation, and it isn't clear that that particular
computation is the one that John Larkin ought to be doing.

With infinite computational resources you could do a non-linear
least-squares fit of a 10MHz-ish sine wave to anything more than about
four successive samples - since you can be pretty confident that you are
looking at a 10MHz sine wave. With a few as 16 samples - if there was
hardly any noise - you could probably do well enough to nail John
Larkin's picosecond absolute phase demand.

You keep ignoring drift.

If he could place a single cycle of the 10MHz clock to 1psec in absolute
phase, he'd be in a position to measure cycle-to-cycle drift. The nice
thing about a VCXO is that it doesn't drift much in a single cycle, and
you probably can ignore it within a single cycle.

And it would manifest itself as a small frequency offset, so I didn't
even ignore it.

The 10MHz sine wave would be described by four parameters - frequency,
absolute phase, amplitude and DC offset. The DC offset ought to be zero,
but A/D converters aren't perfect.

Since John actually wants only about 500Hz bandwidth in his PLL feedback
path, worrying about a 12.5usec latency implicit in the 1944 sample
repeat cycle is probably not a useful exercise, even if it were real.

Which it is (972 samples' worth, anyway).

Only if you jam yourself into the straight-jacket of DFT or FFT processing.

ISTM that the main issues with the B-B loop are: (1) gross PD ripple;
(b) the huge and poorly controlled gain of the phase detector, which
will depend critically on the residual wideband jitter of the two
clocks; and (c), that all the wideband jitter of the VCXO will be
aliased down into the fundamental interval.

Any metastability worries can be got round by reclocking the PD output
from either one of the oscillators, which won't cause significant extra
latency in an 80-kHz loop. Wrapping the VCXO inside a simple wideband
fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM none
will accomplish the required long-term timing stability.)

The residual drift and low-frequency crap could be removed afterwards,
using the bang-bang PD to control a varactor phase shifter on the 10 MHz
sine wave input. The combination ought to be pretty impressive.

One would be impressed that he'd got it to work, less impressed by the
fact that he hadn't been able to recognise the superiority of any of the
better schemes that have been proposed here.

Most of which ignore drift. A picosecond is not a long time.

I really don't understand what you mean by "ignoring drift". The whole
point of what John needs to do is to locking the frequency of his
nominally 155.52MHz VCXO to be exactly 155.52MHz vis-a-vis the laser
facility's 10MHz reference. The PLL hardware - which is what we are
talking about here - works out the difference between what is being
measured and the desired output, and changes the VCXO control voltage to
make them less different.

In effect the phase drift is what you are measuring with a view to
fixing it at zero - in the long term.

My money's on Gerhard Hoffmann's 200MHz 16-bit A/D converter sampling at
155.52MHz and feeding a number cruncher embedded in a reasonably big
programmable logic device. He mentioned a Xilinx Spartan-6

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/

A pretty big hammer to replace a single D-flop!

In fact it's the A/D converter that's replacing the single D-flip-flop.
Each time the A/D converter samples, it collects a lot more information
than the D-flip-flop (except at the peak and minimum of the sine wave,
when the A/D converter collects exactly the same information as the
D-flip-flop).

Taking full advantage of the extra information does require a bit more
numerical processing, and a programmable logic device can deliver that.

I'm old-fashioned - I find anything more powerful than 22V10 a trifle
intimidating, though I did some useful stuff with the PA7024 (which is a
more powerful drop-in replacement for 22V10).

Dangerous Prototypes sells some nice Xilinx XC9572XL CPLD breakout
boards with JTAG headers. The software is free, if clunky, and you can
get a programming cable from Digilent for $50. (You can also build your
own from published plans.)

I've got 25 Xilinx Coolrunner parts lying around in a box somewhere, and
once downloaded the Xilinx software that would have let me program them,
but the requirement evaporated.

Verilog is not the absolute most elegant language in history, but it
didn't take me long to get reasonably up to speed.

I used to have a VHDL text-book on my shelves - some project looked as
if it was going to need it, but it died before I did much reading.

I was happy enough with PALASM, and the variant that ICT used for
programming their programmable devices, and I don't imagine that
mastering either Verilog or VHDL would take me all that long, provided
that I had a task to motivate me to do the work.

--
Bill Sloman, Sydney

 

[rickman]

On 9/27/2014 12:23 AM, Bill Sloman wrote:

On 27/09/2014 1:04 AM, John Larkin wrote:
On Fri, 26 Sep 2014 09:08:31 -0400, Phil Hobbs
hobbs@electrooptical.net> wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

snip

Yeah, and the calculations can very easily be done to produce
overlapped
results (of any length) on every cycle of the 155.52 MHz clock. So no
need to wait 12.5 microseconds to close the loop.

There's still the 1944-cycle latency, though, which will make the loop
unstable if you try to go much faster.

There's no necessary 1944-cycle latency. You can design your numerical
processing to avoid it.

The good news is that it
wouldn't have the grotesque output ripple of a bang-bang PD, so it
wouldn't have to be filtered as hard.

The problem that I see is that, if all the sinewave samples contribute
to the lock phase, then the sine wave has to be incredibly pure, and
the ADC incredibly accurate.

Wrong. The numerical processing processing will extract the
phase-frequency information leaving the imperfections in the sine wave
and A/D conversion as just be extra sources of essentially random noise,
on top of the Johnson nose which is always with us.

This clearly indicates what John doesn't understand about signal
processing. One of the problems with the bang bang PD is that the "high
gain" amplifies any noise in the incoming sine wave. I think he is
planning to convert the sine wave to a square wave with an amp or
comparator and that will produce jitter on the clock edge from any noise
at the moment the input crosses the threshold.

The correlation of the sine wave inherently filters out fast noise just
like a FIR filter. The longer the length of the filter, the higher the
noise rejection and the better the measurement of phase. Better to get
rid of it up front than to have to filter it out after the high gain stage.

A better algorithm would use the sinewave
samples for the HF part of the loop but something else for the DC
pull-in. And I still need to get the 1 PPS into there.

You do need to get somebody to think about this who understands the math.

ISTM that the main issues with the B-B loop are: (1) gross PD ripple;

I think that will be OK, if the VCXO is good. Slow loop filter.

The "gross" PD ripple is much less gross and can be a shorter period. As
short as 6.43 ns.

It's still an unnecessary and avoidable source of noise. A better phase
detector - like the 16-bit A/D converter - introduces a lot less noise.

(b) the huge and poorly controlled gain of the phase detector, which
will depend critically on the residual wideband jitter of the two
clocks;

I don't care too much if it's uncontrolled, as long as it's huge!

Sure you do, if you want you feedback loop to be stable and as close to
critically damped as possible. You claim to know about control theory -
think about the implications of an uncertain gain around a feedback loop.

I'm not sure I understand the need for a high gain in the actual PD.
Can't gain be added after the PD?

Actually, I'm not sure that the bang bang PD has high gain exactly since
the gain is nonlinear. It is low for wide phase deltas and high for
small deltas approaching infinity as the delta approaches zero.

You can do exactly the same thing in the digital PD because you can set
any gain you wish. If the phase result is a signed value then just
taking the sign bit will give you the same gain as the bang bang
detector. This can be digitally filtered and the result fed to a
precision DAC replacing the analog filter. If the sample rate is high
enough and the resolution good enough, I expect you can do without an
analog low pass filter altogether.

But with the linear result obtained from the digital PD it seems you can
use a lower order filter with much less delay resulting in a lower
jitter in the VCXO control voltage.

and (c), that all the wideband jitter of the VCXO will be
aliased down into the fundamental interval.

Low VCXO jitter is the goal. I think it can be kept down in the low ps
RMS.

Any metastability worries can be got round by reclocking the PD output
from either one of the oscillators, which won't cause significant extra
latency in an 80-kHz loop.

What, me worry? About metastability? Metastability is the award for
doing everything right.

But you don't need it, and using a D-fip-flop in conditions where it can
generate a metastable output takes it outside the manufacturers
specifications

Wrapping the VCXO inside a simple wideband
fractional-N PLL would improve its phase noise. (Many reasonable
suggestions have been made for that part of the job, of which ISTM none
will accomplish the required long-term timing stability.)

Why Phil Hobbs thinks that escapes me. The logic actually doing the
fractional-n division can be a synchronous ECLinPS counter, and it's
timing stability is hard to beat. You need more logic to tell the
counter when to divide by 15 and when by 16, but that's outside the
timing loop.

The residual drift and low-frequency crap could be removed afterwards,
using the bang-bang PD to control a varactor phase shifter on the 10 MHz
sine wave input. The combination ought to be pretty impressive.

Bangbang is the ultimate timing feedback. If the loop filter can't
attenuate the bangbang noise enough to keep the jitter down, I'll need
some faster AC-coupled feedback thing to fix that, some classical
RFish thing.

The bang-bang phase detector is the silliest possible phase detector for
this application - ultimately silly. The 200MHz A/D converter is a lot
better. Keep thinking about the problem until you've worked out why.

That makes a lot of sense to me. The digital PD in this case can
produce a VCXO control voltage at a high update rate that has very
little modulation before passing through the loop filter. This spreads
any noise over a rather wide bandwidth with very little in the low end
that is inside the control loop frequency range.

The bang bang PD starts with the maximum amount of modulation and runs
at a very low update rate which exacerbates the noise by pushing the
frequency down. Then you need to follow that with an analog filter.
Sounds like a big compromise.

--

Rick