PLL tricks

On Monday, September 22, 2014 9:27:24 AM UTC-4, Jan Panteltje wrote:

dagmargoo...@yahoo.com wrot:
On Saturday, September 20, 2014 5:58:00 AM UTC-4, Jan Panteltje wrote:
dagmargoo...@yahoo.com wrote:

I mentioned microwave bricks...KE5FX has a schematic for one here:

http://www.ke5fx.com/brick/fwbrick.pdf


Microwaves... If you want a free running oscillator,
then the litte ceramic pucks in the satellite LNBs are 9.something and 10.something GHz,
and have really really low noise.

I have a few of those--they're neat. I'm not sure what the resonator Q's
range is. I assumed for starters that making 10GHz to make 155.52 MHz
was getting there the hard way!

Yes, but mixing a few hundred MHz VCO with a 10 GHz that is extremely stable could
perhaps have advantages in some apps.

Sure, like spectrum analyzers do. I was trying to stay close to John's
problem though--I'm pretty sure he'd prefer "simpler."

I found some 1GHz NHK DR pucks with Q's of 40K, but their df/dt was
several ppm.

The output would also be very stable (but needs a filter).


The little yellowish disks on the right:
http://panteltje.com/pub/5_dollar_LNB_PCB_IMG_3582.GIF

Yep, those are DROs (dielectric resonator oscillators), I think. The
structures at 10 and 8 o'clock look like tapped tuned feedback across
the c/e (or more likely s/d) of the transistor.

Not sure which one you mean but you could be on Pacific Time and I am on Central European Time

The lower-frequency center puck, right under the center mounting hole.
Flip description 180 degrees for the high-band puck on the right hand
side.

Anyways, the 2 transistors on the left are connected to a horizontal -, and vertical 1/4 wave dipole wire

in the horn, one or the other is powered depending on the required polarization.

The one directly above the big hole is the first preamp stage, then a 10 - 12 GHz bandpass,
then more to the right the second preamp stage.

All the way top right is the mixer chip.

I would've thought the "Ea" parts are the mixers, diode quads. The filters
are nicely realized on the PCB, and I'd have guessed the right-top chip
you mentioned is an output amplifier.

The resonaters have each a transistor to cause negative impedance so they oscillate,

coupled by the big horseshoe like tracks, one or the other is activated depending on the selected band.
The chip bottom left does the gate control voltage of these FETS, and decoding of the 22 kHz control tone
on the power line, that selects the band, polarization is switched by supply voltage change from 12 to 18 V,
that chip decodes that too.

This is a Universal LNB ("Astra" LNB), see
http://en.wikipedia.org/wiki/Low-noise_block_downconverter


All teh way top right (under the green solder mask) is teh IF filer (about 1.somethin gGHz, longer tracks obviously.

Yep.

> The coupling of the secodn RF stage to the mixer chip is a bit mysterious, looks like and other transformer.

That looks to me like bandswitching by gating two DROs L.O.s to a
single mixer. The DROs are gated on and off, only one running at a time.

The real interesting part is the filter

i u n u i

Almost like tuning forks.

That's a "hair pin" filter. (It's always neat when the board *is*
the circuit.)

The other zig-zag tracks to the transistors are RF chokes basically.
Mind you, this picture is BIG, the real thing is just a few cm,
you need very strong magnification and a steady hand soldering on that.

Thanks for the nice photo--that was fun.

Cheers,
James Arthur

 

[ChesterW]

On 9/21/14, 5:10 PM, John Larkin wrote:

On Sun, 21 Sep 2014 16:57:51 -0500, ChesterW <iamsnoozin@yahoo.com
wrote:

On 9/19/14, 7:37 PM, John Larkin wrote:
On Fri, 19 Sep 2014 18:15:11 -0500, ChesterW <iamsnoozin@yahoo.com
wrote:

On 9/19/14, 4:21 PM, John Larkin wrote:
On Fri, 19 Sep 2014 15:32:07 -0500, ChesterW <iamsnoozin@yahoo.com
wrote:

On 9/16/14, 10:27 AM, John Larkin wrote:
On Tue, 16 Sep 2014 00:21:44 -0500, ChesterW <iamsnoozin@yahoo.com
wrote:

On 9/15/14, 4:55 PM, Phil Hobbs wrote:
snip



*----------------<----------------------------------------*
| |
VCXO *-----* *-----* *-------* |
155.52 MHz ->-- /1944 ->-|D Q|------|D Q|---| LOOP |----*
| | | | | |FILTER |
V *--^--* *--^--* *-------*
| | |
*------->-------* *---<----10MHz REF
Resynch B-B phase det

With maybe a second DFF stage between the phase detector and the loop
filter, to get rid of any noise caused by metastability.

Cheers

Phil Hobbs

It's elegant, but it seems counter-intuitive that the rather tough specs
can be met when throwing away over 99% of the phase comparison
information (1-1/125).

ChesterW

For a constant loop bandwidth, you should get some noise averaging by
doing the phase comparison faster, I agree. However, since you have to
crank down the BW to filter out the gross amounts of ripple from a
bang-bang phase detector, I expect that it won't be that different
inside the BW.

Of course, losing all that loop bandwidth does mean that the VCXO has to
be a lot better than it would with a 10 MHz comparison frequency.

Using local feedback, i.e. a DDS-based or fractional-N loop (wide loop
BW but probably fairly horrible drift) inside an 80-kHz bang-bang loop
would relax the requirements on the VCXO proper.

This is all such fun that I may have to try building something like that.

Cheers

Phil Hobbs


Yes, John Larkin gets the prize for the most interesting project of the
week. Lucky dog.

Here's a possible idea for evaluating the feasibility of different
schemes. Calculate the entropy of the 155.52 MHz signal. Estimate the
frequency drift of the VCXO and represent it as the number of bits of
information lost per 12.5 us update period. Then the feedback needs to
supply at least this number of bits of information to be a possible
solution. If the required feedback SNR is too high, then you know you
need to use the information from more phase comparisons, not just the
easy 12.5 us ones.


Something like that. We'll probably lay out a nice multilayer proto
board with a few candidate VCXO locations, 10 MHz filters, and
dipswitches and trimpots in the loop lowpass filter to make it easy to
tune. Seed that with SMA connectors for analysis, and experiment. Good
intern sort of project.

Putting a cover over the XO, to keep air currents off it, can reduce
jitter a lot.


This is cool:

https://dl.dropboxusercontent.com/u/53724080/Software/PhaseNoise.exe

It was done by one of the s.e.d. guys some time ago; Jeroen? It lets
you convert a phase noise curve to RMS jitter.


Whatever gets results is good. I wonder how intern errors sum. I don't
think it's a half power law, although I suppose it depends on the
intern. Maybe you can hire the re-incarnation of Claude Shannon.

I'm biased toward lots calculation and simulation before building and
fiddling - for complicated systems anyhow. I think it's from working
early in my career without much theory. That was frustrating as hell.

Anyway, I make your 155.52 MHz oscillator with 0.2 ps rms jitter as
containing 15.0 bits of information. When it degrades to 12.7 bits
you're on the edge of your 1 ps error budget. That and how fast it
degrades should set the performance requirements on the feedback loop.

ChesterW


Seems to me that more modulation of a sine wave carries more
information, not less.

Does a perfect sine wave convey an infinite amount of information?



The answer depends on un-supplied details.

In the sense of sending data using a carrier, then more modulation can
mean more information content. It depends on the determinism of the
modulation.

In the sense of sending data using a carrier, then a perfect sine wave
with infinite extent in time conveys zero information.

In the sense of a time reference, a perfect sine wave with zero error
conveys infinite information.

So how about that, the same signal conveys both zero and infinite
information, depending on the question. Reminds me of a story about
imaginary cows that I may post later.

In your oscillator problem I modeled the system as a clock with each
reference tick happening at 1/155.52 MHz. The 0.2 ps rms jitter is the
uncertainty in the time measurement. For these numbers, that's about 1
part in 32k, which requires about 15.0 bits to specify. Since the jitter
is random from cycle to cycle, this represents the maximum precision of
the system which I take as the information content of the (perfectly
aligned) system related to timing.

When the error from sources besides jitter accumulates to your spec of 1
ps, then the system is precise to about 1 part in 6400, or about 12.7
bits. So, when random occurrences cause your system to drift from
perfectly aligned to just out of spec, the time reference has lost about
2.3 bits of information.

So, if you know the drift rate of the timing of the system, then you can
calculate the data loss rate in bits per second. Since bits per second,
bandwidth, and SNR are related in the channel capacity formula, this may
be a tool to evaluate feedback schemes. If the feedback can't supply
enough bps, then it can't control the loop. I think this might set a
necessary but not sufficient condition, which at least may keep you from
wasting time building something that has no chance of working, which of
course is the purpose of analysis in engineering.

ChesterW


Just because you can divide two things that are in the same units, and
convert the result to bits, doesn't mean you should!



The test for the feedback system I gave before should be an easy bar to
pass. I think that because approaching the Shannon limit typically
requires significant cleverness on the part of the designer, and the
limits placed on the feedback loop by your requirement for speed and
precision probably limit the feedback system to fairly simple modulation
methods. These simple methods will likely fall well short of the maximum
theoretical limit on information transfer given by the channel capacity
formula.

What channel do you refer to?



A test that calculates the information content of a specific feedback
signal should come a lot closer to a necessary and sufficient condition.

Calculating and measuring information is just another tool. Eschewing it
is a bit like never learning about Fourier transforms or relying on
intuition instead of Boolean algebra when designing combinatorial logic.

Funny, but I never use Boolean logic or Karnaugh maps or any of those
classic things. I just look at things and draw logic. Given that FPGAs
are LUT based, and compilers do logic reduction for you (whether you
want them to or not), that old stuff hardly matters any more.



One can get along without these things, they just need to be
significantly smarter than if they had used the available tools. I think
that once a certain level of education and experience is reached that
the major limits are in intuition and imagination. I know I can
certainly use all of the helpful tools I can get.

Anyone who thinks information theory is only of academic interest and is
of no use to 'real' designers should read about the work of Claude
Berrou and the founding of Qualcomm.

I can't see how information theory is especially helpful in my PLL
problem. It's a control loop issue.

I’ll try again. Anything to support our nuclear deterrence. Seriously.
By putting our leaders inextricably on the front lines and squarely in
the cross-hairs of any major conflict, those weapons have saved
countless regular folks from being sacrificed in furtherance of
political ambitions. The human world still rings like a bell from the
first effective harnessing of science and industrialization in support
of political leaders stupid plans a century ago. One can still see the
effects in the psychological stunting of anyone spending their formative
years behind the iron curtain. Without those ultimate weapons to keep
them in check, the mischief caused by the world’s leaders would likely
know few bounds. And who knows, maybe the data from all of those lasers
will be the key that enables some smart kid to finally crack fusion
power and we can turn those ugly brown spots on our planet to lovely green.

Communication depends largely on pre-existing shared ideas. I’ll try to
find some common ground. Here’s how I’ve observed myself solving tough
problems, the process of which I think is fairly universal:

Step 1. Get a problem.
Step 2. Use simple analysis and try to show a solution is impossible to
avoid wasting time.
Step 3. Mull it over. Roll the problem around. Really think about it,
even for years sometimes.
Step 4. Have an idea for a solution that I believe will work. The belief
is not completely rational. It’s based on informed intuition. I don’t
know for a fact the idea will work, but I believe it will work.
Step 5. Prove or disprove the idea using analysis and/or simulation
and/or building parts of the system and making measurements.

There is of course a step 0 where one spends considerable time becoming
an expert in some area.

Step 6 is where one writes down all of the analysis for presentation
with little or no reference to the idea’s origin in intuition. I think
this leads to the myth that new ideas come mostly from analysis.

In my view, the main good use of the ‘old tools’ is in step 0. I think
analysis is the easiest way to develop understanding which is what leads
to informed intuition. It’s the difference between an engineer and a
technician. In my experience, the smartest technician, who may be smart
indeed, can usually only come up with solutions better than those of the
worst engineer. I’m not disrespecting technicians, I started out as one,
I’m recognizing the power of learning from those who came before.

So, in recognition of the intrinsic limits of my tiny mark-one human
brain, I made the simplest model of your system I could imagine. The
155.52 MHz osc generates a time reference, which I view as delivering a
time mark with a certain desired precision, which I model as a number
with a defined number of significant digits, and visualize as a bucket
holding an amount of information equal to the number of significant digits.

Left to its self, the osc drifts away from the desired time
synchronization, which I visualize as a loss of precision, or that the
information bucket has a leak.

The feedback loop has a measurement element which senses the loss of
synchronization, which information is routed back to control the osc,
which fills up the bucket. This is the channel to which I referred, and
about which you asked, in previous posts.

The idea is that if the feedback loop does not supply the necessary
information - at least the amount that is lost through the leak, then
the bucket can not stay full, and the system will not stay in sync.

You’ve had a lot of domain experts submit solutions. This is a suggested
tool for use in step 5 for helping evaluate which may work best.

Using information theory to understand control loops is not new. If you
Google “information theory control systems” you’ll find lots of useful
references.

Good luck with your project. Let us hear how it all turns out.

ChesterW

 

[Jan Panteltje]

On a sunny day (Mon, 22 Sep 2014 05:38:05 -0700 (PDT)) it happened
dagmargoodboat@yahoo.com wrote in
<8c170f53-6c91-41e9-8ce0-841f32470311@googlegroups.com>:

On Saturday, September 20, 2014 5:58:00 AM UTC-4, Jan Panteltje wrote:
On a sunny day (Fri, 19 Sep 2014 21:58:16 -0700 (PDT)) it happened

dagmargoo...@yahoo.com wrote:

Here's a web-accessible example from Wenzel:
http://crovencrystals.com/applications/clockosc.htm

Nice.

Given VCOs with resonators of Q>=70K+, that translates to a crystal 3dB
passband on the order of 2-3KHz @ 155MHz. I'm not immediately sure if
that means 80KHz phase comparisons are enough to keep it on track, but
at least it doesn't look ridiculous...

I mentioned microwave bricks...KE5FX has a schematic for one here:
http://www.ke5fx.com/brick/fwbrick.pdf

Microwaves... If you want a free running oscillator,
then the litte ceramic pucks in the satellite LNBs are 9.something and 10.something GHz,
and have really really low noise.

I have a few of those--they're neat. I'm not sure what the resonator Q's
range is. I assumed for starters that making 10GHz to make 155.52 MHz
was getting there the hard way!

Yes, but mixing a few hundred MHz VCO with a 10 GHz that is extremely stable could
perhaps have advantages in some apps.
The output would also be very stable (but needs a filter).

The little yellowish disks on the right:
http://panteltje.com/pub/5_dollar_LNB_PCB_IMG_3582.GIF

Yep, those are DROs (dielectric resonator oscillators), I think. The
structures at 10 and 8 o'clock look like tapped tuned feedback across
the c/e (or more likely s/d) of the transistor.

Not sure which one you mean but you could be on Pacific Time and I am on Central European Time
Anyways, the 2 transistors on the left are connected to a horizontal -, and vertical 1/4 wave dipole wire
in the horn, one or the other is powered depending on the required polarization.
The one directly above the big hole is the first preamp stage, then a 10 - 12 GHz bandpass,
then more to the right the second preamp stage.
All the way top right is the mixer chip.
The resonaters have each a transistor to cause negative impedance so they oscillate,
coupled by the big horseshoe like tracks, one or the other is activated depending on the selected band.
The chip bottom left does the gate control voltage of these FETS, and decoding of the 22 kHz control tone
on the power line, that selects the band, polarization is switched by supply voltage change from 12 to 18 V,
that chip decodes that too.
This is a Universal LNB ("Astra" LNB), see
http://en.wikipedia.org/wiki/Low-noise_block_downconverter

All teh way top right (under the green solder mask) is teh IF filer (about 1.somethin gGHz, longer tracks obviously.
The coupling of the secodn RF stage to the mixer chip is a bit mysterious, looks like and other transformer.

The real interesting part is the filter
i u n u i
Almost like tuning forks.

The other zig-zag tracks to the transistors are RF chokes basically.
Mind you, this picture is BIG, the real thing is just a few cm,
you need very strong magnification and a steady hand soldering on that.

You can bring these down in frequency by mechanical loading, for example by gluing some
parts of a broken one on it.

So mechanical vibrations at 10 GHz, and cheap.

The key is finding a stable piezo or dielectric material with low
frictional or dielectric losses. Quartz wins for mechanical vibration.

One project on the table here is converting a standard LNB to a transmitter for the 10.5 GHz ham band, DVB-S.

This is done by changing the input and output of the 10 GHz pre-amp so it drives the horn,
and is fed from the (ring diode) mixer.

Very low power that is.

And all is very very low phase noise, even after mixing up with those pucks.

http://www.pi6atv.com/index.php?option=com_docman&task=docclick&Itemid=126&bid=299&limitstart=0&limit=10

From:

http://www.pi6atv.com/content/view/47/108/

Now try to simulate that.


I couldn't read the .PCX (pictures(?), but the station display was awfully
cool.

Yes, pictures, I use the xv viewer in Linux, dunno about windows, but pcx is a normal image format.
http://en.wikipedia.org/wiki/PCX

I once worked in a place where there was a guy who would just design these things from a piece of paper,
and they workled too, we made a 10 GHz link, I did the demodulator.
No simulations in that time, used a gun diode... That showed me a lot about microwaves, it is not that hard.

We will see, ordered some real thin coax to make some modifications..

 

On Monday, September 22, 2014 11:20:34 AM UTC-4, John Larkin wrote:

The other interesting part is the ceramic coaxial resonator.

http://t-ceram.com/obr/coaxial_resonators.jpg

These are essentially shorted coaxial lines made with a very hi-K
ceramic dielectric. Qs get into the thousands and TCs are very
low.
They start at about 500 MHz and get really good in the low GHz.

I remember them well. In fact I remember telling you about them and
buying you a handful in S.F.--at Halted, was it?--1998 ;-) (For
possible DDG use.)

But at my frequency, a quartz crystal would have higher Q and lower
TC and phase noise.

Especially the low TC part. 1 GHz drifting 2ppm/C could get a little
squirrely.

Not to mention that I can buy a small VCXO
from stock.

Yep.

I like the microwave brick-style SRD->schottky sampling phase
detector--eliminates the need for one digital divider, and the
need to square up the 155.52 MHz. That's slick.

I assume samplers can be low-jitter. They're used in sampling
scopes, after all.

Cheers,
James Arthur

 

[John Larkin]

On Mon, 22 Sep 2014 07:39:27 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

On Monday, September 22, 2014 9:27:24 AM UTC-4, Jan Panteltje wrote:
dagmargoo...@yahoo.com wrot:
On Saturday, September 20, 2014 5:58:00 AM UTC-4, Jan Panteltje wrote:
dagmargoo...@yahoo.com wrote:

I mentioned microwave bricks...KE5FX has a schematic for one here:

http://www.ke5fx.com/brick/fwbrick.pdf


Microwaves... If you want a free running oscillator,
then the litte ceramic pucks in the satellite LNBs are 9.something and 10.something GHz,
and have really really low noise.

I have a few of those--they're neat. I'm not sure what the resonator Q's
range is. I assumed for starters that making 10GHz to make 155.52 MHz
was getting there the hard way!

Yes, but mixing a few hundred MHz VCO with a 10 GHz that is extremely stable could
perhaps have advantages in some apps.

Sure, like spectrum analyzers do. I was trying to stay close to John's
problem though--I'm pretty sure he'd prefer "simpler."

I found some 1GHz NHK DR pucks with Q's of 40K, but their df/dt was
several ppm.

The output would also be very stable (but needs a filter).


The little yellowish disks on the right:
http://panteltje.com/pub/5_dollar_LNB_PCB_IMG_3582.GIF

Yep, those are DROs (dielectric resonator oscillators), I think. The
structures at 10 and 8 o'clock look like tapped tuned feedback across
the c/e (or more likely s/d) of the transistor.

Not sure which one you mean but you could be on Pacific Time and I am on Central European Time

The lower-frequency center puck, right under the center mounting hole.
Flip description 180 degrees for the high-band puck on the right hand
side.

The other interesting part is the ceramic coaxial resonator.

http://t-ceram.com/obr/coaxial_resonators.jpg

These are essentially shorted coaxial lines made with a very hi-K
ceramic dielectric. Qs get into the thousands and TCs are very low.
They start at about 500 MHz and get really good in the low GHz.

But at my frequency, a quartz crystal would have higher Q and lower TC
and phase noise. Not to mention that I can buy a small VCXO from
stock.

--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Gerhard Hoffmann]

Am 22.09.2014 um 17:20 schrieb John Larkin:

The other interesting part is the ceramic coaxial resonator.

http://t-ceram.com/obr/coaxial_resonators.jpg

These are essentially shorted coaxial lines made with a very hi-K
ceramic dielectric. Qs get into the thousands and TCs are very low.
They start at about 500 MHz and get really good in the low GHz.

BTW, ordinary solder eats the thin silver coating away in no time.

But at my frequency, a quartz crystal would have higher Q and lower TC
and phase noise. Not to mention that I can buy a small VCXO from
stock.

Good crystals at 100 MHz have a Q of 100 - 110K. The product
of Q and operating frequency is abt. constant for a given
crystal technology / quality.

Gerhard

 

[Jan Panteltje]

On a sunny day (Mon, 22 Sep 2014 07:39:27 -0700 (PDT)) it happened
dagmargoodboat@yahoo.com wrote in
<88e24381-6065-4eb7-b43e-d47ada69c2c4@googlegroups.com>:

I would've thought the "Ea" parts are the mixers, diode quads. The filters
are nicely realized on the PCB, and I'd have guessed the right-top chip
you mentioned is an output amplifier.

No, look at this:
http://www.juras-projects.org/files/lumax_lx-lst40.png
I think that is pretty much the circuit diagram of this one too.

http://www.juras-projects.org/eng/hardware.php
That website gives nice info, bottom page.

 

[Jan Panteltje]

On a sunny day (Mon, 22 Sep 2014 08:20:34 -0700) it happened John Larkin
<jlarkin@highlandtechnology.com> wrote in
<d7f02a9b1qffjnqme7v8fjbmbuqnn1mk7a@4ax.com>:

The lower-frequency center puck, right under the center mounting hole.
Flip description 180 degrees for the high-band puck on the right hand
side.

The other interesting part is the ceramic coaxial resonator.

http://t-ceram.com/obr/coaxial_resonators.jpg

These are essentially shorted coaxial lines made with a very hi-K
ceramic dielectric. Qs get into the thousands and TCs are very low.
They start at about 500 MHz and get really good in the low GHz.

Interesting, never seen those, or noticed those.

But at my frequency, a quartz crystal would have higher Q and lower TC
and phase noise. Not to mention that I can buy a small VCXO from
stock.

Yep.

The 'pucks' have a above them an adjustment screw,
a bit like the screws for tuning in cavities,
to get the exact frequency, not sure if those actually touch the ceramic:
http://www.juras-projects.org/images/lnb_1_small.jpg
Those screws are under the red blurbs.

 

[Jan Panteltje]

On a sunny day (Mon, 22 Sep 2014 07:39:27 -0700 (PDT)) it happened
dagmargoodboat@yahoo.com wrote in
<88e24381-6065-4eb7-b43e-d47ada69c2c4@googlegroups.com>:

I would've thought the "Ea" parts are the mixers, diode quads. The filters
are nicely realized on the PCB, and I'd have guessed the right-top chip
you mentioned is an output amplifier.

Well, maybe you are right,
could be active FET mixer...
then I will have to connect the coax a bit differently

 

[Kevin Aylward]

wrote in message
news:b4833087-2e57-4fe7-984a-9b1590f22113@googlegroups.com...

This ovenized VCXO specs -188dBc/Hz @ 100KHz, and -108dBc/Hz @ 10Hz offset:
http://www.wenzel.com/wp-content/parts/501-25900.pdf

When ever I see really low noise, its a given that it uses lots of volts.
You need the voltage swing to override circuit noise. My stuff is pretty
much restricted to below 5V, with 3.3 being the main stay. This means 2.8V
internal as everything is regulated. External power supplies are way too
noisy. In fact, my BG has 20 times less supply current for the same noise
offered by the likes of Linear Tech, Maxim, Analog Devices etc.

All
other defects corrected by throwing transistors at it.

That makes sense. I was quite interested in doing the same nearly 20 years
ago, adding a uC to a VCXO for all those benefits. That's why I collected
a lot of oscillator / crystal literature.

Digital control is a bit tricky, especially for the heated few ppb
oscillators. 1 ppb steps would be way to large, so its usually all smooth
analog

I realized I'd be in the oscillator-making business then though, which
wasn't
what I really wanted to do the rest of my life.

I got into it by default. The only reasonable option near to where I lived,
when I anticipated the current job at the then current employer was not
going to last.

I don't intend to stay in oscillators...

>Small world, isn't it?

Indeed.


Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

 

[John Larkin]

On Mon, 22 Sep 2014 11:14:26 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

On Monday, September 22, 2014 11:20:34 AM UTC-4, John Larkin wrote:

The other interesting part is the ceramic coaxial resonator.

http://t-ceram.com/obr/coaxial_resonators.jpg

These are essentially shorted coaxial lines made with a very hi-K
ceramic dielectric. Qs get into the thousands and TCs are very
low.
They start at about 500 MHz and get really good in the low GHz.

I remember them well. In fact I remember telling you about them and
buying you a handful in S.F.--at Halted, was it?--1998 ;-) (For
possible DDG use.)

We do make a couple of DDGs that use these as burst oscillators. They
are OK for timing relatively short delays, in the hundreds of
microseconds maybe. Longer delays need fancier schemes to keep the
jitter down.

The bad thing about the coax resonators is that their Zo tends to be
low, like 10 ohms maybe.

But at my frequency, a quartz crystal would have higher Q and lower
TC and phase noise.

Especially the low TC part. 1 GHz drifting 2ppm/C could get a little
squirrely.

Not to mention that I can buy a small VCXO
from stock.

Yep.

I like the microwave brick-style SRD->schottky sampling phase
detector--eliminates the need for one digital divider, and the
need to square up the 155.52 MHz. That's slick.

I assume samplers can be low-jitter. They're used in sampling
scopes, after all.

Samplers can have sub-ps jitter, but their equivalent noise figures
are terrible. They also tend to have a lot of time jitter vs
temperature. I think my d-flop bangbang phase detector will have the
best time stability.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

On Monday, September 22, 2014 2:56:05 PM UTC-4, John Larkin wrote:

On Mon, 22 Sep 2014 11:14:26 -0700 (PDT), dagmargoo...@yahoo.com wrote:

I like the microwave brick-style SRD->schottky sampling phase
detector--eliminates the need for one digital divider, and the
need to square up the 155.52 MHz. That's slick.

I assume samplers can be low-jitter. They're used in sampling
scopes, after all.

Samplers can have sub-ps jitter, but their equivalent noise figures
are terrible. They also tend to have a lot of time jitter vs
temperature. I think my d-flop bangbang phase detector will have the
best time stability.

Yeah, that has the advantage that you can sync it with an ECL D-flop
and take out virtually any arbitrary drift, delay, or wiggle.

Sounds good.

I was trying to avoid the comparator noise from squaring up the
155.52MHz, but there doesn't seem to be any easy way.

It would save a lot in the signal path if you could phase compare
sine waves, but with all these non-common factors in the frequencies
the filtering's impossible.

So as Caesar the famous lunch salad inventor always said, divide,
and conquer.

Cheers,
James

 

[rickman]

On 9/21/2014 6:10 PM, John Larkin wrote:

On Sun, 21 Sep 2014 16:57:51 -0500, ChesterW <iamsnoozin@yahoo.com
wrote:

A test that calculates the information content of a specific feedback
signal should come a lot closer to a necessary and sufficient condition.

Calculating and measuring information is just another tool. Eschewing it
is a bit like never learning about Fourier transforms or relying on
intuition instead of Boolean algebra when designing combinatorial logic.

Funny, but I never use Boolean logic or Karnaugh maps or any of those
classic things. I just look at things and draw logic. Given that FPGAs
are LUT based, and compilers do logic reduction for you (whether you
want them to or not), that old stuff hardly matters any more.

But logic is similar to what you do in that if you have a good innate
sense of what is happening it helps you to see the shortcuts.

Even though the tools may do logic minimization, etc., there are still
plenty of ways to optimize the logic at a high level without getting
into Karnaugh maps and such. In essence you need to understand what is
important and what is not. Just banging code and letting the tools work
it out doesn't get you a good design any more than letting a compiler
worry about your C code or letting a spice simulation tell you your
circuit values. You have to know how to use the tools well to get good
results.

--

Rick

 

[Bill Sloman]

On Tuesday, 23 September 2014 09:37:25 UTC+10, dagmarg...@yahoo.com wrote:

On Monday, September 22, 2014 2:56:05 PM UTC-4, John Larkin wrote:
On Mon, 22 Sep 2014 11:14:26 -0700 (PDT), dagmargoo...@yahoo.com wrote:

I like the microwave brick-style SRD->schottky sampling phase
detector--eliminates the need for one digital divider, and the
need to square up the 155.52 MHz. That's slick.

I assume samplers can be low-jitter. They're used in sampling
scopes, after all.

Samplers can have sub-ps jitter, but their equivalent noise figures
are terrible. They also tend to have a lot of time jitter vs
temperature. I think my d-flop bangbang phase detector will have the
best time stability.

The D-type bistable phase detector is a sampling detector. The signal at the D-input only influences the output at the active edge of the clock waveform.

Yeah, that has the advantage that you can sync it with an ECL D-flop
and take out virtually any arbitrary drift, delay, or wiggle.

Sounds good.

If you don't think about what's going on.

I was trying to avoid the comparator noise from squaring up the
155.52MHz, but there doesn't seem to be any easy way.

Any product detector will let you get away with comparing two sine waves. An AD834 might be one example.

It would save a lot in the signal path if you could phase compare
sine waves, but with all these non-common factors in the frequencies
the filtering's impossible.

Use a DDS to get a 10MHz sine wave out of the 155.52MHz oscillator - low-pass filter the 10MHz to get reduce of the 155.52MHz step artifacts. I suspect that a two pole filter with a bit of ringing would distort the exponential segments between steps into something close enough to a sine wave for most purposes.

Detect phase with a reasonably linear product detector, so that the residual - systematic - spurs can average out over the 12.5usec repeat cycle of the 10MHz/155.52MHz mix. John wants a roughly 500Hz of bandwidth in his PLL, so there's plenty of room for a bunch of poles of low-pass filtering of the phase detector output.

So as Caesar the famous lunch salad inventor always said, divide,
and conquer.

And get assassinated on the Ides of March?

--
Bill Sloman, Sydney

 

On Monday, September 22, 2014 8:03:55 PM UTC-4, Bill Sloman wrote:

On Tuesday, 23 September 2014 09:37:25 UTC+10, dagmarg...@yahoo.com wrote:
On Monday, September 22, 2014 2:56:05 PM UTC-4, John Larkin wrote:
On Mon, 22 Sep 2014 11:14:26 -0700 (PDT), dagmargoo...@yahoo.com wrote:

I like the microwave brick-style SRD->schottky sampling phase
detector--eliminates the need for one digital divider, and the
need to square up the 155.52 MHz. That's slick.

I assume samplers can be low-jitter. They're used in sampling
scopes, after all.

Samplers can have sub-ps jitter, but their equivalent noise figures
are terrible. They also tend to have a lot of time jitter vs
temperature. I think my d-flop bangbang phase detector will have the
best time stability.

The D-type bistable phase detector is a sampling detector. The signal at the D-input only influences the output at the active edge of the clock waveform.

The topic instant was schottky analog samplers.

Yeah, that has the advantage that you can sync it with an ECL D-flop
and take out virtually any arbitrary drift, delay, or wiggle.

Sounds good.

If you don't think about what's going on.


I was trying to avoid the comparator noise from squaring up the
155.52MHz, but there doesn't seem to be any easy way.

Any product detector will let you get away with comparing two sine waves. An AD834 might be one example.

If John has to divide down f(ref) and f(out), neither are sine waves.
One appeal of a sampler was that it eliminates the f(out) comparator
and divider.

If you mix 10Mhz and 155.52MHz sines directly, the result is an unfilterable
mess.

It would save a lot in the signal path if you could phase compare
sine waves, but with all these non-common factors in the frequencies
the filtering's impossible.

Use a DDS to get a 10MHz sine wave out of the 155.52MHz oscillator - low-pass filter the 10MHz to get reduce of the 155.52MHz step artifacts. I suspect that a two pole filter with a bit of ringing would distort the exponential segments between steps into something close enough to a sine wave for most purposes.



Detect phase with a reasonably linear product detector, so that the residual - systematic - spurs can average out over the 12.5usec repeat c...

The DDS in the signal path adds a horrendous, variable delay, loads of
transistors in the signal path, and no control over how clean the
supplies and signals are. I don't see how the DDS' wandering analog
output delay can be re-sync'd to the reference clock, something the
bang-bang can do with a single flop.

A DDS outputs a stepped pseudo-sine with a zero-crossing that will
periodically coincide with flat spots on the DDS'output waveform,
which modulates the zero-cross time (unless specific steps <ducks>
are taken to prevent it). Filtering the DDS output to remove this
problem adds more critical circuitry, delay and drift.

Analog multiplier phase detectors are duty-cycle, d.c. offset, and
amplitude sensitive, all of which seem like bad ideas when John needs
rock-solid phase stability, AIUI.

Adding a DDS comes with a lot of deficits.

Cheers,
James Arthur

 

[Bill Sloman]

On Tuesday, 23 September 2014 10:48:11 UTC+10, dagmarg...@yahoo.com wrote:

On Monday, September 22, 2014 8:03:55 PM UTC-4, Bill Sloman wrote:
On Tuesday, 23 September 2014 09:37:25 UTC+10, dagmarg...@yahoo.com wrote:
On Monday, September 22, 2014 2:56:05 PM UTC-4, John Larkin wrote:
On Mon, 22 Sep 2014 11:14:26 -0700 (PDT), dagmargoo...@yahoo.com wrote:

I like the microwave brick-style SRD->schottky sampling phase
detector--eliminates the need for one digital divider, and the
need to square up the 155.52 MHz. That's slick.

I assume samplers can be low-jitter. They're used in sampling
scopes, after all.

Samplers can have sub-ps jitter, but their equivalent noise figures
are terrible. They also tend to have a lot of time jitter vs
temperature. I think my d-flop bangbang phase detector will have the
best time stability.

The D-type bistable phase detector is a sampling detector. The signal at the D-input only influences the output at the active edge of the clock waveform.

The topic instant was schottky analog samplers.

But the defects of the sampling detector aren't specific to the technology used to realise it.

Yeah, that has the advantage that you can sync it with an ECL D-flop
and take out virtually any arbitrary drift, delay, or wiggle.

Sounds good

If you don't think about what's going on.

I was trying to avoid the comparator noise from squaring up the
155.52MHz, but there doesn't seem to be any easy way.

Any product detector will let you get away with comparing two sine waves. An AD834 might be one example.

If John has to divide down f(ref) and f(out), neither are sine waves.

But the output from a DDS is a good approximation to a sine wave, and the spurs injected by the DDS process are deterministic, small and repeat at 80kHz.

One appeal of a sampler was that it eliminates the f(out) comparator
and divider.

If you mix 10MHz and 155.52MHz sines directly, the result is an unfilterable
mess.

What's that got to do with anything? If you use a DDS clocked by the 155.52MHz source to create a good approximation to a sine wave, and compare it with yur reference 10MHz with a product-type phase detector - the AD834 would be an overkill, but it would work - the output contains the usual 20MHz content, which you can filter - as has been done in PLL for as long as they have existed.

It's certainly not an unfilterable mess, and if you think that you aren't thinking straight. Drink some coffee and re-energise your brain.

It would save a lot in the signal path if you could phase compare
sine waves, but with all these non-common factors in the frequencies
the filtering's impossible.

Use a DDS to get a 10MHz sine wave out of the 155.52MHz oscillator - low-pass filter the 10MHz to get reduce of the 155.52MHz step artifacts. I suspect that a two pole filter with a bit of ringing would distort the exponential segments between steps into something close enough to a sine wave for most purposes.

Detect phase with a reasonably linear product detector, so that the residual - systematic - spurs can average out over the 12.5usec repeat cycle of the 10MHz/155.52MHz mix. John wants a roughly 500Hz of bandwidth in his PLL, so there's plenty of room for a bunch of poles of low-pass filtering of the phase detector output.

The DDS in the signal path adds a horrendous, variable delay, loads of
transistors in the signal path, and no control over how clean the
supplies and signals are. I don't see how the DDS' wandering analog
output delay can be re-sync'd to the reference clock, something the
bang-bang can do with a single flop.

The DDS would use the 155.52MHz source to clock the DAC producing the stair-case approximation to the desired 10MHz waveform.

That's not any kind of "horrendous variable delay" and there are very few transistors in that signal path. And you've got total control over rails feeding the DDS chip. The DDS doesn't have any kind of "wandering analog output delay". You are as bad as John Larkin, who claimed that the DDS output "jittered" when it has - at worst - perfectly systematic, and small, deviations from the desired sine wave.

A DDS outputs a stepped pseudo-sine with a zero-crossing that will
periodically coincide with flat spots on the DDS'output waveform,
which modulates the zero-cross time (unless specific steps <ducks
are taken to prevent it). Filtering the DDS output to remove this
problem adds more critical circuitry, delay and drift.

My guess is that the - obligatory - low pass filter on the output of the DDS should be a slightly peaky two-pole with a 3dB point at about 78MHz. It necessarily adds delay, but the drift on the 13nsec of delay involved can be kept within bounds by an intelligent choice of components.

Analog multiplier phase detectors are duty-cycle, d.c. offset, and
amplitude sensitive, all of which seem like bad ideas when John needs
rock-solid phase stability, AIUI.

They do need careful analog design, which John does claim that he can deliver.
They do have the overwhelming advantage over the bang-bang phase detector that John seems to fancy - because he got one to work, once when he could sample at 77Mz - in that they average over the complete cycle rather than looking within a very narrow window, and throwing away loads of useful information that shows up outside that window.

>Adding a DDS comes with a lot of deficits.

But nowhere near as many - or as severe - deficits as you seem to imagine. I won't say "as you seem to think" because you really don't seem to have thought all that hard about what's involved.

Design is all about compromises, and they rarely work out to be identical from one design to the next.

--
Bill Sloman, Sydney

 

Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

Den fredag den 19. september 2014 16.11.10 UTC+2 skrev dagmarg...@yahoo.com:
On Friday, September 12, 2014 9:18:41 PM UTC-4, mrob...@att.net wrote:

Sort of related: European starlings (Sturnus vulgaris) develop about
10 to 15 W of metabolic power, and deliver about 1 to 2.5 W at the
wings.

Pretty neat that a 100g critter makes 15W.

I liked the idea that if you have the amount of power that comes out of
a standard USB port, you can fly.

Also neat that going from 23Km/hr to 52Km/hr only increases draw from
10.4 to 14.9W.

It's almost like they're really aerodynamic or something.

As a special added bonus, if you have two of them of the correct
configurations, they can *manufacture copies of themselves* at the rate
of three or four a year.

the Tour de France riders put around 6W/kg in the pedals all day, in
the sprint the best can do around 22W/kg for a few seconds

She don't lie, she don't lie, she don't lie...

Matt Roberds

 

[josephkk]

On Sat, 20 Sep 2014 12:36:31 GMT, Jan Panteltje <panteltje@yahoo.com>
wrote:

On a sunny day (Sat, 20 Sep 2014 20:42:28 +1000) it happened Bill Sloman
bill.sloman@ieee.org> wrote in <lvjlmr$1tj$1@dont-email.me>:

On 20/09/2014 7:58 PM, Jan Panteltje wrote:
On a sunny day (Fri, 19 Sep 2014 21:58:16 -0700 (PDT)) it happened
dagmargoodboat@yahoo.com wrote in
6eb4d413-9b79-48f5-84f3-d73d93bbc9e8@googlegroups.com>:

snip

And those fusion lasers, chances are same as winning the euromillions.

Never the main reason for the set-up - it's actual job, as a opposed to
the PR window-dressing, has always been nuclear weapons testing and
maintenance.

Now I am curious, how do you test nukes by imploding a pellet of ??
with lasers?
US has plenty nukes, some need fresh plutonium I've read..
Maybe some more recent electronics, would make me feel safer.

Well modern electronix is vastly more sensitive to radiation and Single
Event Upsets. Not a smart idea in a device full of radioactive materials.

?-/

 

On Monday, September 22, 2014 11:46:54 AM UTC-4, Jan Panteltje wrote:

dagmargoo...@yahoo.com wrote:


I would've thought the "Ea" parts are the mixers, diode quads. The filters
are nicely realized on the PCB, and I'd have guessed the right-top chip
you mentioned is an output amplifier.

No, look at this:

http://www.juras-projects.org/files/lumax_lx-lst40.png

Ahh, multiple input amps--a diversity receiver, or more likely two feedhorns
for two bands. I should have thought of that.

(Looking back at your board photo it's the latter, indicated by the different
geometries of the two input amps' structures.)

Two DROs, gated for band-switching as suspected.

That's a pretty impressive mixer, running at Ku-band.

I think that is pretty much the circuit diagram of this one too.

http://www.juras-projects.org/eng/hardware.php

That website gives nice info, bottom page.

Nice stuff. The DROs use BJTs--pretty neat that that's possible nowadays.

Cheers,
James Arthur

 

On Monday, September 22, 2014 12:42:18 PM UTC-4, Jan Panteltje wrote:

On a sunny day dagmargoo...@yahoo.com wrote:

I would've thought the "Ea" parts are the mixers, diode quads. The filters
are nicely realized on the PCB, and I'd have guessed the right-top chip
you mentioned is an output amplifier.


Well, maybe you are right,
could be active FET mixer...
then I will have to connect the coax a bit differently

Normally I'd expect the hair-pin bandpass to be the IF filter. I can't
tell from the dimensions from here, but it looks like it's at r.f. rather
than i.f. Weird.

ISTM the last FET to the right is the mixer, fed hot from the DROs, which
then goes through a wimpy IF filter before heading to the output amp.

I don't see any path from the DROs to the output chip, so either I've missed
it or it's likely not a mixer, just an amp.

As noted before, a Ku-band mixer chip would be something *mighty* special.

Cheers,
James Arthur