EDK : FSL macros defined by Xilinx are wrong

Jonathan Bromley wrote:

Our VHDL and Verilog courses teach language essentials
and coding style, and discuss some generally-applicable
design techniques such as FSMs, but to keep them generic
(and a reasonable length!) we don't discuss how to design
any specific kind of hardware. But we have often been
asked to create a course covering "the art of good RTL
design" or somesuch. What these customers seem
to want is something like "thirty years of design
experience in a three-day class".
Click to expand...
I hear it stated like this:
"I'd like to try that technique, but
I'm not sure it will work so I'm sticking
with the way I did it last time."

And that's what many opencores designs
look like.

It's never been
feasible for us to do that, because the exact content
would be so specific to the particular needs of any
one customer. But an open, peer-moderated,
frequently-updated repository sounds like a good
idea to me. I don't mean a library of complete
ready-cooked designs like opencores.org; rather,
I'm thinking of a collection of "design patterns"
and shared experience.
Click to expand...
I imagine a site like opencores
with working synthesis and verification code
under version control. The difference would be
that all of the designs would be peer-reviewed
and make full use of advanced synthesis techniques.
The examples would be easy to read, understand and modify.
They would be simple, but non-trivial.
Working code would provide some confidence for the skeptical.

The same code base would provide the "design patterns"
for tutorial authors to reference and write about.
Designs might be combined structurally or procedurally.
They might be used as benchmarks for synthesis
or for evaluating the latest assertion based testing.

Any takers?
Click to expand...
I would be happy to write and review some code examples,
but we would need to find an interested retired person
to be the web master and chief editor.

-- Mike Treseler
 
larwe wrote:
Antti Lukats wrote:


Goddamn, I hate Xilinx's software. Nowhere - NOWHERE in the
documentation with the ML403 does it state that the license is limited
to one year.

Is the ISE installation similarly limited?


ISE is also sold as 'time based license' yes.


This is rampant bullshit, and it is PRECISELY why proprietary
development tools are so dangerous. It is not disclosed anywhere on the
purchasing/specifications page for the ML403 EDK bundle that all this
software is time-limited crippleware. Likewise, it is not disclosed
anywhere in the software or any installed documentation. It is ONLY
mentioned on the web site in an unrelated and semi-buried page.

In this case it isn't much money - $500 per year isn't a whole lot, and
it's tax deductible. But how much is EDK? And where do they disclose
this information about the price, or is it a case of "if you have to
ask, you can't afford it"?

I'm emailing Altera and Xilinx simultaneously; whichever one offers the
better deal for someone who's going to write about their products and
never field a design, that's the one that goes into my next book.
Fortunately I wasn't working on this section of it yet!
Click to expand...
I've crossposted this, so someone in Xilinx can comment on the
Details.

The link Antti gave does not mention webpack, or Microblaze,
and I believe the webpack does not expire ?

I would expect MB to be a one-time license,
"solely for use in developing designs for Xilinx Programmable devices."

You should also note that Xilinx's have 'separated from the pack' in
that their latest webpack (free) does NOT support any of their newest V5
devices, as a matter of policy.

-jg
 
Hi there,

I am doing my first FPGA/VHDL design. Previously I did CPLD designs
utilizing Altera's AHDL.
I coded the VHDL source files and simulated it successfully with
Modelsim. Then I made the I/O pin assignments and made the .bit
file and loaded it to the FPGA. To my disappointment only some of
the signals are correct; the functionality of the system does not
work.
I am using ispLEVER and a Lattice LFEC33 FPGA.
There is a "Post Place and Route Simulation" action available within
ispLEVER (actually it starts Modelsim), but this does not work.
Modelsim always complains "Error loading design".
What possibilities do I have to debug my design?

Thanks a lot,

Johannes
 
Hi Johannes,

did you import the testbench file and associate it to the device in
ispLEVER?
By doing that you can start functional and timing simulation when
marking
the device.

Besides are you using VHDL packages ?

Rgds
André


There is a "Post Place and Route Simulation" action available within
ispLEVER (actually it starts Modelsim), but this does not work.
Modelsim always complains "Error loading design".
What possibilities do I have to debug my design?

Thanks a lot,

Johannes
Click to expand...
 
Johannes Hausensteiner wrote:

I am doing my first FPGA/VHDL design.
I coded the VHDL source files and simulated it successfully with
Modelsim. Then I made the I/O pin assignments and made the .bit
file and loaded it to the FPGA. To my disappointment only some of
the signals are correct; the functionality of the system does not
work.
I am using ispLEVER and a Lattice LFEC33 FPGA.
There is a "Post Place and Route Simulation" action available within
ispLEVER (actually it starts Modelsim), but this does not work.
Modelsim always complains "Error loading design".
Click to expand...
Use modelsim directly from the command line or GUI.

What possibilities do I have to debug my design?
Click to expand...
Common first-time synthesis problems include:
Use of wait statements.
No clock.
No reset.
Inputs not synchronized.
Clock or reset on non-global pin.
Not using standard clocked process template.

If all else fails,
post your code to comp.lang.vhdl
Good luck.

-- Mike Treseler
 
Johannes Hausensteiner wrote:

What possibilities do I have to debug my design?
Click to expand...
Hi Johannes,
besides comp.arch.fpga and other usenet groups, you could post your
questions on Lattice's support forum:

http://www.latticesemi.com/support/forums.cfm

hope this helps.
regards,
bart borosky, lattice
 
Hi Bart,

Thanks for the link.

bart wrote:
Johannes Hausensteiner wrote:

What possibilities do I have to debug my design?

Hi Johannes,
besides comp.arch.fpga and other usenet groups, you could post your
questions on Lattice's support forum:

http://www.latticesemi.com/support/forums.cfm

hope this helps.
regards,
bart borosky, lattice
Click to expand...
 
Hi André,

Thanks for your answer; yes I added my testbench to the ispLEVER
project and assosiated it to the FPGA chip. I get three entries in
right pane of the ispLEVER ProjectNavigator:
- VHDL Functional Simulation
- VHDL Post-Route Functional Simulation
- VHDL Post-Route Timing Simulation
When I double-click on any of them Modelsim is started and it compiles
and tries to load the design. In all three of them there are following
error messages in Modelsim:
-- snip ---
# ** Error: (vsim-3170) Could not find 'work.StimModule_Unknown'.
# Error loading design
# Error: Error loading design
# Pausing macro execution
-- snip ---
The name "work.StimModule_Unknown" is used for each and every design
I tried up to now.
When I replace this in the (by ispLEVER generated) do-files
(test_bench.fdo, test_bench.xdo, test_bench.tdo) with the name of the
testbench then the "Functional Simulation" will work.
The "Post-Route Functional Simulation" and the "Post-Route Timing
Simulation" will still refuse to load in Modelsim with the following
error:
-- snip ---
# Loading work.tb_counter(test_counter)
# ** Error: (vsim-13) Recompile work.counter(everything) because
work.counter has changed.
# Error loading design
# Error: Error loading design
-- snip ---
This does not change when I actually recompile "counter",
"work.counter", or the whole design.

While once more double-checking I found out the following:
for the "Post-Route ... Simulation" ispLEVER decompiles what it has
routed to a VHDL file named "design.vho". This uses the architecture
name "Structure". For the testbench to be loaded correctly within
Modelsim is has (of course) to be of architecture "Structure", too
(which was in the case in my design). - OK, this one is clear; I can
live with the "work.StimModule_Unknown" thing.


So thank you for your replies!

Johannes



ALuPin@web.de wrote:
Hi Johannes,

did you import the testbench file and associate it to the device in
ispLEVER?
By doing that you can start functional and timing simulation when
marking
the device.

Besides are you using VHDL packages ?

Rgds
André


There is a "Post Place and Route Simulation" action available within
ispLEVER (actually it starts Modelsim), but this does not work.
Modelsim always complains "Error loading design".
What possibilities do I have to debug my design?

Thanks a lot,

Johannes
Click to expand...
 
I'm starting a new thread on this since Google locked me out from
replying.

Regarding conflicts using CVS, use SVN and tag certain files as
requiring checkout. (I forget the procedure but it uses the property
name you attach. You need to run a script on a regular basis that does
this because it's done on a pre file basis.

Regarding which source control system. Any one should work (but I hate
CVS). SVN is pretty nice.

Regarding which files should be archived (as source). I would not sweat
it too much (e.g. files that get copied from library etc.) It's not the
end of the world if they get versioned.

Ragarding binary: Just check them in as binary. SVN handles binary much
better than svn and the database is amazingly small.

I'm still working myself on what makes sense for users. I have the CAD
folks that use solid works working very nicely on SVN. If also saved
their butts in short order.

I'm trying to understand where FPGA pin mappings are stored as the
users claim they are in the db directory and other folks on the
previous thread said never to version the db directory.
 
mswlogo wrote:
I'm trying to understand where FPGA pin mappings are stored as the
users claim they are in the db directory and other folks on the
previous thread said never to version the db directory.
Click to expand...
I put pin mappings in the RTL source file. You can assign I/O type
there as well.

I like to keep all technology/implimentation dependant stuff in one
spot. The very top level usually works well.
 
The pin mappings are stored in the *.qsf file. Each revision for the
project has its own qsf file. You should not be storing anything from
the db directory in the source code control system.

Hope this helps,
Subroto Datta
Altera Corp.

mswlogo wrote:
I'm starting a new thread on this since Google locked me out from
replying.

Regarding conflicts using CVS, use SVN and tag certain files as
requiring checkout. (I forget the procedure but it uses the property
name you attach. You need to run a script on a regular basis that does
this because it's done on a pre file basis.

Regarding which source control system. Any one should work (but I hate
CVS). SVN is pretty nice.

Regarding which files should be archived (as source). I would not sweat
it too much (e.g. files that get copied from library etc.) It's not the
end of the world if they get versioned.

Ragarding binary: Just check them in as binary. SVN handles binary much
better than svn and the database is amazingly small.

I'm still working myself on what makes sense for users. I have the CAD
folks that use solid works working very nicely on SVN. If also saved
their butts in short order.

I'm trying to understand where FPGA pin mappings are stored as the
users claim they are in the db directory and other folks on the
previous thread said never to version the db directory.
Click to expand...
 
mswlogo wrote:

I'm trying to understand where FPGA pin mappings are stored as the
users claim they are in the db directory and other folks on the
previous thread said never to version the db directory.
Click to expand...
The *nice* thing about Quartus is that you only need to store *2* text
files for the project, aside from your source - namely the .QPF and .QSF
files.

Everything else is generated output from Quartus!

Works really well with SVN.

Nice
Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
 
I'm trying to understand where FPGA pin mappings are stored as the
users claim they are in the db directory and other folks on the
previous thread said never to version the db directory.

The *nice* thing about Quartus is that you only need to store *2* text
files for the project, aside from your source - namely the .QPF and .QSF
files.
Click to expand...
If you have more than one device in the JTAG chain also
store the .cdf. And for the SOPC builder all information
is in the .ptf. So you end up with a maximum of 4 files
and they are all plain text. Very convenient.

Martin
 
Mark McDougall <markm@vl.com.au> writes:

The *nice* thing about Quartus is that you only need to store *2*
text files for the project, aside from your source - namely the .QPF
and .QSF files.
Click to expand...
I only store ONE file for Quartus, a tcl script to compile the design.
It includes all the pin assignments, global assignments to generate
SVF files etc.

A typical build from a fresh checkout will look like:

cvs co designname
cd designname/impl/ep1c6t144c8
quartus_sh -t compile.tcl



Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
 
Martin Schoeberl wrote:

And for the SOPC builder all information
is in the .ptf.
Click to expand...
Ah yes, indeed! However, we'll strategically overlook mentioning NIOS
IDE projects and the !@#*@&^#%$% workspace... ;)

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
 
Petter Gustad wrote:

A typical build from a fresh checkout will look like:
cvs co designname
cd designname/impl/ep1c6t144c8
quartus_sh -t compile.tcl
Click to expand...
Now there's someone who doesn't like documenting build instructions! ;)

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
 
Mark McDougall wrote:
Martin Schoeberl wrote:

And for the SOPC builder all information
is in the .ptf.

Ah yes, indeed! However, we'll strategically overlook mentioning NIOS
IDE projects and the !@#*@&^#%$% workspace... ;)
Click to expand...
Although the Nios IDE is Eclipse under its makeup, and Eclipse supports
Subversion very well via the Subclipse plugin:
http://subclipse.tigris.org - has anyone tried installing this?

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
Click to expand...
 
Mark McDougall <markm@vl.com.au> writes:

Martin Schoeberl wrote:

And for the SOPC builder all information
is in the .ptf.

Ah yes, indeed! However, we'll strategically overlook mentioning NIOS
IDE projects and the !@#*@&^#%$% workspace... ;)
Click to expand...
As for NIOS I've made a makefile to build everything from the ptf
file. In the NIOS case compile.tcl, mysystem.ptf and makefile are the
only files checked in besides hdl and c source files.

The makefile is probably not portable across different versions of the
sopc builder. There are lots of variables which have to be set
(SOPC_PERL, sopc_kit_nios, etc.)


Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
 
Mark McDougall kirjoitti:

Martin Schoeberl wrote:

And for the SOPC builder all information
is in the .ptf.

Ah yes, indeed! However, we'll strategically overlook mentioning NIOS
IDE projects and the !@#*@&^#%$% workspace... ;)

Regards,

--
Mark McDougall, Engineer
Click to expand...
I save these project files into repository.

..cdtbuild
..cdtproject
..project
application.stf

My problem is related to Linked Resources, since I use variables to
define location of some common files. And value of Linked Resources is
hidden in user !@#*@&^#%$% workspace.

Antti
 
Petter Gustad wrote:
I only store ONE file for Quartus, a tcl script to compile the design.
It includes all the pin assignments, global assignments to generate
SVF files etc.

A typical build from a fresh checkout will look like:

cvs co designname
cd designname/impl/ep1c6t144c8
quartus_sh -t compile.tcl
Click to expand...
If only Xilinx made life that simple :(

I'm not what you'd call a fan of the .ise file.. Project Navigator regularly
corrupts it (usually after it's destroyed the backup copy), and the tools
that interface to it are.. weak. pjcli can't even recreate a full project
because it doesn't understand how to add a constraint file to it!

And let's not get into the tool's obsession with absolute pathnames which
make having 'beta' versions of your design very frustrating :(

(but on the plus side I have a makefile which replicates the build
functionality I need.. still working on generating simulation)

--
Daniel O'Connor software and network engineer
for Genesis Software - http://www.gsoft.com.au
"The nice thing about standards is that there
are so many of them to choose from."
-- Andrew Tanenbaum
GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C
 
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