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EDK : FSL macros defined by Xilinx are wrong

T

Theo

Guest
Rick C <gnuarm.deletethisbit@gmail.com> wrote:
> I guess once your design becomes complex enough it isn't so practical to debug it in the HDL simulator. Eh?

We have boxes of 16 and a rack of 80 FPGAs, and this is used for data
onload/offload not debugging. So the simulator won't do ;-P

Theo
 
R

Rick C

Guest
On Friday, April 17, 2020 at 4:19:49 PM UTC-4, Theo wrote:
Rick C <gnuarm.deletethisbit@gmail.com> wrote:
I guess once your design becomes complex enough it isn't so practical to debug it in the HDL simulator. Eh?

We have boxes of 16 and a rack of 80 FPGAs, and this is used for data
onload/offload not debugging. So the simulator won't do ;-P

Theo
Have you thought of putting it all into one really big FPGA? 8-o

--

Rick C.

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