EDK : FSL macros defined by Xilinx are wrong

PeteS wrote:
Bob Ferapples wrote:
To save time and bandwidth, I have boiled down the vast majority of
postings to this newsgroup into a quick and dirty little format that
can speed things up. Please follow this format from now on in this
group.

--------------------------------------------

Please kind (insert platitudes here, or addreess titles i.e. Sirs or
Madames),

I am a new (insert job function or social status here, i.e. Student,
Engineer,
Electrician, Homeowner etc.)

optional> from (insert non-english speaking country)

and I have this (insert task here, i.e. homework assignment, personal
project, project
assigned to me, problem with my appliance etc.).

I know (insert qualifications here, i.e. next to nothing, very little,
a
little, enough to be dangerous etc.) about electricity,

but was hoping that you all could help me to (restate task here, but
without saying what you really mean, i.e. do my homework for me, get me
out of a jam, help me to avoid paying a professional to do it
correctly, get me through this day without having to think, avoid
electrocuting myself or my loved ones etc).

I hope to hear from you soon.

Nooby Nooberson

---------------------------------

Snort
x-posted to s.e.d, s.e.b., comp.arch.fpga, comp.arch.embedded,
comp.arch.dsp
Click to expand...
I'm new to this group and been reading over the different articles, and
a funny thing is I haven't seen any that was of the nature you have
described.

Maybe others have a similar attitude and that would explain why I have
received no replies to a simple question that the Xilinx site does not
answer.

Somehow I feel really welcomed.


--

Cecil
KD5NWA
www.qrpradio.com www.hpsdr.com

"Sacred Cows make the best Hamburger!" Don Seglio Batuna
 
On Sun, 03 Sep 2006 17:00:20 -0500, Don Seglio
<cbayona@cox.net> wrote:

I'm new to this group and been reading over the different articles, and
a funny thing is I haven't seen any that was of the nature you have
described.
Click to expand...
Try watching a little longer - there are enough...

Maybe others have a similar attitude and that would explain why I have
received no replies to a simple question that the Xilinx site does not
answer.
Click to expand...
Errrm, maybe not. Traffic on comp.arch.fpga is pretty light
at weekends - many of the most active contributors are
professionals in the field and regard monitoring the NG
as a useful part of their work,
whether for self-publicity, keeping up-to-date, or just generally
being helpful. Such folk are more likely to respond to your
Sunday-morning post some time on Monday. And I'm not
sure that your question about Matlab version compatibility
really rates as "simple" - it sounds hard to me, but I'll
wager there are plenty of people here who can tell you.

For the record, my perception is that comp.arch.fpga is
pretty open to anyone who's prepared to make the effort
to articulate a pertinent question. A nice contrast with
some other groups I've looked at!
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Jonathan Bromley wrote:
On Sun, 03 Sep 2006 17:00:20 -0500, Don Seglio
cbayona@cox.net> wrote:

I'm new to this group and been reading over the different articles, and
a funny thing is I haven't seen any that was of the nature you have
described.

Try watching a little longer - there are enough...

Maybe others have a similar attitude and that would explain why I have
received no replies to a simple question that the Xilinx site does not
answer.

Errrm, maybe not. Traffic on comp.arch.fpga is pretty light
at weekends - many of the most active contributors are
professionals in the field and regard monitoring the NG
as a useful part of their work,
whether for self-publicity, keeping up-to-date, or just generally
being helpful. Such folk are more likely to respond to your
Sunday-morning post some time on Monday. And I'm not
sure that your question about Matlab version compatibility
really rates as "simple" - it sounds hard to me, but I'll
wager there are plenty of people here who can tell you.

For the record, my perception is that comp.arch.fpga is
pretty open to anyone who's prepared to make the effort
to articulate a pertinent question. A nice contrast with
some other groups I've looked at!
Click to expand...
It's simple in the sense that one has tried it and it works or it
doesn't. Guessing won't help me. That is also why I asked about what
software is shipping with the new kit's, if it a recent enough version
it might work with the MatLab I have.

Once I break the wrapper on the package, I'm stuck with it so it would
be nice to save a ton of money to know if it has been tried and if it
worked before I end up wasting money I can't afford to waste.

Right now I tried to get it exchanged for R14 but my vendor says sorry
all they can do is refund my money if it has not been opened, they did
me a favor by sending me the new version since it cost a lot more than
what I paid. I have about a week to figure out what I need to do.

--

Cecil
KD5NWA
www.qrpradio.com www.hpsdr.com

"Sacred Cows make the best Hamburger!" Don Seglio Batuna
 
In message <09ROg.1689$6S3.769@newssvr25.news.prodigy.net>, dated Sat,
16 Sep 2006, joseph2k <quiettechblue@yahoo.com> writes

I disagree, the appearance upon entering the interview stated clearly
that the candidate was not in the least interested in working for a
suit bound, mature hierarchy and had reasonable desire to minimize the
amount of time lost to both parties. I am wildly extrapolating that
said candidate would not have presented the same way at your company.
Click to expand...
I don't employ anyone, but a friend of mine recruited a guy, against his
initial judgement, who had, and has, multicoloured hair. He's GOOD, but
I suppose software artists are allowed to be bohemian.
--
OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk
There are benefits from being irrational - just ask the square root of 2.
John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK
 
betterone11@gmail.com wrote:
fpgaman wrote:

"http://www.latticesemi.com/products/intellectualproperty/latticemico32"


The link to the store does not show the board directly. What is the
price?
Is there any low cost evaluation kit alternative and what kind of
debugger will work?
Click to expand...
Looks like the web store is a little slower in the loop...

When you get a direct link like given above, it's normally a good idea
to also find the related press release :
http://www.latticesemi.com/corporate/newscenter/productnews/2006/r060918new32bitembeddedmi.cfm

this mentions the prices of the EvalPCB's & toolchains.

This core complements the Mico8, but is much larger.
What would be nice is an intermediate core: along the lines of
"smallest core that can run HLL" - with 16/18 bit opcodes ?

-jg
 
thanks for the heads up. i've notified the Lattice store. the mico32
development kit should be up on the store later today. rgds, bart,
Lattice

The LatticeMico32 Development Kit is available now and is priced at
$995. The Kit includes both the ispLEVER design tools, regularly priced
at $695, and the development board, which as a stand-alone is priced at
$595.
> Looks like the web store is a little slower in the loop...
 
Jim Granville schrieb:

betterone11@gmail.com wrote:
fpgaman wrote:

"http://www.latticesemi.com/products/intellectualproperty/latticemico32"

finally - a 100% Eclipse-+GNU based SoC system with open-source RTL
Click to expand...
that just works.

Antti
 
Antti wrote:
Jim Granville schrieb:

betterone11@gmail.com wrote:
fpgaman wrote:

"http://www.latticesemi.com/products/intellectualproperty/latticemico32"

finally - a 100% Eclipse-+GNU based SoC system with open-source RTL
that just works.
Click to expand...
Have you used it yet?

Cheers,
Jon
 
Jon Beniston schrieb:

Antti wrote:
Jim Granville schrieb:

betterone11@gmail.com wrote:
fpgaman wrote:

"http://www.latticesemi.com/products/intellectualproperty/latticemico32"

finally - a 100% Eclipse-+GNU based SoC system with open-source RTL
that just works.

Have you used it yet?

Cheers,
Jon
I started the Eclipse based builder,
Click to expand...
made a project
generated the RTL
it was blazing fast and easy.

The IP cores are described in XML, the generated source code is plain
verilog, the compiler toolchain is GCC based, I see no reasons why it
would not work. Its not so hard to make things that work actually.

I havent yet tested it - I do not own any Lattice boards with some
largish FPGA - I was about to buy from private money for my collection
the LatticeSC PCIe single lane eval board - but unfortunatly it is not
yet available for purchases. So I possible have make some wrappers
around Xilinx primitives and check it out on Xilinx FPGA. I opened the
proect in ISE project navigator it all looks eays and understandable.
GSR, ADDSUB and EBR components from Lattice libraries should be
substituted then I guess it would synthesize.

Lattice I would love to test LM32 out on Lattice silicon, but see above
the only board I was/am ready to buy isnt available. After ECP2/M
announce I maybe will wait up ECP2/M PCIe board, or XP2 board.

Antti
 
bart schrieb:

thanks for the heads up. i've notified the Lattice store. the mico32
development kit should be up on the store later today. rgds, bart,
Lattice

The LatticeMico32 Development Kit is available now and is priced at
$995. The Kit includes both the ispLEVER design tools, regularly priced
at $695, and the development board, which as a stand-alone is priced at
$595.
Looks like the web store is a little slower in the loop...
Click to expand...
and..Any plans for uClinux on Mico32?

Antti
 
Antti wrote:
Jim Granville schrieb:

betterone11@gmail.com wrote:
fpgaman wrote:

"http://www.latticesemi.com/products/intellectualproperty/latticemico32"

finally - a 100% Eclipse-+GNU based SoC system with open-source RTL
that just works.
Click to expand...
I was looking at the open source agreement and one paragraph strikes me
as a bit odd.

Appendix C
3. The Provider grants to You a personal, non-exclusive right to use
object code created from the Software or a Derivative Work to
physically implement the design in devices such as a programmable logic
devices or application specific integrated circuits. You may distribute
these devices without accompanying them with a copy of this license or
source code.

It looks like the only rights to the object code created is to use it
in an ASIC or FPGA. Am I just missing the point or does this keep you
from using this for any other purpose? Or would there be no point to
any other purpose? I am not real clear on which software the license
is actually talking about.
 
Antti wrote:
Jim Granville schrieb:

betterone11@gmail.com wrote:
fpgaman wrote:

"http://www.latticesemi.com/products/intellectualproperty/latticemico32"

finally - a 100% Eclipse-+GNU based SoC system with open-source RTL
that just works.

Antti
Click to expand...
I worked before with the NIOSII and a price tag was on the tool. As I
can see it here there is not much difference with the Lattice approach.
Even if someone finds later a 3rd party low cost board and debugger you
still need to buy the ispLEVER software for $595.
Or is there a complete free solution with the LatticeMico32?
...richard
 
betterone11@gmail.com schrieb:

Antti wrote:
Jim Granville schrieb:

betterone11@gmail.com wrote:
fpgaman wrote:

"http://www.latticesemi.com/products/intellectualproperty/latticemico32"

finally - a 100% Eclipse-+GNU based SoC system with open-source RTL
that just works.

Antti

I worked before with the NIOSII and a price tag was on the tool. As I
can see it here there is not much difference with the Lattice approach.
Even if someone finds later a 3rd party low cost board and debugger you
still need to buy the ispLEVER software for $595.
Or is there a complete free solution with the LatticeMico32?
..richard
Click to expand...
http://www.latticesemi.com/products/designsoftware/isplever/ispleverstarter.cfm

look at the list of supported devices, if you use any of them then you
can use the free ispLever starter and do not need to pay a dime.

I havent looked at the debugger yet, but all the rtl for the jtag-debug
is open so it wouldnt be so hard to make a open-source debugger if
there isnt any solution yet.

Antti
 
I worked before with the NIOSII and a price tag was on the tool. As I
can see it here there is not much difference with the Lattice approach.
Even if someone finds later a 3rd party low cost board and debugger you
still need to buy the ispLEVER software for $595.
Or is there a complete free solution with the LatticeMico32?
Click to expand...
Lattice give you the RTL for free and you are allowed to use it on any
device, including non-Lattice devices. i.e. you don't have to buy
ispLEVER or any Lattice FPGAs.

In contrast, the NIOS and MicroBlaze RTL costs tens of thousands of
dollars, and I believe you are only able to use it either in an ASIC or
on their devices.

Cheers,
Jon
 
Jon Beniston schrieb:

I worked before with the NIOSII and a price tag was on the tool. As I
can see it here there is not much difference with the Lattice approach.
Even if someone finds later a 3rd party low cost board and debugger you
still need to buy the ispLEVER software for $595.
Or is there a complete free solution with the LatticeMico32?

Lattice give you the RTL for free and you are allowed to use it on any
device, including non-Lattice devices. i.e. you don't have to buy
ispLEVER or any Lattice FPGAs.

In contrast, the NIOS and MicroBlaze RTL costs tens of thousands of
dollars, and I believe you are only able to use it either in an ASIC or
on their devices.

Cheers,
Jon
Click to expand...
MicroBlaze source code license costs 19 KUSD

the Mico32 RTL is free, but...
it is too advanced verilog for Xilinx XST
so synplify is needed for synthesis :(

Antti
 
MicroBlaze source code license costs 19 KUSD
Click to expand...
Source yes, but not RTL. My guess it's lots of instantiated primitives,
thus not portable. Last time I asked about ASIC licensing, they wanted
150k. Funnily enough, I went elsewhere ;-)

Cheers,
Jon
 
it's my humble understanding that Mico32 is truly RTL, i.e. we do not
use any library elements, so it should be portable. (although, of
course, we'd like for you to buy our chips!)
rgds,
Bart Borosky, Lattice, online marketing manager
Source yes, but not RTL. My guess it's lots of instantiated primitives,
thus not portable.
Click to expand...
 
bart schrieb:

it's my humble understanding that Mico32 is truly RTL, i.e. we do not
use any library elements, so it should be portable. (although, of
course, we'd like for you to buy our chips!)
rgds,
Bart Borosky, Lattice, online marketing manager

Source yes, but not RTL. My guess it's lots of instantiated primitives,
thus not portable.
Click to expand...
Yes it is.

but it uses verilog at such advanced level that is not supported
by Xilinx XST synthesis, e.g. it is only useable with Synplify
as synthesis tool

Antti
 
bart schrieb:

it's my humble understanding that Mico32 is truly RTL, i.e. we do not
use any library elements, so it should be portable. (although, of
course, we'd like for you to buy our chips!)
rgds,
Bart Borosky, Lattice, online marketing manager

Source yes, but not RTL. My guess it's lots of instantiated primitives,
thus not portable.
Click to expand...
Yes it is.

but it uses verilog at such advanced level that is not supported
by Xilinx XST synthesis, e.g. it is only useable with Synplify
as synthesis tool

Antti
 
but it uses verilog at such advanced level that is not supported
by Xilinx XST synthesis, e.g. it is only useable with Synplify
as synthesis tool
Click to expand...
It's about time Xilinx had full Verilog 2001 support really. What year
is it?

Still, on the plus side, if you do use Synplify, at least the rest of
your design might work too ;-)

Cheers,
Jon
 
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