R
rickman
Guest
On Jun 24, 7:44 am, "Fredxx" <fre...@spam.com> wrote:
That would be a truly bizarre circuit design. I don't know how they
actually construct memory to use separate clocks, but I expect it uses
an async memory with two independent synchronous interfaces. FPGA
reps have posted here that there is a lot of "magic" in the logic
between the sync interfaces and the async memory inside the block
ram. All of this would be very hard to describe using an HDL. But
driving a signal with 'z' or switching clocks is not the way to go at
all...
Rick
"Jonathan Bromley" <jonathan.brom...@MYCOMPANY.com> wrote in message
news:bn0445lbemmf3qnl87te1hps2l3nc9novv@4ax.com...
On Wed, 24 Jun 2009 11:37:24 +0100, "Fredxx" wrote:
if you used something like;
if we1 = '1' then
mem(to_integer(unsigned(a1))) := wd1;
else
mem(to_integer(unsigned(a1))) := (others => 'Z');
end if;
Would this then give more consistent results where both processes wouldn't
be fighting against each other?
Sadly, no. I see what you're getting at, but I don't think you could
ever get the memory to have the correct contents if both ports are
doing that all the time. Each process may overwrite locations it's
already correctly written, using Zs, for no good reason.
Suppose you could get it right somehow, and arrange that each process
is driving Z to all locations it's never written, but appropriate
values to locations it has written. What then happens if the second
process writes to a location that previously was written by the other?
How can it tell the first process now to put Z on that location?
In truth the "correct" solution would be to write the whole thing
as a single process with two clocks:
process (clock0, clock1)
variable mem: t_mem;
begin
if rising_edge(clock0) then
if we0 = '1' then
mem(a0) := wd0;
end if;
end if;
if rising_edge(clock1) then
if we1 = '1' then
mem(a1) := wd1;
end if;
end if;
...
But I suspect synthesis tools would chuck that overboard
without a second thought.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
I perhaps am making the (erroneous) assumption that two statements will be
or'd together and the Z's will be overdriven by the signals. But as you
say, I would be replacing the RAM locations with Z's or something that the
synthesiser concocts.
To be honest, I think it isn't good practice to have signals driven by 2
clocks, and I'd probably use clock switching primitives instead so the
memory would be written in one process with just one clock.
That would be a truly bizarre circuit design. I don't know how they
actually construct memory to use separate clocks, but I expect it uses
an async memory with two independent synchronous interfaces. FPGA
reps have posted here that there is a lot of "magic" in the logic
between the sync interfaces and the async memory inside the block
ram. All of this would be very hard to describe using an HDL. But
driving a signal with 'z' or switching clocks is not the way to go at
all...
Rick