Clock Edge notation

[Mike Treseler]

John Moore wrote:

Sorry to be a bore, but I'm still having trouble getting the generator
working in an ethernet transmitter.

We only do monitors so I haven't actually done this,
but in theory, the FCS you add to the end of the
packet should be the payload remainder with each
octet bit reversed, then the whole thing inverted.


-- Mike Treseler

 

[Pieter Hulshoff]

Mario Trams wrote:

Troels Smit wrote:
When in a state, why is it not ok to listen for an event of another
signal ??
Let me reverse your question: Assume you have a regular synchronous
state machine and you instantaneously want to change the state when
an event on some signal occured.
How would you create some piece of hardware using D-FlipFlops and
some logic gates that do the job?

I think this is a better question indeed. Please describe what you wish
to create, and I'll see if I can give you some code that'll do it. What
Mario is describing is pretty easy to build in VHDL, so if you can give a
proper description of what you want, I'll see what I can do for you.

Kind regards,

Pieter Hulshoff

 

[Mike Treseler]

Troels Smit wrote:

When in a state, why is it not ok to listen for an event of another signal ??

For simulation, that would work. It's legal VHDL.

For synthesis you should use the synchronous template.
The only event in synthesis is the rising edge of the clock.
Other "events" become synchronous strobes
Clock inputs to the dflops are not used for
any signal other than clk.

_|___|___|__ clk'event
_________________
______________/ my_output
___
_______________/ \__ my_event

-- Mike Treseler

 

[Alan Coppola]

John,
A little late to this discussion, but if you ever have to respin
or handle more complicated conditions, and want a three-prong verification
scheme, check out:

http://www.nwlink.com/~ajjc

alan

....
Thank you for the help Mike. I've now got it working!

John Moore

 

[Troels Smit]

What is the "synchronous template" ??

I would like to make sure that Im doing this the easiest way:

What I need is to interface the DAC AK4520A. It has three control
signals "MCLK", "SCLK" and "LRCK".

These signals are connected to my clk as follows (counter is
incremented on each clk cyclk)

sclk <= counter(2);
mclk <= counter(0);
lr <= counter(8);

Now, on an LR'event I would like to send a serial word on the next 20
sclk'cycles, and then wait for the next lr'event.

How would you write that in VHDL ?
(You have a parallel serial converter with enable at your disposal,
giving data with sclk speed)

Best Regards,
Troels Smit

Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3EF9E410.4050505@flukenetworks.com>...

Troels Smit wrote:


When in a state, why is it not ok to listen for an event of another signal ??

For simulation, that would work. It's legal VHDL.

For synthesis you should use the synchronous template.
The only event in synthesis is the rising edge of the clock.
Other "events" become synchronous strobes
Clock inputs to the dflops are not used for
any signal other than clk.

_|___|___|__ clk'event
_________________
______________/ my_output
___
_______________/ \__ my_event

-- Mike Treseler

 

[Troels Smit]

Hi Troels,
Is there any reason that you can not use a Flop with and an enable
in the idle state to "latch" the value of the signal and then just
compare that to the incoming signal in the wait4lr state and
transition if the values are not the same?

This doesn't comply 100% with the timing diagram, but indeed it works
and I use something like this solution now - until taught better

(Can't wait to see what code the other thread will result in!!)

/Troels

 

[FE]

you can't do it directly.
you can create a conversion function.
for an example, see
http://groups.google.ca/groups?hl=en&lr=&ie=UTF-8&selm=3AHR9.27582%24KR6.364541%40weber.videotron.net

regards
FE

"Subramanian Ramaswamy" <gtg418c@mail.gatech.edu> wrote in message
news:bde37t$t07$1@news-int.gatech.edu...

I have a question -

If I have a 2 D array X( )( ) , both parameters being unconstrained and I
want to specifically access just one index.i.e something like

Y <= X(1)( )

How do I go about this?

To make myself clearer suppose X is a 10 X 10 array of std_logic;

I want to access X(5)(9 downto 0)
But I want to do this for unconstrained arrays.

Thanks in advance for the replies.

 

[John Moore]

We only do monitors so I haven't actually done this,
but in theory, the FCS you add to the end of the
packet should be the payload remainder with each
octet bit reversed, then the whole thing inverted.

Thank you Mike. After reversing the CRC bytes, reversing the bits in each

byte, and inverting the bits (!) I have got the transmitter working as well.
Having a parallel CRC calculation is much nicer than a serial bit by bit
method. I can use a slower clock for a start.

John Moore

 

[ben cohen]

"Jörg Breitenstein" <haag-streit@sunway.ch> wrote in message news:<3ef972aa$0$1053$5402220f@news.sunrise.ch>...

Hi
Does anyone now if there is a good methologie to analyse and design digital
systems. There are plenty of books about VHDL, but that's the language. I'm
looking for somenthing like SA/SD or UML for software Design. But this vor
digital hardware.

Does Ben Cohen's Book cover topics like this?

Vhdl Coding Styles and Methodologies.

???

Thanx

Joerg

No my books do not cover structured ananlysis and structured design
(SA/SD), nor UML. However, an interesting methodology that is gaining
popularity is assertion-based design with PSL. Assertion-based
verification (ABV) with Property Specification Language (PSL) is
changing the traditional design process because that methodology helps
to formally characterize the design intent and expected operations,
guides the verification task, and eases the design of the testbench
because it transfers more of the "verifier" task onto PSL, instead of
a user defined model. My latest book addresses PSL by example.
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn
0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115
------------------------------------------------------------------------------

 

[Mike Treseler]

John Moore wrote:

Thank you Mike. After reversing the CRC bytes, reversing the bits in each
byte, and inverting the bits (!) I have got the transmitter working as well.
Having a parallel CRC calculation is much nicer than a serial bit by bit
method. I can use a slower clock for a start.

You are welcome. Glad it works for you.
Consider posting a snippet of the
generator code to share with the group.

-- Mike Treseler

 

[Mike Treseler]

Troels Smit wrote:

What is the "synchronous template" ??
see:

http://groups.google.com/groups?q=vhdl++synchronous++template+spaghetti

What I need is to interface the DAC AK4520A. It has three control
signals "MCLK", "SCLK" and "LRCK".

These signals are connected to my clk as follows (counter is
incremented on each clk cyclk)

sclk <= counter(2);
mclk <= counter(0);
lr <= counter(8);

Now, on an LR'event I would like to send a serial word on the next 20
sclk'cycles, and then wait for the next lr'event.

How would you write that in VHDL ?
--------------------------------

I would write a process using the synchronous template.
Lets say your fpga clock is 40MHz and your generated
mclk is 10MHz. Now the process can generate clocks
or controls for the other inputs with a 50nS resolution.

A shift register with enable can drive the serial data.

To generate synchronous events, consider
using a procedure call like ck_rising(lr, last_lr, lr_rising);
by first declaring the functions below.

-- Mike Treseler

-------------------------

function now_high (std_arg : std_ulogic) -- input bit
return boolean is begin
if std_arg = '1' then return true;
else return false;
end if;
end function now_high;

procedure ck_rising(watch : in std_ulogic;
last_low : inout boolean;
result : out boolean)
is begin
result := now_high(watch) and last_low;
-- check for active edge based on

-- variable from last time;
last_low := now_low(watch);
-- assign variable for next time

 

[Jeremy Pyle]

As an add-on to this quetsion, are real numbers always synthesizable or only
certain architectures?


"Jeremy Pyle" <jeremyp@rochester.rr.com> wrote in message
news:e%HKa.33938$kQ5.33752@twister.nyroc.rr.com...

Hey all,

I'm trying to find out how I would get a hold of the representation of a
real number. I know it's represented at a sign bit, exponent, mantissa,
but
I'm trying to store this real number in RAM, meaning I have to pass it in
as
a STD_LOGIC_VECTOR, so somehow I need to convert a real to a
STD_LOGIC_VECTOR. Is there any way to do this?

Also, I have to divide the real numbers so I'm trying to figure out the
best
way to do it. Here are my two choices:
1. just use the division operator provided for real numbers
2. use the XiLinx dividor module provided in XiLinxCoreLib.

If anyone could tell me the pros and cons of using one over the other that
would be fantastic.

Thanks all,

Jeremy

 

[Mike Treseler]

John Moore wrote:

The generator code is attached. It's trivially simple.

Good example, thanks.
Getting code working and making it look simple isn't simple.

I hope this may help someone else.

It has.

-- Mike Treseler

 

[Kent]

Kai Harrekilde-Petersen <khp@harrekilde.dk> wrote in message news:<ufzm6vxk2.fsf@harrekilde.dk>...

stehenry@yahoo.com (stephen henry) writes:

3. I have to generate a high speed pipeline, used to append and decode
CRC's, (De)Scramble the datastream, and encode it into 8B10B.
Additionally, i have to insert a number of primitive characters to
control the flow of data across the link. I was told by one of my
lecturers that the 8b10b section should be implemented serially, for
speed, which got me wondering if i should also implement the CRC and
Scrambler serially as well (which i had previously implemented
parallel).

Serially as in 1 bit at a time? - forget it. 8B/10B should be
implemented as a parallel thing, taking 8 bits + control per cycle,
and yielding the corresponding 10bit codegroup. Get the patent (IIRC
$3 from Delphion as a .pdf file) - it is very readable.

As for the CRC, I wouldn't do that serially either. I'd do it 8bit at
a time, unless speed required me to go to bigger widths.

Good luck,


Kai

Actually if you look at a book called "Fibre Channel for SANS" a much
more compact way to do it is 5B/6B and 3B/4B and cascade for the
current running disparity.

If you use a ROM lookup table and treat the input as an address and
the output as the decoded/encoded result, you can implement 8B/10B
with cycle times as fast as the access time of your ROM.

Kent

 

[Chao]

I think, you should use Q-Format to represent the fractional numbers.

 

[Ken Smith]

In article <0VMKa.34026$kQ5.19014@twister.nyroc.rr.com>,
Jeremy Pyle <jeremyp@rochester.rr.com> wrote:

As an add-on to this quetsion, are real numbers always synthesizable or only
certain architectures?

Real ALUs take up a lot of space. If you are trying to do an add in one
stroke, you have to have a normalizing array and an adder. This is a lot
of logic so some tools won't even try unless you are designing for a
really big chip.

--
--
kensmith@rahul.net forging knowledge

 

[Roadie Roger]

"Jörg Breitenstein" <haag-streit@sunway.ch> wrote in message news:<3ef972aa$0$1053$5402220f@news.sunrise.ch>...

Hi
Does anyone now if there is a good methologie to analyse and design digital
systems. There are plenty of books about VHDL, but that's the language. I'm
looking for somenthing like SA/SD or UML for software Design. But this vor
digital hardware.

Does Ben Cohen's Book cover topics like this?

Vhdl Coding Styles and Methodologies.

???

Thanx

Joerg
You've got at least two issues here. Programming and Digital Design.

I'm sure that VHDL programming can benefit from all the software
productivity and correctness type tools. Revision control, formal
specifications, elaborate testing. I only dabble in programming, so
I'm not sure what state of the art is today. Maybe somebody can
comment on the tools used by large multi-engineer ASIC projects.
Paying for large complicated software projects can be very expensive
and can easily go out of control. If I was paying for a large VHDL
project I'd be very concerned about these issues.

Digital logic design isn't as straight forward as it may seem. An
ounce of insight and clever partitioning can be worth a pound of
logic. Propagate/Generate bits on adder slices aren't obvious, but
can substantially reduce logic gates and give excellent speed. I
don't think there is any Holy Grail of logic design that will pop this
out. It was an important problem that lot's of people looked at and
this was a very good solution. I don't even think that optimal state
assignment and output assignment can be guaranteed. VHDL is famous
for blowing up at synthesis and using way more gates than the minimum
because the tools didn't recognize that there is a clever method
available for what you are doing.

Design reviews of Digital Logic or VHDL are incredibly educational.
Getting 8 experienced, intelligent and competitive people in a room
and asking them to criticize something can spin you up the learning
curve in a hurry. It's entertaining too, in a Dr. Laura
reach-down-their-throat-and-rip-out-their-heart sort of way I just
never get tired of that.

I guess I don't have a great solution for you. It's a pretty good
question though.

Roadie Roger
<http://home.earthlink.net/~roadieroger/index.htm>

 

[David Bishop]

The SIMPRIM and UNISIM libraries are easy, there are only a few files.
Just remember to compile the component packages last.

The Xilinx core libraries are something else. There is a compilation
order file inside the IP directory. I have a little script that compiles
these files, if you need it drop me a line.

Thomas wrote:

How do you recompile the libraries for ModelSim 5.7? all the libs I found
at for 5.6

I tried to ask modelsim to rebuild them, but there are lots of errors.
I tried the tcl script on xilinx's ftp, as a result it goes for a while and
then modelsim just crashes and quits...

--
NAME: David W. Bishop INTERNET: dbishop@vhdl.org ( \ )
US MAIL: Hilton NY A Long time ago, \__\/
PHYSICAL: 43:17:17N 77:47:37W 281' In a Galaxy far, far away... | |
For Supernova info: http://www.RochesterAstronomy.org/snimages/ | |
For VHDL/Synthesis info: http://www.vhdl.org/vhdlsynth _/___\_
All standard disclaimers apply. [_______]

 

[Tim Hubberstey]

David Bishop wrote:

The SIMPRIM and UNISIM libraries are easy, there are only a few files.
Just remember to compile the component packages last.

The Xilinx core libraries are something else. There is a compilation
order file inside the IP directory. I have a little script that compiles
these files, if you need it drop me a line.

Thomas wrote:

How do you recompile the libraries for ModelSim 5.7? all the libs I found
at for 5.6

I tried to ask modelsim to rebuild them, but there are lots of errors.
I tried the tcl script on xilinx's ftp, as a result it goes for a while and
then modelsim just crashes and quits...

The 5.x Xilinx tools include a utility called 'compxlib' for doing this.
I don't know if it is available in the WebPak or only in the full ISE
tools.

http://toolbox.xilinx.com/docsan/xilinx5/data/docs/sim/sim0055_10.html
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

[Alex Gibson]

"sunil" <sunilsreenivas2001@yahoo.com> wrote in message
news:d924fa71.0306282123.55cd302c@posting.google.com...

Hi All,
I am newbie to FPGA. Could some one please suggest me a good
book on FPGA that deals with important FPGA concepts like Floor
Planning, Place and Route, Timing Analysis. I would also like to know
where I can get a FPGA tool kit. I have Orcad Aldec simulation
software but don't have any synthesizer software. Do anyone know how
to obtain Xilinx (4.2i)synthesizer? I mean what are some of the
synthesizer softwares and where do I download/get them?
Thanks,
Regards,
Sunil.

look for xilinx webpack (you will have to register first)
http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack

look at the xilinx cpld and fpga application notes and reference designs

cheaper fpga boards
digilentinc www.digilentinc.com
xess www.xess.com

see http://www.optimagic.com/
for more resources, faqs, books, boards etc

Alex