Clock Edge notation

[rickman]

Alan Fitch wrote:

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F2EFF97.9072E30A@yahoo.com...
I added a variable to calculate a time for a wait statement in a
testbench and am not getting this error from ModelSim...
^^^ now??

Yes, now, not "not".

Signal arm_command is read by the VITAL process but is NOT in the
sensitivity list

This is the line of code producing the error...

WaitTime := (ARM_command.RelTime - (now - CurrentTime));

I follow this up with a check for negative values before using in
the
wait. ARM_command is a signal and WaitTime and CurrentTime are
variables. And of course all these objects are of type time. This
same
calculation done directly in the wait statement gives no error.


It sounds like Modelsim is confused. Is it actually an error, or just
a warning? Having a signal read that is not in the sensitivity list
is not an error. Can you disable Modelsim's synthesis checks?

If it's a warning, just ignore it.

If it's an error, it sounds like a bug.

regards

Alan

p.s. I know it's nothing to do with this error, but I'd check for
negative values before assigning, just because I am paranoid (!). In
particular I wonder what happens if you assign a negative time value
to a variable of type time?
e.g.

assert ( (ARM_command.RelTime - (now - CurrentTime)) >= 0 ns )
report "negative time value";

waittime := ...

p.p.s.
Reading the LRM shows I really am being paranoid, as type TIME is
guaranteed to include the range -2**9+1 to 2^9-1, so negative
time values in variables of type TIME are ok.

The possibility of being negative was why I was using a variable instead
of just sticking it in the wait statement. I thought it would be better
to calculate it once and then test it and set to zero if negative. So
now I have to do the calculation twice.

I am getting the same error from a different assignment now. The common
point is that a signal is on the right hand side of the assignment and a
variable is on the left. I am using the variable assignment operator,
":=". This is reported as an error, not a warning.

Last_Bus_Action := Bus_Command.Bus_Action;

In both cases, part of the right hand expression is an element in a
record. The error reports the record "Bus_Command" as missing from the
sensitivity list, not the element! Could the VITAL process have a bug
in regards to dealing with record elements? This doesn't sound likely
to me. But then I don't even know what the VITAL process is.

Maybe I need to contact Mentor about ModelSim.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Alan Fitch]

<snip>

p.p.s.
Reading the LRM shows I really am being paranoid, as type TIME is
guaranteed to include the range -2**9+1 to 2^9-1, so negative
time values in variables of type TIME are ok.

That should have been -2**31+1 to 2**31-1, sorry.

The possibility of being negative was why I was using a variable
instead
of just sticking it in the wait statement. I thought it would be
better
to calculate it once and then test it and set to zero if negative.
So
now I have to do the calculation twice.

OK, sounds sensible.

I am getting the same error from a different assignment now. The
common
point is that a signal is on the right hand side of the assignment
and a
variable is on the left. I am using the variable assignment
operator,
":=". This is reported as an error, not a warning.

Last_Bus_Action := Bus_Command.Bus_Action;

In both cases, part of the right hand expression is an element in a
record. The error reports the record "Bus_Command" as missing from
the
sensitivity list, not the element! Could the VITAL process have a
bug
in regards to dealing with record elements? This doesn't sound
likely
to me. But then I don't even know what the VITAL process is.

That is weird. I thought that VITAL was a label you'd used in your

code, e.g.

vital: process...

But if it's not?

If it's vital as in "VITAL - VHDL Initiative Toward Asic Libraries"
then
I'd only expect to see it referred to if you were doing back-annotated
gate level simulation?

Maybe I need to contact Mentor about ModelSim.

Sounds like a good idea.

regards

Alan


--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.

 

[Brian Drummond]

On Tue, 05 Aug 2003 12:18:31 -0400, rickman <spamgoeshere4@yahoo.com>
wrote:

Alan Fitch wrote:

"rickman" <spamgoeshere4@yahoo.com> wrote in message

This is the line of code producing the error...

WaitTime := (ARM_command.RelTime - (now - CurrentTime));


It sounds like Modelsim is confused. Is it actually an error, or just
a warning? Having a signal read that is not in the sensitivity list
is not an error. Can you disable Modelsim's synthesis checks?

I am getting the same error from a different assignment now. The common
point is that a signal is on the right hand side of the assignment and a
variable is on the left. I am using the variable assignment operator,
":=". This is reported as an error, not a warning.

Last_Bus_Action := Bus_Command.Bus_Action;

If that's the case, then assigning the record field to an intermediate
signal would probably "fix" it. Not nice, but as an expedient to (a)
keep moving and (b) home in on the real problem, maybe worth trying.

-- parallel signal assignment
tempAction <= Bus_Command.Bus_Action;

-- within process or whatever
Last_Bus_Action := tempAction;

Assuming it works, then a support call to ModelSim, asking why one
works, but not the other, would be very worthwhile.

- Brian

 

[rickman]

Brian Drummond wrote:

On Tue, 05 Aug 2003 12:18:31 -0400, rickman <spamgoeshere4@yahoo.com
wrote:

Alan Fitch wrote:

"rickman" <spamgoeshere4@yahoo.com> wrote in message

This is the line of code producing the error...

WaitTime := (ARM_command.RelTime - (now - CurrentTime));


It sounds like Modelsim is confused. Is it actually an error, or just
a warning? Having a signal read that is not in the sensitivity list
is not an error. Can you disable Modelsim's synthesis checks?

I am getting the same error from a different assignment now. The common
point is that a signal is on the right hand side of the assignment and a
variable is on the left. I am using the variable assignment operator,
":=". This is reported as an error, not a warning.

Last_Bus_Action := Bus_Command.Bus_Action;

If that's the case, then assigning the record field to an intermediate
signal would probably "fix" it. Not nice, but as an expedient to (a)
keep moving and (b) home in on the real problem, maybe worth trying.

-- parallel signal assignment
tempAction <= Bus_Command.Bus_Action;

-- within process or whatever
Last_Bus_Action := tempAction;

Assuming it works, then a support call to ModelSim, asking why one
works, but not the other, would be very worthwhile.

- Brian

I already have a work around and have sent the problem to Xilinx (Mentor
does not support the Starter Edition). But thanks.


--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Mike Treseler]

Isaac wrote:

I am using 12 same entitites using Component decleration method.

Perhaps you mean a top architecture with 12 instances of some entity.

I am
giving input to 12 entities in such a way that the internal signal's
in each entity has different values from each other at any time. Now
the top vhdl final in which all the component decleration are defined
, I want to use the internal signal's of each block to perform some
calculation. The probelm is that in each of the 12 entities signal has
the same name (as I am using component decleration method to generate
same entity 12 time).

Each instance has a unique label:

my_entity_1 : entity work.my_entity
port map (reset => reset_sig, -- [in]
clk => clk_sig, -- [in]
i => i_1_sig, -- [in]
o => o_1_sig); -- [out]

my_entity_12 : entity work.my_entity
port map (reset => reset_sig, -- [in]
clk => clk_sig, -- [in]
i => i_12_sig, -- [in]
o => o_12_sig); -- [out]

The signal associated with an instance port is whatever
you define it to be in the port map.
I think of this as "wiring up" the instances.
These "wire" signals must be declared between
the IS and BEGIN of the top architecture.
It can be a different signal for each instance if you like.

Is there is any way to access these Signal in VHDL?

These signals are accessible anywhere in the top architecture.

-- Mike Treseler

 

[Ray Andraka]

It is pretty straight forward. See my article in XCell about digital
downcoverters. There is a link on the publications page of my website to
the paper.

Jan wrote:

Hi,

Can anyone point me at a vhdl design for a DDC, Digital Down Convertor,
in an FPGA. Preferably free.
It should be a wideband design with up to 10MHz and as low as 100KHz
bandwidth. Resolution of adc is 14bits.
Also it should be possible to synthesise it with the Xilinx Webpack.

Thanks for any help

Jan

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Clyde R. Shappee]

Then, please enlighten us as to how to use the block rams with Web-pack, without
using the core generator.

I looked at your web page and did not see in your example projects how you did
it.

Clyde

Nial Stewart wrote:

Clyde R. Shappee <clydes@the_world.com> wrote in message
news:3F64ABE0.783CE26F@the_world.com...
I just did a little experiment with the webpack software, instantiating a
fifo in the block ram.... and the software black boxes it because it
doesn't
know how to hook it up.
The .edn file from the core generator is missing, and as such XST does
not
know how to configure the block ram.
This is consistent with information I received from the Xilinx Apps guy.
Clyde

What are you trying to instantiate? If it's a component that you
previously generated from Coregen then it won't work as coregen
stitches whatever Blockrams together to get the structure you
need, creates a wrapper round them and gives it a sensible name.

If you try to instantiate the wrapper web-pack won't know what you're
talking about.

Have a look at the data sheet for whatever device you're targeting to
see what the blockrams should be called. As an example a 256* 8 bit dual
port
ram in SpartanIIE is RAMB4_S8_S8, you'll have to check the data sheet for
port names.

If you want bigger/wider structures than you get with one block ram you've
got to stitch them together yourself (with a wrapper if you want).

It would be almost a complete waste of time for Xilinx to release web-pack
if you couldn't access blockrams.

Nial.

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk

 

[Uwe Bonnes]

In comp.arch.fpga Clyde R. Shappee <clydes@the_world.com> wrote:
: Then, please enlighten us as to how to use the block rams with Web-pack, without
: using the core generator.

: I looked at your web page and did not see in your example projects how you did
: it.

Here is how I instantiate in in some verilog project:

RAMB4_S16_S16 ram0(.DOA(),.DOB(rdo_data_a),.ADDRA(rdo_wfifo_cnt),.ADDRB(rdo_rfifo_cnt),
.CLKA(!mclk_i),.CLKB(rclk),.DIA(dba_r[15:0]),.DIB(16'b0),
.ENA(1'b1),.ENB(1'b1),
.RSTA(1'b0),.RSTB(1'b0),.WEA(rdo_read_rrrr),.WEB(1'b0));

RAMB4_S16_S16 ram1(.DOA(),.DOB(rdo_data_b),.ADDRA(rdo_wfifo_cnt),.ADDRB(rdo_rfifo_cnt),
.CLKA(!mclk_i),.CLKB(rclk),.DIA(dbb_r[15:0]),.DIB(16'b0),
.ENA(1'b1),.ENB(1'b1),
.RSTA(1'b0),.RSTB(1'b0),.WEA(rdo_read_rrrr),.WEB(1'b0));

Hpe this helps.

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Nial Stewart]

Clyde R. Shappee <clydes@the_world.com> wrote in message
news:3F6891AD.B0291535@the_world.com...

Then, please enlighten us as to how to use the block rams with Web-pack,
without
using the core generator.

I already have.

"Have a look at the data sheet for whatever device you're targeting to
see what the blockrams should be called. As an example a 256* 8 bit dual
port ram in SpartanIIE is RAMB4_S8_S8, you'll have to check the data
sheet for port names."

And see Uwe's example above/below.

Spoon feeding bit.....

If you look in webpack/vhld/src/unisims/unisim_VCOMP.vhd you'll see
the models for all the rams supported. RAMB4 is supported in Spartan
devices (as specified in the SpartanII-E data sheet), I presume
RAMB16 configurations are supported in Virtex devices.

I looked at your web page and did not see in your example projects how you
did
it.

Download pico2spart.zip, unzip it and look at ../SW/picocode.vhd

This contains five blockram instantiations with the associated
configurations
containing the software for the Virtex picoblaze in a SpartanII.

These Blockrams are 1024 addresses* 4 bits.

For an example of a singla 256*16 ram download picoblaze.zip, then look at
.../sw/ROM_form.vhd . This is a template file, but it's exactly the way
the ram's instantiated in a real design.


Did you ask the Xilinx apps guy "Does web-pack support blockrams?", or
"Does web-pack support this ram I've generated with Coregen?" ?.

As I said, it would be almost a complete waste of time for Xilinx to
release web-pack if you couldn't get at the Rams.


Nial.

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk

 

[Martin Thompson]

"Plenolo" <plenolo@freemail.it> writes:

Hi all i am new in the group, i am a italian student of computer science and
i have hobbies for electronics, too... so i have using PIC, St6/7
microcontroller, etc.. now my dream is develop some circuit with fpga (or
similar) and VHLD language. I have just a bit studing (only teorically) VHDL
in my university, but now i would REALLY program some chip for develop some
simple and medium project.
I have not money (and i don't want ) to buy some original developing
system, so i would home build some free "programmer" (in-circuit JTAG ???)
how i have do in pass for PIC / St6/7 programmers

You'd be better off on comp.arch.fpga, for the actual hardware
questions - I've crossposted to there and set the followups to go
there also.

Regarding programming hardware, Altera have the Byteblaster schematics
downloadable from their site, in the Byteblaster datasheet. I can;t
recall if Xilinx have similar.

Thank you very much to all friends, and sorry for my very bad and poor
english language

It's better than my Italian!

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

 

[Vinh Pham]

If your synthesis tool creates FFs that power up as zero, by default, then
you could try this:

process(clk)
begin
if rising_edge(clk) then
if reset_n = '0' then
reset_n <= '1';
end if;
end if;
end process;

reset <= not(reset_n);

--
Regards,
Vinh Pham
vinh-pham (a) hawaii rr com

 

[ALuPin]

Duane Clark wrote:

It makes no sense to say that you are going to "synchronize the data bus
with some register stages". What will invariably happen when you try to
do that is that some of the portions of the data bus will occasionally
exit the last stage on different clocks. Each individual bit of the bus
may be synchronized correctly, but the bus as a whole will not, without
taking additional measures.

Thank you for your answers.
The external data stream I am talking about comes form an USB transceiver
which sends the data synchronous to 60MHz clk which I can use in my FPGA
as FIFO write clock. Under this assumption of synchronous data stream
the portions of the data bus will NOT occasionally exit the last stage
on different clocks, will they ?

My idea was to use additional register stages to improve the performance
of the data flow.

Rgds
André

 

[Dan Nilsen]

Hello,

Thanks for the responses.

The reason I need to do it is because I get a (signed) quotient from a
divider in a range I already know. I divide a 8x8 DCT by 1 out of 2
preset Quantization matrices, which in turn are scaled by an integer
ranging from 1-32. Sometimes I will get a 0 from the divider, during
this case I don't want to transmit "too many" bits. I do however
realise that this might be impossible, but I appreciate answers given
me here.

Thanks,

Dan

 

[Berty]

Peter,
While I understand your point I'm afraid this is why you see so many
Eng that know just about nothing except copy paste of IP module.
Of course Async FIFO is not as simple as shift register. And of course
it involve some thinking and I would strongly recommend anyone who want
to design such thing or for that matter any new design to have DR of
more experience Eng to see how he did what he did and see how to
improve or fix the wrong.
I'm fully aware of the Empty Full having designed several FIFO of all
type and flavor.
Except for the obvious of the advantage of knowing what you do and
example as for why you should know to design by yourself can be that
Some FIFO depend on the implementation when they have one last entry
will toggle the empty while other will not.
Sometime this toggle can be more useful however if you know Zilch about
how the FIFO was design you can do nothing and have to adapt yourself
to what ever the core give even if this is not the best for the design
you do.
And talking about synconizers and Gray counter etc while to use them
correctly is important this is not rocket science, Sure to give
complete and full explanation of what Metastable is and the effect of
it in clear way and not just using "wave hand" explanation can be
challenging but the actual implementation once you understand the
meaning of it is not so difficult that one have to pass it aside and
use other proven code.
I guess it all boil down to are you an Eng who want to be a copy/paste
one or are you an Eng who want to know how to do thing and yes ONCE you
know use other if they make sense, but even for this to tell if it make
sense you need to understand and not just be another copy/paste-Eng as
more and more I for one encounter.

And all those who might give example on how they saved money, time etc
by using other FIFO and not learning how to do it the right way are
just an example as why you SHOULD learn and not just be copy paste one
and use this as example to why to use other code.

Back to Math using your own logic is equivalent to say to Eng you
should learn how to do 1+1 however to do integral of X^2 from 0 to 2 is
to complex so use calculator, I do hope university will not go with
this logic and those that do well maybe from there we get all the
copy-paste Eng's.

Remember that any minute you "Waste" today for learn how to do it
will pay thousands time in your future, when you have design which are
not simple and there is no IP and you need to draw from your own
experience, which if it involve only/mainly copy-paste without the
knowledge mean you will never become ASIC leader or Architect of new
complex designs and you will stay basic simple Designer, as no
knowledge mean poor capability.

 

[Marc Randolph]

Berty wrote:

Peter,
While I understand your point I'm afraid this is why you see so many
Eng that know just about nothing except copy paste of IP module.
[...]
Back to Math using your own logic is equivalent to say to Eng you
should learn how to do 1+1 however to do integral of X^2 from 0 to 2
is
to complex so use calculator, I do hope university will not go with
this logic and those that do well maybe from there we get all the
copy-paste Eng's.
[...]

And where do you stop? By your own logic, they can't just stop at
doing integrals. You need to know how to derive all the integral
short-cuts that you use, for fear that someday while waiting for a bus,
someone holds a gun to your head and makes you re-derive the integral
of sin(x)dx. But you can't stop there either - you have to move on to
differential calculus and partial differential equations. But that's
not all, then you need to... (etc)

Moving back to the electronics world, how about other components in the
FPGA (or an ASIC)? Before I can use the PLL or CDR within the Rocket
I/O, should I understand it so well that I could design one myself?
What about the DCM? Do I need to be able to design my own latch-up
resistant, ESD protected, discrete input and output buffers before I
can use an ASIC vendors' IO cell? What about the optical transceiver
that I connected to the Rocket I/O - do I need to know exactly how the
pin diodes and laser drivers work before I can use an optical
transceiver?

Everyone is going to draw the line in different spots, based upon their
needs. Not everyone wants or needs to specialize in FIFO design. If
you can do it, great - it gives you a slight competitive advantage for
a few jobs out there (or turn it into a life-long job, as Peter has).
But that alone does not indicate

Having said all this, however, I have to agree with some of the
underlying points upon which you've placed your FIFO example... that
engineers need a firm understanding of the basics so that when they are
called upon to design something, they know where to start. Even more
importantly, they understand the limits of their knowledge, and if
necessary, know how to educate *themselves* further on the topic,
without much outside help. That's the true sign of an engineer - not
if they can design an async FIFO.

Have fun,

Marc

 

[Peter Alfke]

Well, I did design FIFOs,and in particular the asynchronous arbiter in
the Virtex-4 BlockRAM FIFO ( and the test methodology for it), and I
measured asynchronous behavior and metastable recovery. But these were
major efforts, and were based on many decades of design experience.
Xilinx can afford such exploration since we expect that many of our
customers will eventually benefit from it...
It's just not what you should entrust a junior engineer to do.
Let them grow up with synchronous logic, and carefully graduate to data
transfer across clock boundaries later. When you cannot simulate, you
really need to be both experienced and confident
Peter Alfke

 

[ALuPin]

"cas7406@yahoo.com" <cas7406@yahoo.com> wrote in message news:<1114549471.965608.217160@f14g2000cwb.googlegroups.com>...

Andre,

You should be able to constraint the Tco for the DQ and DQS in the
input_setup/clock_to_output preference window.
Check the example at
$ispLEVER/ispcpld/examples/latticeEC/preferences_attributes/ddr/vhdl/ddr.syn

and let me know.

rgds,

cristian

Hi Cristian,

I checked the example, and yet, the tCO is for the bits of DQ
identical.

But the example does not use the template from the IP Manager but
the particular modules.

ispLEVER5.0 is my hope )

Rgds
André

 

[Bryan]

I think you highly under estimate the average engineer. I believe this
is because you only deal with people that can't get their designs to
work. There are a lot more out there that never need help and you
never hear from them. I would hate to think what engineers are
designing logic that can't design an async FIFO(actually I know one,
see bleow). My experience has shown that cut and paste does not
provide the best performance, it may provide the best time to market as
pointed out. When performance is more important than time to market
you design everything yourself and highly optimize it. Apparently you
only work with some below average junior engineers. We did have a
senior senior engineer that couldn't design his own async FIFO, just
goes to show there are below average people at all levels. That is the
same type of mentality that would not hire a person with less than 5
years experience. I hope the people with that mentality end up with
senior senior on their team.




Peter Alfke wrote:
> It's just not what you should entrust a junior engineer to do.

 

[Irwin Kennedy]

dan.nilsen@gmail.com (Dan Nilsen) wrote in message news:<50a67599.0504260257.6c83de8e@posting.google.com>...

Hi all!

I have a problem that someone here might have the answer to. I have a
divider that takes inputs of 13 and 12 bits, and produces an output of
12 bits. I have a component to strip away the redundant bits from the
divider, if the result of the division is, say an int value of 6, I
don't want to use all 12 bits. This circuit is a part of an MPEG-4
device, a quantizer, so I want to compress as much as possible.

I think you will find the step following quantization actually
performs the compression. Quantization just prepares the values so
they compress well (loads of zeroes). Something like the huffman and
run length encoding algorithms will take the quantized values and
express them concisely (compress them).

 

[Peter Alfke]

Well, Bryan, here is a test for a smart engineer:
Assume a 1K-address deep FIFO ( data width does not matter) implemented
in a dual-ported RAM.
Design only the EMPTY-flag detect circuit that operates reliably at
totally asynchronous write and read clock frequencies of >300 MHz, and
show a test circuit that proves that this operation is reliable.
(Hint: The Virtex-4 BlockRAM does this job at up to 500 MHz worst
case).
Peter Alfke