A
Alessandro
Guest
thutt wrote:
The "clk_pin" is just the name of the signal attached to the 50MHz clock
oscillator, specified in a pin constraint in usual way:
NET "clk_pin" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
The constraint just tells that this is a 50MHz clock. I don't know exactly
how it works (and I'll certainly read the two links provided by Jochen), I
just copied the first one from a fpgaarcade source code (asteroids, if I
remember).
I made the second (75MHz) by myself, recalculating timings with the ratio of
50 to 75 (the difference in frequency). clk_pll is the name of an internal
signal clock, not a physical pin. I'm not really sure that using "TS01"
twice is a good practice, I have to learn about it.
things in many xilinx projects (for example the default picoblaze project,
flashed into the board as a factory default and downloadable from the xilinx
site): this is what's inside it's .ucf file:
NET "clk" LOC = "C9" | IOSTANDARD = LVTTL;
# Period constraint for 50MHz operation
NET "clk" PERIOD = 20.0ns HIGH 50%;
generate almost any frequency you need, starting from a given clock source
(50MHz in our case). A dcm will multiply then divide the frequency in a very
flexible way.
You can create an instance for a dcm by running the "Core Generator" under
the ISE/Accessories program group or, inside ISE, by adding a source file to
the project then selecting "IP Coremanager" instead of, for example, a new
..vhd file).
You then select "fpga features and design" then "clocking" then the fpga
family then "single DCM_SP, then "customize".
The clock manager can simply shift the input clock by 90, 180, 270 degrees
or generate a different frequency. For the latter, you should check the box
"CLKFX" (it is a pin on the drawn component on the screen). You input the
osc clock (50MHz) and the desired output frequency, then the gui will
calculate the parameters and tell if it could be done or not.
For example, the zx-badaloc project runs at 85MHz generated by a dcm with
*17 multiply then /10 divide (50*17/10 = 85).
You can easily obtain a 300MHz clock by multiplying by 6 the 50MHz input
clock.
Then, the gui generates a "component" and a wrapper to be placed in the
project. I remember I've had problems launching from inside ISE so I prefer
starting the core manager from the start menu, as described above. The
wrapper for my 85MHz clock was:
COMPONENT pll
PORT(
CLKIN_IN : IN std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
END COMPONENT;
then the "connections" to my signals:
-- PLL
mainpll: pll PORT MAP(
CLKIN_IN => clk_pin, -- oscillatore clock 50MHz
CLKFX_OUT => clk_pll -- clock sintetizzato 85MHz
);
Ciao!
Alessandro
All the statements are in the .ucf file.
The "clk_pin" is just the name of the signal attached to the 50MHz clock
oscillator, specified in a pin constraint in usual way:
NET "clk_pin" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
The constraint just tells that this is a 50MHz clock. I don't know exactly
how it works (and I'll certainly read the two links provided by Jochen), I
just copied the first one from a fpgaarcade source code (asteroids, if I
remember).
I made the second (75MHz) by myself, recalculating timings with the ratio of
50 to 75 (the difference in frequency). clk_pll is the name of an internal
signal clock, not a physical pin. I'm not really sure that using "TS01"
twice is a good practice, I have to learn about it.
I found it in the source code of an fpgaarcade game. You will find similar
things in many xilinx projects (for example the default picoblaze project,
flashed into the board as a factory default and downloadable from the xilinx
site): this is what's inside it's .ucf file:
NET "clk" LOC = "C9" | IOSTANDARD = LVTTL;
# Period constraint for 50MHz operation
NET "clk" PERIOD = 20.0ns HIGH 50%;
The spartan fpga has some "DCM" units (digital clock managers) which will
generate almost any frequency you need, starting from a given clock source
(50MHz in our case). A dcm will multiply then divide the frequency in a very
flexible way.
You can create an instance for a dcm by running the "Core Generator" under
the ISE/Accessories program group or, inside ISE, by adding a source file to
the project then selecting "IP Coremanager" instead of, for example, a new
..vhd file).
You then select "fpga features and design" then "clocking" then the fpga
family then "single DCM_SP, then "customize".
The clock manager can simply shift the input clock by 90, 180, 270 degrees
or generate a different frequency. For the latter, you should check the box
"CLKFX" (it is a pin on the drawn component on the screen). You input the
osc clock (50MHz) and the desired output frequency, then the gui will
calculate the parameters and tell if it could be done or not.
For example, the zx-badaloc project runs at 85MHz generated by a dcm with
*17 multiply then /10 divide (50*17/10 = 85).
You can easily obtain a 300MHz clock by multiplying by 6 the 50MHz input
clock.
Then, the gui generates a "component" and a wrapper to be placed in the
project. I remember I've had problems launching from inside ISE so I prefer
starting the core manager from the start menu, as described above. The
wrapper for my 85MHz clock was:
COMPONENT pll
PORT(
CLKIN_IN : IN std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
END COMPONENT;
then the "connections" to my signals:
-- PLL
mainpll: pll PORT MAP(
CLKIN_IN => clk_pin, -- oscillatore clock 50MHz
CLKFX_OUT => clk_pll -- clock sintetizzato 85MHz
);
Ciao!
Alessandro
. If you can't afford a PSL license then look into the free OVL