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So why do you not use schematic capture tools for your designs - or is thatOn Jul 26, 10:12 am, Frank Buss <f...@frank-buss.de> wrote:
rickman wrote:
The process based description is not immediately clear to me at first
glance. I *do* have to think about it since that is not what I
picture in my mind. I visualize a MUX controlled by GenEn feeding an
AND gate with BERTSel. The Verilog like assignment maps exactly to
that visualization. The others require me to mentally convert the
syntax from and IF statement to the AND gate not to mention the length
of the code. But like I said, it is not that this is hard to
understand, it is not what I pictured in my mind and so I had to
perform a conversion from the logic to the syntax. That takes time
and is a distraction from making my work accurate.
I have no doubt that others may find that verbose code is easier for
them to read. But I find concise code is best (but not too!
concise). There are any number of different logic forms to be
expressed and each is expressed best in different ways. I think the
selection statement is an operator that has a useful place in VHDL.
I'm just sorry it wasn't included. I guess it would have been hard to
provide for overloading since it does not fit the standard uniary or
binary format.
Rick
Yep that is a totally serious question.On Jul 26, 12:50 pm, "Icky Thwacket" <i...@it.it> wrote:
"rickman" <gnu...@gmail.com> wrote in message
So why do you not use schematic capture tools for your designs - or is
that
too uncool?
Icky
Is this a serious question? Or are you just playing devil's
advocate?
Probably the single biggest reason to use an HDL instead of schematics
is the portability it provides. Schematics have always locked you
into a manufacturer unless you are willing to reenter your design for
every company's chips you wish to try.
But I was a diehard on schematics. Just like Ray Andraka, I saw a lot
of utility in them. He finally switched when he found that he could
instantiate primitives and achieve the same degree of control over the
design details that he got with schematics. I switched when I found
out how handy it was to have text based designs instead of proprietary
formatted schematics. But there are any number of other reasons. Do
you really not understand what they are? I don't think I ever
considered schematics "uncool". In fact, one of the cooler things
about being an engineer is having an E sized print of a schematic
design hanging on your wall.
Rick
I don't think drawing logic is a good way to start. Using flow chartsOn Jul 26, 7:56 am, Brian Drummond <brian_drumm...@btconnect.com
wrote:
On Sat, 26 Jul 2008 10:31:32 +0100, Jonathan Bromley
jonathan.brom...@MYCOMPANY.com> wrote:
On Fri, 25 Jul 2008 22:46:26 -0700 (PDT), rickman wrote:
In VHDL an operator can be overloaded. But can a new operator be
created? There is more than once I would like to use the very concise
notation available in Verilog such as the select operator. Is there a
way to create the selection operator in VHDL? Looking at the
structure, I guess it just doesn't fit the mold for VHDL with three
operands.
More dynamic OO languages support arbitrary operator creation; Smalltalk
would be an example, or the old Linn Lingo.
It's not VERY complicated _in_that_environment_ where static typing is
almost non-existent (strong typing can be rigorous, but implemented at
runtime) BUT ...
(1) you are limited to the creation of binary operators; so ?: is still
tricky, to put it mildly, and
(2) operator precedence is usually predetermined and deeply embedded in
the parser. The above languages solved this problem by allocating
precisely one precedence level to all operators - in other words, use
brackets.
I suspect extensible operator precedence was the main complexity in
ALGOL-68.
But anyway I suspect you'd have to destroy VHDL to add extensible
operators...
I know I can create a function for this such as select(sel,a,b), but I
like the form of the notation sel ? a : b, very clear and concise. I
guess I could always switch to Verilog... :^)
It may be personal preference, but I find if-then-else MUCH easier to
read in somebody else's code.
?: does save a few of those precious characters though.
- Brian
The problem is not so much reading the code, but is writing. I think
in the terms of the logic, usually a schematic/block diagram. Then I
try to express that logic in the language. It is not uncommon that it
is simply impossible to express the logic in the form I have drawn
it. Then I have to convolute it to come up with something that is
what I have drawn, or at least I hope so.
This construction wouldn't be very clear for people that areExample: A data mux controlled by the output of an AND of a signal and
the output of a mux. This is four control signals gated together to
drive the control on the data mux. Here is what I ended up with.
BERTEn <= '0' when BERTSel = '0' else
not SyncPOSSel when GenEn = '0' else
not GenPOSSel;
I don't think that the diagram I drew comes to mind when you see this
code. Maybe a process with an IF statement would be slightly more
clear, but the verbosity presents an obfuscation of its own from the
"clutter" created.
process ( BERTSel, SyncPOSSel, GenEn, GenPOSSel) begin
if (BERTSel = '0') then
BERTEn <= '0';
elsif (GenEn = '0') then
BERTEn <= not SyncPOSSel
else
BERTEn <= not GenPOSSel;
end if;
end process;
The clutter is from the sheer size of the code. The first three line
example is a bit obtuse, the 9 line example is large enough to make it
hard to see the rest of the code and so to see how it fits into the
big picture. Compare the two examples to this code...
BERTEn <= BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel;
I see your point and I agree. I would like to write my programmableThis is what I expect a concurrent statement to look like, not to
mention that it represents exactly the image I had in my head and on
the whiteboard, making it much easier to write.
I am sure there are those who disagree and much prefer the verbose
process. Maybe I'm just not cut out for the regimen of VHDL.
Try removing the range from your Y output. You might also want to tryHere's my issue:
This is the port definition in Verilog:
FSM2 F2(.CLock(fsm2clk),
.reset(fsm2rst),
.Control(ctrl),
.Y(Fsm2Out));
This is the port definition for VHDL:
entity FSM2 is
port (CLock, reset: in std_logic;
Control: in std_logic;
Y: out integer range 0 to 4 );
end FSM2;
When we run this, the model tech simulator says:
# ** Fatal: (vsim-3362) The type of VHDL port 'y' is invalid for
Verilog connection (4th connection).
# Time: 0 ns Iteration: 0 Instance: /top/FSM2 File: fsm2.vhd
Line: 7
# FATAL ERROR while loading design
# Error loading design
Error loading design
Does anybody know what's wrong with this?
What should I do to connect VHDL ports to Verilog?
Thanks
Valerie
From what I remember it used to be the case that a concurrent clockTorsten Landschoff wrote:
How about the inverse problem (data arriving before the clock because
the clock is forwarded using concurrent signal assignments)?
A clock does not belong in a signal assignment.
-- Mike Treseler
So how does one generate the clock signal in a VHDL testbench?
For such a large memory model you might need to use a sparse array whichHi,
I am trying to simulate my design via ModelSim but my design will use
an external RAM in real environment and I could not manage to
instantiate a model for ram. The actual ram has 19 bits of address bus
and 36 bits of data bus. It is a ZBT ram.
What I tried was creating an signal array of 2^19x36 in the testbench
assuming it as an external ram and use it, however this time "out of
memory" error comes out and my simulation crashes.
Thank in advance for your suggestions.
Regards.
Enes
Hi,
I need help for timing constraints in Xilinx virtex 4 Fx.
I have this design with two clocks on bufgmux and two components.
First clock : 50 Mhz
Second clock : 300 Mhz
Component A, need to work at 50Mhz
Component B, need to work at 300 Mhz
___________
| |
| |
|Component|
__________| A |
| | |
| |_________|
|
|\ |
CLK_50M ---| \ |
| \_________|
| / |
CLK_300M---| / |
|/ |
| ___________
| | |
|________| |
|Component|
| B |
|_________|
When I define both clock timing constraints on ucf file, ISE apply 300
Mhz for component A and B.
But the component A doesn't work at 300 Mhz and I don't whant that the
component A work at this frequency.
How i do for put the good frequency on each component whithout use two
bufg instead one bufgmux? (specific timing constraint)
Regards,
Yannick
The key words here are 'may'...and that it's a 'warning'. Good to questionHere's a weird one. I have a boolean generic, say FOO, that is
determines how some logic is generated. When analyzing with ModelSim
XE 6.3c, I get a warning that says, "non-resolved signal 'bar' may
have multiple sources."
bar <= sel(FOO, bletch, loadthis);I've done this sort of thing before, although with std_logic and not
natural. So obviously bar (of type natural) is not a resolved type
whereas std_logic is, which is why I've never seen this warning
before.
Is there a better way to do this?
I usually use simply it to surround...On Thu, 31 Jul 2008 14:45:27 -0700 (PDT), Andy Peters <google@latke.net
wrote:
This constant can be used to generate different behaviour in synthesis
and simulation.
Which is not usually a good idea; though there are occasionally good and
safe uses for it. (For example, to greatly speed up a serial interface
to reduce wasted simulation time,
Off to a bad start....std_logic_vectors and addition...oh well.Hi,
I am having a quite strange problem when I am using the addition with
std_logic types.
OK.I am basically using a std_logic_vector containing the address for
accessing a SRAM. After writing an octect in the RAM I am adding 8 to
the address for the next word.
Displayed on what?As I did not have the expecting design, I have displayed the content
of the address vector and I have something ... strange.
A simulation would likely clear this all up...Here are the values I obtain :
0000 0000
1100 1000
1001 0000
0101 1000
0010 0000
1110 1000
1011 0000
0111 1000
0100 0000
0000 1000
1101 0000
etc
I can see something is quite correct with the 2^0 -> 2^5 bits but only
for a few time and the 2^6 & 2^7 bits are totally wrong.
Yes, suspect everything else first...then question your own code and design.I thought that it could come from the library I used
Frequently that is the result...library is fine, so it must be the new andbut after
different tests it does not seem to be the problem.
When I try for
exemple a LED_out <= "0000 0000" + 8; everything is correct ...
Use ieee.numeric_std instead of std_logic_arith and std_logic_unsigned.Here is the reduced portion of the concerning code. I have removed
some signals which does not concern the address mechanism.
------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
I wonder where the read and write signals are? Oh well, you're onlyentity RAM_controller is
port (CLK, Reset,flag_data_in: in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
signal_on : in std_logic; -- 0 : mode transfert - 1 : mode signal
rw : in std_logic; -- 0 : ecriture - 1 : lecture
sram_io : inout std_logic_vector(15 downto 0);
sram_a : out std_logic_vector(17 downto 0);
LED_out : out std_logic_vector(7 downto 0);
);
end RAM_controller;
Synchronous process, so far so good.architecture arch_RAM_controller OF RAM_controller IS
type state_machine is(idle,RAM_read);
signal current_state, next_state : state_machine;
signal I : std_logic_vector(15 downto 0);
signal counter_write,counter_read : unsigned(7 downto 0);
signal counter_write_next,counter_read_next : unsigned(7 downto 0);
signal addr, addr_next : std_logic_vector(17 downto 0);
begin
process(CLK,Reset)
begin
if Reset='1' then
current_state<=idle;
counter_write <= (others => '0');
counter_read <= (others => '0');
count <= (others => '0');
addr <= (others => '0');
elsif (CLK'event and CLK='1') then
current_state<=next_state;
counter_read <= counter_read_next;
counter_write <= counter_write_next;
count <= count_next;
addr <= addr_next;
end if;
end process;
Hmmm...you seem to be missing quite a few signals from the sensitivity list.process(current_state,rw,flag_data_in,data_in)
begin
counter_read_next <= counter_read;
counter_write_next <= counter_write;
addr_next <= addr;
case current_state is
when idle=
LED_out <= addr;
if rw = '0' then -- write
if flag_data_in = '1' then
next_state <= RAM_write;
else
next_state <= idle;
end if;
else
next_state <= idle;
end if;
when RAM_write=>--ecriture
LED_out <= addr;
sram_a <= addr;
sram_io <= "00000000" & data_in;
sram_we <= '0';
addr_next <= addr + 8;
counter_write_next <= counter_write + 1;
next_state <= idle;
end case;
end process;
Is the input signal 'rw' synchronous to the clk? More generally any inputend arch_RAM_controller;
---------------------------------------------
The flag_data_in is high when a word is transfered by a RS232 link
(the STOP state of the RS232 controller).
If anyone has an idea on this problem it would be great because I am
really clueless on that issue !
http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdfIf anyone has an idea on this problem it would be great because I am
really clueless on that issue !
Xavier
Below is a snippet of your current code with two processesNow, the main point I did not really understand is the "all-in-one"
process one. I understand the synchronous and asynchronous scheme in
what you wrote. But in my case I don't really catch how to implement
it.
Good point, but remember up counters are fine too! E.g. divide by 200...One suggestion. When implementing counters, it is slightly more
efficient to implement them as loadable down counters.
This is because in most technologies there is a carry chain built in
that can detect when counter is 0. If you are counting up to (M-1)
the synthesizer has to use LUTs to detect the final state if M is not
a power of 2.
Rick
Post some example so we don't have to guess endlessly about what you'reThe bit I don't get yet is why a coinational process, with just one
register in the sensitivity list (IR) process is instruction decode
from insrtuction register, inferes latches on intermediate signals,
when there latched contents have no relevance. The intermediates
should always be recalculated.
One can only speculate based on your cloudy description.Is it because only some paths through the process do not assign to
them? As I thought this was only relevant to synchronous behaviour.
a<=b;"jacko" <jackokr...@gmail.com> wrote in message
news:8837cbe8-b3fd-4a25-9cc6-a474556616c5@v57g2000hse.googlegroups.com...
The bit I don't get yet is why a coinational process, with just one
register in the sensitivity list (IR) process is instruction decode
from insrtuction register, inferes latches on intermediate signals,
when there latched contents have no relevance. The intermediates
should always be recalculated.
Post some example so we don't have to guess endlessly about what you're
talking about when you toss around things like
* 'intermediate' signals (as opposed to what? an 'immediate' signal? There
is no such distinction, so why are you making one?)
* latched contents have no relevance....does that mean you write
non-relevant code? Maybe you shouldn't do that
I'll strongly second Mike's advice and I'd go further and state that latchesjacko wrote:
It *is* a problem because fpga latches are only safe
if excruciating timing constraints are applied in synthesis.
What makes you think that 'carry routing' is not being done properly? IfHi
I have optimized alu some. and fixed correct return address stacked.
It is now compiling at 301 LEs, but has a low fmax of 25MHz in C3
speed MAX II. Is there any way of forcing carry routing via VHDL or is
that a tool option?
Actually, I take that back you can get latches from the code...again, like I"jacko" <jackokring@gmail.com> wrote in message
news:9aaec06e-9ac0-4228-8474-fc95cb6380d7@d77g2000hsb.googlegroups.com...
On 9 Aug, 16:24, "KJ" <kkjenni...@sbcglobal.net> wrote:
"jacko" <jackokr...@gmail.com> wrote in message
news:8837cbe8-b3fd-4a25-9cc6-a474556616c5@v57g2000hse.googlegroups.com...
You won't get warnings about latches from the above code, so if you want
some help on that topic, you'll have to post some code demonstrating what
code Quartus is actually flagging...I'm too lazy to download your code
from the web site, run it through Quartus, etc.
Synthesis implements the source code that you wrote. If you write stuffOn 9 Aug, 21:09, "KJ" <kkjenni...@sbcglobal.net> wrote:
"KJ" <kkjenni...@sbcglobal.net> wrote in message
news:6lmnk.32983$co7.4027@nlpi066.nbdc.sbc.com...
Now themain thing is as i implemented the alu by explicit xor and and,
I am wondering how o indicate to the synthesizer that a signal should
be fed through fast carry logic.
Synthesis mostly puts things where they are needed in order to communicatethe synth has distributed the alu all
over. knoking fmax to 25MHzor lower.
stop thinking you can do better.Any idea how to indicate special carry property in vhdl?
By using arithmetic operators and letting synthesis do some of the work and