Clock Edge notation

[KCL]

As the two box are the same size you vcould only declare 1 type tag and use
it both for your two signal tag


"Neo" <zingafriend@yahoo.com> a écrit dans le message de news:
1109849178.223444.51630@z14g2000cwz.googlegroups.com...

well, here is two boxes of 8registers with 9 bits each which can be
read and written into.
----CODE------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity xyz is
port(
clk: in std_logic;
din: in std_logic_vector(8 downto 0);
add: in std_logic_vector(3 downto 0);
rdwr: in std_logic;
do : inout std_logic_vector(8 downto 0)
);
end entity;

architecture acrh_xyz of xyz is
type tag_array1 is array (0 to 7) of std_logic_vector(8 downto 0);
type tag_array2 is array (0 to 7) of std_logic_vector(8 downto 0);

signal tag1: tag_array1;
signal tag2: tag_array2;
begin

--reading
do <= tag1(conv_integer(add(2 downto 0))) when (add(3) = '0' and rdwr =
'0') else
tag2(conv_integer(add(2 downto 0))) when (add(3) = '1' and rdwr =
'0') else
(others => 'Z');

--writing
process(clk)
begin
if(clk'event and clk= '1') then
if(rdwr = '1') then
if(add(3) = '0') then
tag1(conv_integer(add(2 downto 0))) <= do;
else
tag2(conv_integer(add(2 downto 0))) <= do;
end if;
end if;
end if;
end process;

end acrh_xyz;

 

[Mike Treseler]

springer54@hotmail.com wrote:

So for school I need to make a 2-way set associative cache with a
write-back policy and LRU replacement policy.
The trouble is, I go to such a good engineering school (top 5), they
seem to believe that they don't actually need to teach VHDL or the
design tools. Nah, we can figure those out on our own.

Sounds like you're in an upper level class
that requires working knowledge of an HDL.

I liken this to teaching the concept of Red-Black trees and then having
them say, "go write a program that implements them!" without them
having actually taught basic structures in code (not to mention a
programming language)...

I would hesitate to take an algorithms class
without working knowledge of some programming language.

Anyway, any help would be appreciated. I *think* what I'm asking about
is pretty basic. But I haven't a clue!

Consider getting a tutor or dropping the class.

-- Mike Treseler

 

Though it would be nice to drop the class, it is quite important to me.

And I too would hesitate to take an algorishms class without working
knowledge of some, but as far as my problem goes, that is just the way
things are done here.

This is not my first class using VHDL. I had another where it was
essentially sink or swim. I did okay, but that was a while ago. Even
then, they didn't teach VHDL but rather expected you to just pick it up.

 

Thanks, Neo!

It looks great, but there were a few changes I needed to make to make
it a little more compatible with what I need to do. For one, I need
two separate tag boxes, etc.

So I've changed it to the following, but would like it proofread if you
(or someone else) doesn't mind:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY MP2_2;
USE MP2_2.LC3b_types.all;

ENTITY tag_array IS
PORT(
TagIn : IN LC3b_tag;
WhichSet : IN std_logic_vector (2 DOWNTO 0);
WriteTag : IN std_logic;
clk : IN std_logic;
TagOut : OUT LC3b_tag
);

-- Declarations

END tag_array ;

-- hds interface_end
ARCHITECTURE untitled OF tag_array IS
type tag_array is array (0 to 7) of LC3b_tag;
signal tag : tag_array;
BEGIN
--reading
TagOut <= tag(to_integer(WhichSet(2 downto 0))) when (WriteTag = '0')
else (others => 'X');

--writing
process(clk)
begin
if(clk'event and clk= '1') then
if(WriteTag = '1') then
tag(to_integer(WhichSet(2 downto 0))) <= TagIn;
end if;
end if;
end process;
END untitled;

LC3b_tag is just a std_logic_vector(8 downto 0)

 

Also, I tried to reduce this for an array of 8 bits that I also need,
but the VHDL compiler spits back, "Error, aggregate cannot be of scalar
type 'std_logic'. Must be array or record"

here's the offending code (offending line marked with ***):

ENTITY eight_tall_1bit_array IS
PORT(
BitIn : IN std_logic;
WhichSet : IN std_logic_vector (2 DOWNTO 0);
WriteBit : IN std_logic;
clk : IN std_logic;
BitOut : OUT std_logic
);

-- Declarations

END eight_tall_1bit_array ;

-- hds interface_end
ARCHITECTURE untitled OF eight_tall_1bit_array IS
type bit_array is array (0 to 7) of std_logic;
signal abit : bit_array;
BEGIN
--reading
***BitOut <= abit(to_integer(WhichSet(2 downto 0))) when (WriteBit =
'0') else (others => 'X');

--writing
process(clk)
begin
if(clk'event and clk = '1') then
if(WriteBit = '1') then
abit(to_integer(WhichSet(2 downto 0))) <= BitIn;
end if;
end if;
end process;
END untitled;

 

[Takuon Soho]

Thanks, this is idea interesting.

But, I ended up breaking counter stuff into a seperate process
and then it synthesized fine. Did'nt use up much macrocells
either.

Thanks everyone.

Tak.


"Egbert Molenkamp" <molenkam_no_spam@cs.utwente.nl> wrote in message
news:d07qh2$ahh$1@ares.cs.utwente.nl...

james_pannozzi@cisgi.com> schreef in bericht
news:1109782534.193265.25960@f14g2000cwb.googlegroups.com...
Thanks, I think I can take the approach of making everything
synchrnous to the clock signal and yes the MsgRcvd is at least
one clock signal high.

If I make everything synchonous to the clock signal, then an I follow
the well known reset/clk paradigm that you mentioned?

How is it done with 3 signals instead of 2?

Thanks
Tak


Something like:

architecture ...
signal MsgRcvdPrev : std_logic;
begin

process(reset,clk)
...
begin
if reset='1' then
-- here the reset stuff
elsif rising_edge(clk) then
if MsgRcvdPrev='0' and MsgRcvd='1' then
-- now you have detect the '1' (I Assumed it is long enough high)
send_xx <= '1';
sw_linex <= '1';
msgFlag := 0;
bus_0_11 <= conv_std_logic_vector(my_counter, 12);
end if
MsgRcvdPrev <= MsgRcvd; -- flipflop
end if;
end process;

Egbert Molenkamp

 

[Neo]

The error is because you have "others" clause in else part for a signle
bit . it should just be "x".
But I dont understand why you are resorting to 'X' when its not
synthesizable.

 

It's the way they want it done. *shrugs*

 

Thanks for both ideas, I will try them out next week.

Thanks

colin

 

[Charles Bailey]

Logic like this is SOOO much easier if you just make everything
synchronous.
A synchronous process should have only the clock in the sensitivity
list. (Actually, I prefer to WAIT on a clock edge and not have a
sensitivity list at all; even simpler.)
If this is going to be synthesized into real logic, you shouldn't put
initial values on any ports or signals. You must design the logic so
that a reset sequence gets it into a known state.

Try something like this:

entity count12 is port (
clk: in std_logic;
reset: in std_logic;
start: in std_logic;
msgRcvd: in std_logic;
sw_linex: out std_logic;
send_xx: out std_logic;
bus_0_11: out std_logic_vector(11 downto 0)
);
end count12;

architecture behavioral of count12 is
begin

process
subtype counter_ty is integer range 0 to 4095;
variable my_counter : counter_ty;
variable counting : bit;

begin
wait until clk='1';
if reset='1' then
counting := '0';
send_xx <= '0';
sw_linex <= '0';
else
if start='1' then
my_counter := 0;
counting := '1';
elsif msgRcvd='1' then
bus_0_11 <= conv_std_logic_vector(my_counter, 12);
counting := '0';
elsif counting='1' then
my_counter := my_counter + 1;
end if;
send_xx <= msgRcvd;
sw_linex <= msgRcvd;
end if;
end process;

end behavioral;

You didn't say whether the start or msgRcvd inputs were synchronous to
the clock or how wide they were. If not, then you need to add
synchronizing latches to the above circuit. The reset signal needs to
be synchronous to the clock also.

In a synchronous circuit, everything happens on a clock edge. You
shouldn't try to trigger on edges of any other signals. Think of these
other inputs as levels that are stable during the clock period and
change on the clock edge. If they aren't, then add synchronizing
latches to make it so.

Charles Bailey

 

[cristian]

ALuPin wrote:

That basically is just an ouptut that
is connected to the global reset signal. That is the way to activate
the reset after configuration.


Hi Cristian,

when simulating I can see in Modelsim that
the component gsr has only inputs:

Name Value Kind Mode
timingcheckson false Generic In
xon false Generic In
msgon false Generic In
instancepath gsr Generic In
gsr 1 Signal In

So how can I connect gsr to the global reset signal
if gsr is an input ?

Rgds
Andrés

Andres,
The GSR is a component that has an input: the signal that will be used
as global reset. You have to supply that input to the GSR component.
During power up all the components tied to that global reset signal
will be reset/set by the GSR component. The GSR component does not have
a 'visible' output signal, but it has one that set/reset all the FF
controled by the global reset signal.
When simulating your design the simulator should show the FF reset/set
after a short time if you are using the GSR component and before
activating your global reset signal.

rgds.

cristian

 

[Ulf Samuelsson]

roninn@gmail.com wrote:

I have an entity that has two std_logic_vectors as inputs (see below).
I want to make it so when I instantiate a component of this entity, it
will arrange itself in response to the width of the vectors it
receives as an inputs.

... snip ...

Thanks!

Do a generic declaration

entity SquareRoot is
generic (W : Integer := 16)
port(
A, B: in std_logic_vector(W-1 downto 0);
Cin: in std_logic;
Cout: out std_logic;
Sum: out std_logic_vector(W+W-1 down to 0)
);
end;

architecture behav of SquareRoot is

--removed component declarations
signal Plink, Glink, Slink0, Slink1: std_logic_vector(W-1 downto 0);
signal Clink0, Clink1: std_logic;

begin
pg: pAndG port map (A, B, Plink, Glink);
a0: sradderc0 port map (Plink, Glink, Clink0, Slink0);
a1: sradderc1 port map (Plink, Glink, Clink1, Slink1);
mx: mux port map (Cin, Slink0, Slink1 , Clink0, Clink1, Sum, Cout);
end;


--
Best Regards,
Ulf Samuelsson
ulf@a-t-m-e-l.com
This message is intended to be my own personal view and it
may or may not be shared by my employer Atmel Nordic AB

 

[info_]

Hi,

It makes me nervous to see "shared variables" in RTL code... As a newbie, you
probably shouldn't be aware of these beasts anyway ;-)
Shared vars can be very handy in test benches and behavioral models, but they must be
used with extreme care.
A constant would have done the trick.

Unconstrained arrays in port is IMO a very elegant style, but it doesn't
have only advantages... I'm not sure all the synthesis tool accept this yet either,
you need to check first before using this style ! Don't rely on manuals, they are
sometimes unaware of what the tool can do !!! Use the code below (wrap it in a
sized-ports top level first indeed) to see of it works.

So below is something which I wrote "similar" to your idea (though the function coded
has nothing to do with a square root. I think there is a synthesizable square root in
the Synplify examples, but if it's an assignment, write your own solution first).
You can throw this code in your VHDL simulator and see it work (PWM on Cout).

Hope this helps,
Bert
--
-- Using unconstrained array : simple example.
-- Bert Cuzeau.
--
-- Note though that unitary synthesis will require a wrapper...
-- so unconstrained arrays in ports, despite their "beauty"
-- is probably not the panacea. But it's elegant and highly reusable.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity pAndG is
port( A, B : in std_logic_vector;
Plink,
Glink : out std_logic_vector );
end pAndG;

architecture dummy of pAndG is
begin
-- just to put something here for the sake of the example
Plink <= A and B;
Glink <= A xor B;
end;
-- we ae going to instanciate this entity.

-- ----------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity SquareRoot is
port( A, B : in std_logic_vector;
Cin : in std_logic;
Cout : out std_logic;
Sum : out std_logic_vector );
end SquareRoot;

library IEEE;
use IEEE.numeric_std.all;

architecture Dummy of SquareRoot is -- just for the example !
-- this does nothing interesting, the purpose is only to show how
-- to use unconstrained array and attributes.

constant Width : positive := A'length; -- if you want to use it.

signal Plink, Glink, Slink0, Slink1: std_logic_vector(A'range);
signal Clink0, Clink1: std_logic;
signal Sum1 : std_logic_vector (A'high+1 downto 0);

begin
-- shows the instanciation of another entity with unconstrained vectors in port
pg: entity work.pAndG(Dummy) port map (A, B, Plink, Glink); --

Sum1 <= std_logic_vector (unsigned('0'& A) + unsigned('0'& B));
Sum <= Sum1(Sum'range);
Cout <= Sum1(Sum1'high);
end;

-------simple test bench-----------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity TB is end;
architecture test of TB is
signal A,B,Sum : std_logic_vector(5 downto 0);
signal Cout : std_logic;
begin
UUT: entity work.SquareRoot port map (A,B,'0',Cout,Sum);
process begin
A <= (others=>'0'); B <= (others=>'0');
for i in 0 to 2**A'length-1 loop
for j in 0 to 2**A'length-1 loop
A <= std_logic_vector (to_unsigned(i,A'length));
B <= std_logic_vector (to_unsigned(j,B'length));
wait for 10 ns;
end loop;
end loop;
wait;
end process;
end test;
----------------------------------

 

[info_]

I'm not sure your understood that generic parameter wasn't the only solution.
You can create generic RTL code with unconstrained vectors, (and no generic
parameter) as shown in my example. You just need to use attributes as shown.


roninn@gmail.com wrote:

Hi Bert,

Thank you for the advice. To be honest, I only had shared variables
becuase a compilation error suggested it

I do not need to simulate this particular code, but in the future I
will take your advice and try it out on the Xilinx synthesizer I am to
use.

Thank again for your help.

 

[info_]

Did you simply try sample / 2 ????
If sample is signed or unsigned or integer range, it should work.
If not, simply do type conversions.

The "hardware orientated" guys (like me) would probably do a shift right...


genlock wrote:

I am trying to divide a 24 bit binary value by 2,4,8...for which I have
used the following syntax:

sample / "000000000000000000000010"

It keeps showing an error as follows :

/ can not have such operands in this context

Any suggestions welcome.

Thanks

 

[Brad Smallridge]

Can you give us a hint? If this is for a testbench then you
can easily do the division using varaibles. If this is hardware
then we need to know how fast and how big the vectors are.
Lookup tables are fast if the numbers are small.

 

[Brad Smallridge]

That's tough. More like microprocessor work than FPGA.
Can't help you but I do know that there is no / operator in
VHDL that will do it on "real" signals. I suggest you do a
Google search on Xilinx (or whatever you are using) and
division and see what pops up. Perhaps other people in this
comp.fpga group can be more help.

b r a d @ a i v i s i o n . c o m

 

[Hal Murray]

I am basically trying to divide a 24 bit vector by 1.36.(output result
eventually being a bit vector)

One trick is to multiply by the inverse.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Ralf Hildebrandt]

genlock wrote:

I am basically trying to divide a 24 bit vector by 1.36.(output result
eventually being a bit vector)

Don't divide by 1.36, but multiply by 1/1.36. Multiplication is much easier.

Am I right, that you have a constant factor? Then multiplication is very
easy. It becomes only a series of additions (and shifts).

The fractional number should not be used in floating point format but in
fixed point format with the accuracy you need. Remember that within some
bounds of accuracy a number can be given with:
2^n + ... + 2^1 + 2^0 + 2^(-1) + 2^(-2) + ... + 2^(-m)

Then your problem is nothing more than normal integer multiplication by
a constant value, which can be greatly optimized using even the normal
"*" Operator.

I am first converting this 24 bit vector to an integer.

No. A vector is much better (signed or unsigned is suitable). Extend
this vector by some zeros to the left to have a fractional part.
Use a constant with the same bitwidth (also signed or unsigned),
representing 1/1.36 with your desired accuracy using the above mentioned
fixed point scheme.



Addition: This multiplication will be represented by several additions.
Pipelining is possible, if needed for speed or lower area.

Ralf

 

[Jonathan Bromley]

On 29 Mar 2005 22:45:01 -0800, arul_enggus@yahoo.com wrote:

All strings can be displayed in the report message

report "Channel"&conv_string(J)&"failed"
severity note;

conv_string is not standard; it's nicer to use the built-in
function 'IMAGE that comes with every scalar data type:

report "channel " & integer'IMAGE(J) & " failed"
--
Jonathan Bromley, Consultant

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