Clock Edge notation

VHDL level simulation of JOP is now available ;-)

The actual version of JOP at the usual download page
http://www.jopdesign.com/download.jsp
now contains (hopefully) all necessary file to run a
simulation with ModelSim or a different VHDL
simulator.

A (very) simple step-by-step introduction can be found at:
http://www.jopdesign.com/simulation.jsp
Click to expand...
I've added a simulation version of the uart module (sim_uart.vhd)
to speed-up the simulation a little bit. It's too monotonous to watch
the simulation generating the output at 115kbaud ;-)

Martin
 
Andrés wrote:

ATTRIBUTE PINL OF Sdram_dq : SIGNAL IS "C17, D17, C16, D16, F17,
G17, F16, G16, C15, B16, C14, E14, D15, E15, F14, G14";

When compiling I get the following warning message:
Warning, attribute PINL given large bit vector width, potentially
unacceptable by place and route tools. Consider a string attribute
instead
Click to expand...
Consider commenting out all of the attributes from your vhdl sources.
Once you have an error-free synthesis, find the text file
with the pin assignments, and edit that.

-- Mike Treseler
 
Andres,

I think the problem is the 'PINL' string you are using.

Here is a pin assignment that works for me:

--The syntax of attribute LOC
--attribute LOC : string;
--attribute LOC of [SigName] : signal is "P[pin#]";

attribute LOC : string;
attribute LOC of in5 : signal is "W24";
attribute LOC of in8 : signal is "W22";
attribute LOC of in10 : signal is "A15";
attribute LOC of o : signal is "D19, A18, E18";

You can get information on this and other attributes in:
File->Open Example->CPLD-> Constraints or
File->Open Example->Lattice EC->Preferences_attributes

Regards,

cristian
 
Hartmut Reinke wrote:
Hans schrieb:

Hello Hartmut,

I would speak to CAST (http://www.cast-inc.com/) since I am pretty
sure they
can modify their 186 to an 8086 (just remove the 8259 PIC?). They
also have
a 187 core both are supplied by Evatronix so they should be able to
come up
with a nice solution, the price might be a different story :)

Hans
www.ht-lab.com


Thank you for that Information.
Meanwhile we know, we could even use the 80186 as it is (unneeded
peripherals, including the 8259 can be disabled without greater
problems), so we have some choice concerning the 8086, but there seems

to be no other source for a reasonable fpu except evatronix.
It seems to be good, but the price will surely be a great problem...
:-(

Hartmut
www.srel.de
Click to expand...
I'm a newbie, but it seems to be that if you need an 8086, would it
not make more sense to pick up one of the various low-power [345]86
chips out there, and use it? Why waste all that fpga/etc real-estate
on an 8086? :)

--

[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]s
alax
 
pflloyd wrote:
process(Reset, DataSentTouCAck, Latch_FMU_Bus)
variable temp : bit;
begin
if Reset = '1' then
temp := '0';
elsif DataSentTouCAck'event and DataSentTouCAck = '1' then
temp := '0';
elsif Latch_FMU_Bus = '1' then
temp := '1';
end if;
DataInLatchToFMUValid <= temp;
end process;

When I compile this I get the following error

Can't infer register for signal "temp" because signal does not hold
its
value outside clock edge

This process is just a D-FF with an asynchronous reset.
Click to expand...
Could you draw me a picture of what you're trying to build, because this
most certainly does not look like a D-FF. On the positive clock edge you
want temp to become 0, and if there's no clock edge you want it to
become 1
if latch_fmu_bus = 1. I can imagine that the compiler doesn't know what
to
build out of this.

Regards,

Pieter Hulshoff
 
cristian wrote:
Andres,

I think the problem is the 'PINL' string you are using.

Here is a pin assignment that works for me:

--The syntax of attribute LOC
--attribute LOC : string;
--attribute LOC of [SigName] : signal is "P[pin#]";

attribute LOC : string;
attribute LOC of in5 : signal is "W24";
attribute LOC of in8 : signal is "W22";
attribute LOC of in10 : signal is "A15";
attribute LOC of o : signal is "D19, A18, E18";

You can get information on this and other attributes in:
File->Open Example->CPLD-> Constraints or
File->Open Example->Lattice EC->Preferences_attributes

Regards,

cristian

Did you try that with the EC/ECP family?
Click to expand...
When using LOC instead of PINL I still get the warning.

Rgds
Andrés
 
Andres,

I am targeting the same part that you use and using 4.2 as well (have
you installed SP1 yet? ). I've increased the bus width to 32 and other
one to 16 and I do not have any problem assingning the pins with the
above attribute.
One point I discovered is that you have to declare the pin # all in the
same line. Do not use enter (< > ) to make the code more readable.
If still having problems, follow what Mike mentioned, until finding the
line generating the warning and work on that particular pin assignment.
After trying that and still with warnings, you should call your local
FAE to find out the source of the warnings.

regards,

cristian
 
cristian wrote:

One point I discovered is that you have to declare the pin # all in
the same line. Do not use enter (< > ) to make the code more readable.
Click to expand...
It's a string. Try the "&"-function instead.


Vinzent.

--
worst case: The wrong assumption there actually is one.
 
Andres,

It looks like you have SP1 installed. For future updates you can use
the ispUPDATE utility available from: Start->Programs->Lattice
Semiconductor-> ispUPDATE

Regarding the RESET and the WATCHDOG, well that is up to you. Of course
you can implement that configuration when using the EC/ECP. I see no
issue at all.
In the EC/ECP family any I/O pin can be the Global Asynchronous
Reset/Set (GSRN, active low) . Take a look at TN1008 page 14-13.

rgds,

cristian
 
"funcheung" <funcheung@ustc.edu> wrote in message news:<e381c68d6ec0f7894e69a6ec530a7934@localhost.talkaboutprogramming.com>...
I have met the same problem, I dont have any solution
Click to expand...
Have you 2 tried communicating this to Altera Support? If so, what did
they say? They are usually pretty good at answering support questions.
Personally I never had this problem.

- Paulo Valentim
 
Hi FPGA people,

I am trying to map my VHDL design on a Lattice-EC FPGA. (LFEC20E-5F672CES)

The following error warning occurs:

*********************************
Map checkpoint failed.
Design's logic delay (97 percent of total delay)
exceeds the 60 percent limit set in the map checkpoint options
*********************************
Process Stopped.

Done: failed with exit code: 0001.


Unfortunately there is no direct "double click" HELP for this error
message and I could not find any hint in the HELP menu.

Has someone of you any idea what this message could mean ?


Thank you in advance.

Rgds
Andrés
 
Tim Hubberstey <bogus@bogusname.com> wrote in message news:<QKpTd.4412$TB.398@edtnps84>...
In my experience, most synthesizers do not support positional
association for instantiations. Try using named association
(portname->signalname;) in your portmap. It is also MUCH easier to read
when you're debugging.
Click to expand...
I already tried and it doesn't make any difference. Positional
association is supported because I used it for another component and
it worked perfectly.

Thx anyway Tim,

Vince
 
Andres,

It looks confused to me as well, but again any I/O pin can be used as
GSRN.

On the other question, if you see the example on page 14.14 it
instantiates the GSR component. That basically is just an ouptut that
is connected to the global reset signal. That is the way to activate
the reset after configuration.

rgds,

cristian
 
Andres,

The ispLEVER software has an option that allow you to stop/continue
witht the map process depending on the porcentage of the delay that you
set.
That is, if you go to Tools-> Timing Checkpoint Options, the Timing
Checkpoint Options window will come up. There you can set the Estimated
Logic Delay that you will allow and then you have to tell the tool
whether to Stop or Continue when that number is violated. The 'Before
Route' is related to the Map process.

rgds

cristian
 
"Takuon Soho" <Tak@somwhere.net> wrote in message
news:_EdVd.9027$MY6.1221@newsread1.news.pas.earthlink.net...
I have learned how to set up a process
properly with clk and reset signals so that it will
synthesize properly without getting the dreaded
"bad synchronous description" error.

But here I have 3 signals - a clk (of course),
a start signal, and a MessageRcvd signal.

I am supposed to accumulate a count
by adding 1 to a counter
only after getting a "Start" signal (hi).

Whenever the "MsgRcvd" signal goes
hi, I must output the count and clear the counter.

Whatever I try keeps running into the "bad synchrnous"
problem.

Question: Should I break this into two seperate processes
or is it doable in 1?? Can 2 processes have a common
variable (the counter?)

I was going to try to re-write it as a state machine

Here is one thing I tried (clearly wrong because
sw_linexx and send_xx are set low by
1 clock signal and set high by another).

Thanks for any suggestions.
Tak (VHDL newbie, obviously).


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.all;

entity count12 is port (
clk: in std_logic;
start: in std_logic
msgRcvd: in std_logic;
sw_linex: out std_logic;
send_xx: out std_logic := '0';
bus_0_11: out std_logic_vector(11 downto 0);
);
end count12;

architecture behavioral of count12 is
begin


process(clk,start,msgRcvd)

subtype counter_ty is integer range 0 to 4095;
variable my_counter : counter_ty := 0;
variable msgFlag :integer := 0; --make it a boolean flag later

begin

if (rising_edge(start)) then
msgFlag := 1;
end if;

if (rising_edge(clk) and msgFlag = 1) then
sw_linex <= '0';
send_xx <= '0';
my_counter := my_counter + 1;
elsif
(rising_edge(msgRcvd)) then
send_xx <= '1';
sw_linex <= '1';
msgFlag := 0;
bus_0_11 <= conv_std_logic_vector(my_counter, 12);
end if;

end process;

end behavioral;


The rising_edge with different signal names (clk and msgRcvd) is not
Click to expand...
(mostly) supported by synthesis tools.
The synchronous frame work you learned was probably something like:

process(reset,clk)
begin
if reset='1' then
-- here the reset stuff
elsif rising_edge(clk) then
-- here the synchronous logic.
-- no rising_edge, falling_edge or 'event
end if;
end process;

Whenever the "MsgRcvd" signal goes hi
How long is this signal at least high?
Click to expand...
If it is at least one clock period high you could load the signal in a
flipflop ("MsgRcvdPrev").
If MsgRcvdPrev='0' and MsgRcvd='1' then "increment counter"
(Note: probably you need also 1 or 2 flipflops for synchonization?)

In case your MsgRcvd is short high, compared to the clock period, you could
model an SR latch. Set the latch with the MsgRcvd and reset the latch from
your synchronous description. (You can not detect two or more short high
pulses within one clock period).

Egbert Molenkamp
 
That basically is just an ouptut that
is connected to the global reset signal. That is the way to activate
the reset after configuration.
Click to expand...

Hi Cristian,

when simulating I can see in Modelsim that
the component gsr has only inputs:

Name Value Kind Mode
timingcheckson false Generic In
xon false Generic In
msgon false Generic In
instancepath gsr Generic In
gsr 1 Signal In

So how can I connect gsr to the global reset signal
if gsr is an input ?

Rgds
Andrés
 
colin wrote:


Obviously I want the case statement to be able to read an unknown
number of registers.
Click to expand...

constant reg_number : integer := 8;
constant reg_size : integer := 16;
signal register_1D_array : std_ulogic_vector(number*reg_size-1 downto 0);

-> 8 registers with 16 bit datawidth each.
Reading the registers is easy (reg_addr selects which one):

data_out <= register_1D_array((reg_addr+1)*reg_size-1 downto reg_addr*reg_size);

If your synthesis tool gets stuck with this description of a mux, take a for-loop:

for N in 0 to reg_size-1 loop
data_out(N) <= register_1D_array(reg_addr*reg_size+N);
end loop;


A similar solution is possible with a 2D array, which may be more human-readable, but may
make trouble with some older synthesis tools (or if you ever want to convert your code to
Verilog ;-)).

Ralf
 
"KCL" <kclo4_NO_SPAM_@free.fr> wrote in message
news:422626f5$0$11713$8fcfb975@news.wanadoo.fr...
Hi

Is it possible to declare a std_logic_vector of size that is log2(A) with
A a generic??
I was thinking of doing something like a range signal but doesn't work,
does anyoneone have any idea without using integer/natural signal??

Thanks

Alexis


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.NUMERIC_STD.all;

entity ztest is
generic(
A : integer :=132
);
port(
rst : in std_logic;
clk : in std_logic;
data_out : out std_logic_vector( range A downto 0 )
);
end ztest;
Click to expand...
Place the following functions in a package, say 'support' and it will work.
data_out : out std_logic_vector( log2(A) .... )

The solution with the WHILE is general solution. Most of the synthesis tools
I used supported that.
The solution with the for loop is not that nice but more synthesis tools
support that in stead of the WHILE solution.
Notice that the log2 checks if N is a power of 2 and ceil_log2 returns the
'round up' value.

Egbert Molenkamp

function log2 (N : positive) return natural is -- N should be power of
two.
variable res : integer;
begin
res := ceil_log2(N);
assert 2**res=N report "N is not a power of 2" severity note;
return res;
end log2;

-- function ceil_log2 (N : positive) return natural is
-- variable tmp, res : integer;
-- begin
-- tmp:=1 ; res:=0;
-- while tmp < N loop
-- tmp:=tmp*2;
-- res:=res+1;
-- end loop;
-- return res;
-- end ceil_log2;

-- *SDC: This version of ceil_log2 uses a for loop instead of a while loop
function ceil_log2 (N : positive) return natural is
variable tmp, res : integer;
variable out_of_range : boolean;
begin
tmp:=1 ; res:=0;
out_of_range:=true;
for i in 0 to 10 loop
if tmp < N then
tmp:=tmp*2;
else
res:=i;
out_of_range:=false;
exit;
end if;
end loop;
assert not out_of_range report "increase upper bound of for loop in
function ceil_log2 (package <the package name>)" severity error;
return res;
end ceil_log2;
 
well, here is two boxes of 8registers with 9 bits each which can be
read and written into.
----CODE------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity xyz is
port(
clk: in std_logic;
din: in std_logic_vector(8 downto 0);
add: in std_logic_vector(3 downto 0);
rdwr: in std_logic;
do : inout std_logic_vector(8 downto 0)
);
end entity;

architecture acrh_xyz of xyz is
type tag_array1 is array (0 to 7) of std_logic_vector(8 downto 0);
type tag_array2 is array (0 to 7) of std_logic_vector(8 downto 0);

signal tag1: tag_array1;
signal tag2: tag_array2;
begin

--reading
do <= tag1(conv_integer(add(2 downto 0))) when (add(3) = '0' and rdwr =
'0') else
tag2(conv_integer(add(2 downto 0))) when (add(3) = '1' and rdwr =
'0') else
(others => 'Z');

--writing
process(clk)
begin
if(clk'event and clk= '1') then
if(rdwr = '1') then
if(add(3) = '0') then
tag1(conv_integer(add(2 downto 0))) <= do;
else
tag2(conv_integer(add(2 downto 0))) <= do;
end if;
end if;
end if;
end process;

end acrh_xyz;
 
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