Clock Edge notation

[SneakerNet]

Hi Mike..

I would like to point out that this is a receiver module (Rx) so what I
wrote was correct. It is Data_FromPc[7..0] as it is a uart module that
receives data from PC and sends it to other modules within FPGA. I don't
know how you got the idea that it is Data_To_PC!.

Anyway I have no idea what your reply means. Can you pls be more clear in
this area.

Cheers


"Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message
news:3F33DAAC.2050205@flukenetworks.com...

SneakerNet wrote:

The receive module of the uart has these I/Os:
clock: input
baudclock: input
RxD: input
Data_FromPC[7..0]: output



That would be Data_To_PC




RxComplete: output

The I/O's are self-explanatory.
Now how can i use the RxComplete signal to implement the buffer? Help.
Any
info/advice appreciated.




1 8 8
RxD]---[UART]---/--[FIFO]--/---[Data_To_PC



-- Mike Treseler

 

[VhdlCohen]

Does anyone know of a windows version vhdl documentation program that
converts vhdl code into html pages? Something similar to vhdldoc

Thanks
Sanjay

lookup in google "htmlize.el"
That works under emacs.
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

 

[Pieter Hulshoff]

Hello Sarah,

So, i need to keep the signal : start_tx longer until the rising endge of
Uart_clcok.
Does anyboday know how to slove this problem? Which logic should be
used?

It's a 3 step approach:

1. Stretch the start_tx signal such that it is longer than the clock pulse
of the UART clock including clock skew. A simple counter to turn the
start_tx signal on and off should do the trick. It's no problem if the
start_tx pulse is a bit longer than it needs to be. Too short however will
cause problems.
2. Clock the start_tx to the UART clock using 3 FFs to avoid meta-stability.
3. Perform a positive edge detection on the output of the 2nd and 3rd FF
using the UART clock.


For step 2 and 3:

PROCESS
BEGIN
WAIT UNTIL uart_clk = '1';
uart_start_tx <= start_tx; -- 1st FF
uart_start_tx_1d <= uart_start_tx; -- 2nd FF
uart_start_tx_2d <= uart_start_tx_1d; -- 3rd FF
-- rising edge detection
IF uart_start_tx_1d = '1' AND uart_start_tx_2d = '0' THEN
-- start your transmission here
END IF;
END PROCESS;


Hope this helps,

Pieter Hulshoff

 

[Chris Pruett]

Sarah,

You need to generate a signal from the 10 MHz domain that is long
enough for the logic in the uart clock domain to capture. A rule of
thumb for two totally asynchronous clocks is that it must be at least
two of the destination clock cycles in length. What you do then is
synchronize the signal in the target clock domain and then edge-detect.
The edge-detection pulse is the signal to the UART to start.

A possible implementation:

process (clk_10, reset_10) is
begin
if (reset_10 = '1') then
toggle <= '0';
elseif (clk_10'event and clk_10='1') then
if (start_tx = '1') then
toggle <= not toggle;
end if;
end process;


process (clk_uart, reset_uart) is
begin
if (reset_uart = '1') then
toggle_meta <= '0';
toggle_sync <= '0';
toggle_delay <= '0';
uart_start_tx <= '0';
elseif (clk_uart'event and clk_uart='1') then
toggle_meta <= toggle; -- metastable
toggle_sync <= toggle_meta; -- synchronized
toggle_delay <= toggle_sync; -- delayed
uart_start_tx <= toggle_sync xor toggle_delay; -- edge
end if;
end process;

Then uart_start_tx can be used by the UART logic.

CP


In article <d51c0c2.0308130712.349bcb47@posting.google.com>, sarah
<sarahshen2003@yahoo.ca> wrote:

Hi,

I have a clock problem when implementing reading and wrting data from
ram in FPGA.

First, write data to ram. The write clock is 10 Mhz. Then after
finishing writing, read data from ram and send them to UART. The
problem is here, the reading clock is the same as UART_clock, much
slower than 10 Mhz. In the UART, the transmitter block is controlled
by the signal: start_tx. It means when start_Tx is '1', the data can
be trasmitted. But this signal is triggered by the high speed clock,
10 mhz. The transmitter block can work under the uart-clock. So, i
need to keep the signal : start_tx longer until the rising endge of
Uart_clcok.

Does anyboday know how to slove this problem? Which logic should be
used?

Thank you very much.

sarah

 

[Mike Treseler]

Jerker Hammarberg (DST) wrote:

I put together a generic floating point package that performs addition,
subtraction, multiplication and comparison. Contrary fphdl
(www.eda.org/fphdl), it is synthesizable with Xilinx XST - that's why
I made my own. Anyway, I present it here in the hope that anyone may
wants to look through it for
* possible optimizations, particularly for implementation size,
* language misuse or simplifications,
* bugs,
* or actually, any possible improvements.

Consider:

1. A simple testbench with an assertion for each function.
2. numeric_std:

-- use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

m := "01" & shift_left((m(size-3 downto 0))
to_integer(to_unsigned(leftshift,EXPSIZE)));

-- m := "01" & shl(m(size-3 downto 0),
-- conv_unsigned(leftshift, EXPSIZE));

-- rsres := shr(rsarg1, rsarg2);
rsres := shift_right(rsarg1, to_integer(rsarg2));

-- return conv_std_logic_vector(result, TOTALSIZE);
return std_logic_vector(result);


-- return conv_std_logic_vector(result, TOTALSIZE);
return std_logic_vector(result);



-- Mike Treseler

 

[Mike Treseler]

missed a comma \

m := "01" & shift_left((m(size-3 downto 0)) ,
to_integer(to_unsigned(leftshift,EXPSIZE))) ;

-- Mike Treseler

 

[Pieter Hulshoff]

Please, can anybody tell me why do I get e as a complement of a when I
simulate this examle in Aldec's AHDL with waveform?

The complement is caused because your process is only called once on a
change of a, causing e to always lag one change behind a. I don't know
exactly what this design is supposed to do, but if you wish to just connect
a to e, why not settle for e <= a? If you insist on using connect, then at
least place it in the sensitivity list or in the wait on list:

barrel: PROCESS (a, e) IS
BEGIN
connect <= a;
e <= connect;
END PROCESS barrel;

or

barrel: PROCESS IS
BEGIN
connect <= a;
e <= connect;
WAIT ON a, connect;
END PROCESS barrel;

Regards,

Pieter Hulshoff

 

[VhdlCohen]

Sounds like you would be much happier if you had a context-sensitive editor
with VHDL keyword help. I use prism. There are probably others to choose
from.
http://www.iol.ie/~dmurray/Prism/Prism_Editor.html

Agreed about LSE, but emacs is my favorite.
Ben

 

[Tim Hubberstey]

"Jerker Hammarberg (DST)" wrote:

2. numeric_std:

This is interesting... what is the difference between numeric_std and
std_logic_arith? I can see the former is slightly more readable. Is it also
more efficient?

I don't know for sure about efficiency but I doubt there is any
appreciable difference since efficiency is determined primarily by the
tool, not the package, unless you have optimization turned off.

The most important difference is that numeric_std is an IEEE standard
while std_logic_arith actually has several different (and incompatible)
versions, depending on whose tool you're using. If you want your code to
be portable, use numeric_std.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

[Jonathan Bromley]

"William Wallace" <msm30@yahoo.com> wrote in message
news:7e4865b7.0308162039.62aaac2f@posting.google.com...

1. Is there a general rule I can use to know when I need to use the
word "is" and when I do not? Also, what good does making somebody
type these two characters do?

It means, for example, that the syntax doesn't need parentheses
around the selector of a "case" statement, because "is" acts as
a separator between the selector and the rest of the statement.

2. Is there a general rule I can use to figure out when two words are
combined into one word (e.g., "elsif") versus being kept as two words
(e.g., "end if")?

Yup. The only such elision in VHDL is "elsif" (a slightly mysterious
spelling; "elif" or "elseif" would perhaps have made more sense).
Contrast with Verilog's absurd statement bracketing syntax, with
the huge collection of elided terminators (endmodule, endcase,
endgenerate... and a scad more of them in SystemVerilog) and
interminable repetition of "begin...end".

3. Is there a general rule I can use to figure out when I need to put
a semicolon (e.g., after the generic section and also the port section
in the component declaration) and when I do not (e.g., not after the
generic section but only after a port section of an instantiation)?

I agree this is fidgety syntax. Semicolon acts as:

- a statement TERMINATOR (one after every statement or declaration)
- a list SEPARATOR (one after every port specification in an
entity, except after the last one)

The second of these is likely to be regularised in VHDL-200x,
so that you can use semicolon at the very end of a port list if
you wish.

As for the instantiation syntax, surely it makes sense that
the port and generic lists of an entity are quite separate
things, but the port and entity bindings on an instance
are part of the same statement?

4. Why if I pass a argument, say a std_logic_vector, to a function
that takes a std_logic_vector, do I need to use data_in(arg'low) in
the function as opposed to data_in(0). Why doesn't VHDL automatically
rejustify a function call, say, function(data(15 downto 8)) to
data_in(7 downto 0) in the function automatically?

So you can find out what you were given. If you want to renormalise
the input vector, you can easily do that using alias, constant or
a variable:

function f (a: in std_logic_vector) return stuff is
constant norm_a: std_logic_vector(a'LENGTH-1 downto 0) := a;
begin
...

This is one of several areas where VHDL has immense superiority
over Verilog. See my recently posted fixed-point arithmetic
package for a more extended example.

5. Is there a better way to bit reverse a bus than "new_bus(7 downto
0) <= old_bus(0) & old_bus(1) & ... & old_bus (7);", which gives my
hands cramps for large busses.

Yup; use a for loop or a generate loop, depending on the situation.
Unlike Verilog, you can do it in a completely general way, thanks to
exactly the thing you were complaining about with the function
arguments. (Needs VHDL-93 for the "reverse_range" attribute;
without that, a bit more work is required but it's still easy.)
There is an appealing recursive formulation too, also impossible
in Verilog, but this version is more practical.

function reverse_any_bus (a: in std_logic_vector)
return std_logic_vector is
variable result: std_logic_vector(a'RANGE);
alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
begin
for i in aa'RANGE loop
result(i) := aa(i);
end loop;
return result;
end; -- function reverse_any_bus

Show me how to do that in Verilog

6. What advantage is there in not allowing an port output to not be
used on the rhs of an assignment in a module, forcing the RTL authors
to create internal versions of such signals (e.g., "signal oData_v
std_logic_vector(3 downto 0);") and later doing an assignment such as
"oData <= oData_v;"?

It gives better consistency between entities and subprograms, but
I agree that it's a bit of a nuisance. On the other hand, creating
an internal signal is hardly a five-star headache.

I have actually seen RTL code from VHDL
engineers who did not know Verilog come up with even more ludicrous
ways of solving this problem (routing an output back into a module as
an input for use on the RHS of assigments inside the module).

There are people writing execrably bad VHDL, just as there are people
writing execrably bad Verilog. That's life.

I have concluded that the people who came up with VHDL syntax were not
working with each other, not referring back to previous decisions they
made when making new ones,

Hmm. Maybe that's why the VHDL LRM is half the thickness of the Verilog
LRM, but is considerably more precise and consistent.

and/or took the concept of "strongly typed"
to a ludicrous extreme.

You mean, like, they chose to USE that concept? There's plenty that
needs fixing about VHDL, but very little of it is stuff that the
Verilog camp are likely to be able to teach us!

It is also my belief that if it weren't for the government mandate,
and the hordes of VHDL-only engineers these mandates created (VHDL
fanatics who refuse to learn a better HDL), VHDL would be dead.

Believe away. You have many supporters.

Any VHDL apologists care to explain?

I prefer to think of myself as an "HDL apologist", as someone who's
been using both Verilog and VHDL for a decade and who is very aware
that both have their considerable strengths and weaknesses.
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Egbert Molenkamp]

"William Wallace" <msm30@yahoo.com> wrote in message
news:7e4865b7.0308162039.62aaac2f@posting.google.com...

1. Is there a general rule I can use to know when I need to use the
word "is" and when I do not? Also, what good does making somebody
type these two characters do?

The syntax of VHDL is more or less based on ADA. The 'is' occurs also
in ADA (I think).
In the first VHDL standard (from 1987) the usage of 'is' is not consequent.
E.g. ENTITY name IS
but not
COMPONENT name .. and NOT followed with 'is'

From 1993 the syntax is more regular. At the places you (may) expect an
'is' is allowed ('allowed' to be compatbile with '87 description).
So nowadays you may also write:
COMPONENT name IS ..

Probably most of the tools support the '93 standard, there are of course
many books that use the '87 style.

What is the meaning of 'is' .. I think that it is only sugar (and probably
only
there because is was used in ADA?) But I'm not sure here.

2. Is there a general rule I can use to figure out when two words are
combined into one word (e.g., "elsif") versus being kept as two words
(e.g., "end if")?

IF cond1 THEN
...
ELSE IF condi2 THEN
..
END IF
END IF;

In the previous description "ELSE IF" can not be replaced with ELSIF.
In the previous description there are TWO IF-statements. Where the
ELSIF will result in ONE IF-statement. See next example (not the missing
END IF).


IF cond1 THEN
...
ELSIF condi2 THEN
..
END IF;

(probably ELSEIF is not nice so therefore ELSIF is used)

Furthermore END <..> is rather regular (also from VHD'93)
ENTITY .. END ENTITY
PROCESS .. END PROCESS
IF .. END IF;
CASE .. END CASE
BLOCK .. END BLOCK
etc.

3. Is there a general rule I can use to figure out when I need to put
a semicolon (e.g., after the generic section and also the port section
in the component declaration) and when I do not (e.g., not after the
generic section but only after a port section of an instantiation)?
I must confess. When I read the Peter Ashendens "The VHDL Cookbook"

(in 1990 or so) I send him an email because I though he made an
error with missing semicolums. I was wrong.

4. Why if I pass a argument, say a std_logic_vector, to a function
that takes a std_logic_vector, do I need to use data_in(arg'low) in
the function as opposed to data_in(0). Why doesn't VHDL automatically
rejustify a function call, say, function(data(15 downto 8)) to
data_in(7 downto 0) in the function automatically?

David Bishop had made a fixed point proposal. He modeled an
unsigned fixed point number as foolows:
variable nmbr : ufixed (1 downto -3)"
With the interpretation 2 position on the left (index 1 and 0 in array)
of the point and three on the right of the point (index -1, -2 and -3).

In his proposal he can manipulate different fixed point numbers.
In his case it is a benefit that the index is given to the function and
not 'normalized' losing the information where the point is. In the
latter case additional information would be needed (e.g. a record
structure?)

If you write a function and the index is to be normalized you can write
FUNCTION (a : IN bit_vector ...) IS
CONSTANT ai : bit_vector(a'LENGTH-1 DOWNTO 0) := a;
and use ai internally.

5. Is there a better way to bit reverse a bus than "new_bus(7 downto
0) <= old_bus(0) & old_bus(1) & ... & old_bus (7);", which gives my
hands cramps for large busses.

Yes, create only once a function (you see I also used the index alignment
here)

FUNCTION bitr (i : std_logic_vector) RETURN std_logic_vector IS
CONSTANT ii : std_logic_vector(i'LENGTH-1 DOWNTO 0) := i;
VARIABLE o : std_logic_vector(i'LENGTH-1 DOWNTO 0);
BEGIN
FOR j IN 0 TO ii'LENGTH-1 LOOP
o(j):=ii((ii'LENGTH-1)-j);
END LOOP;
RETURN o;
END bitr;

6. What advantage is there in not allowing an port output to not be
used on the rhs of an assignment in a module, forcing the RTL authors
to create internal versions of such signals (e.g., "signal oData_v
std_logic_vector(3 downto 0);") and later doing an assignment such as
"oData <= oData_v;"? I have actually seen RTL code from VHDL
engineers who did not know Verilog come up with even more ludicrous
ways of solving this problem (routing an output back into a module as
an input for use on the RHS of assigments inside the module).

Reading mode OUT internally is currently considered to be part of the
VHDL standard.

..

I have concluded that the people who came up with VHDL syntax were not
working with each other, not referring back to previous decisions they
made when making new ones, and/or took the concept of "strongly typed"
to a ludicrous extreme.
It is also my belief that if it weren't for the government mandate,
and the hordes of VHDL-only engineers these mandates created (VHDL
fanatics who refuse to learn a better HDL), VHDL would be dead.

I must agree the learning curve of VHDL is not easy.
But if you can 'play' with the language you can do nice things.

Egbert Molenkamp

 

[Willem Oosthuizen]

I fully agree with your sentiments.

Would it not be great if VHDL used curly brackets instead of begin...end
nonsense.

Maybe people should look at how C is structured. The designers of C new
something about engineers and computer people who prefer less words.

Also why doesn't VHDL support text-replacement macros, and conditional
signal declarations?

Why do some Synthesis tools generate ripple tree structure of things like
bit adders and gates, if fully synchronous designs are intended?

"William Wallace" <msm30@yahoo.com> wrote in message
news:7e4865b7.0308162039.62aaac2f@posting.google.com...

1. Is there a general rule I can use to know when I need to use the
word "is" and when I do not? Also, what good does making somebody
type these two characters do?
2. Is there a general rule I can use to figure out when two words are
combined into one word (e.g., "elsif") versus being kept as two words
(e.g., "end if")?
3. Is there a general rule I can use to figure out when I need to put
a semicolon (e.g., after the generic section and also the port section
in the component declaration) and when I do not (e.g., not after the
generic section but only after a port section of an instantiation)?
4. Why if I pass a argument, say a std_logic_vector, to a function
that takes a std_logic_vector, do I need to use data_in(arg'low) in
the function as opposed to data_in(0). Why doesn't VHDL automatically
rejustify a function call, say, function(data(15 downto 8)) to
data_in(7 downto 0) in the function automatically?
5. Is there a better way to bit reverse a bus than "new_bus(7 downto
0) <= old_bus(0) & old_bus(1) & ... & old_bus (7);", which gives my
hands cramps for large busses.
6. What advantage is there in not allowing an port output to not be
used on the rhs of an assignment in a module, forcing the RTL authors
to create internal versions of such signals (e.g., "signal oData_v
std_logic_vector(3 downto 0);") and later doing an assignment such as
"oData <= oData_v;"? I have actually seen RTL code from VHDL
engineers who did not know Verilog come up with even more ludicrous
ways of solving this problem (routing an output back into a module as
an input for use on the RHS of assigments inside the module).

I have concluded that the people who came up with VHDL syntax were not
working with each other, not referring back to previous decisions they
made when making new ones, and/or took the concept of "strongly typed"
to a ludicrous extreme.

It is also my belief that if it weren't for the government mandate,
and the hordes of VHDL-only engineers these mandates created (VHDL
fanatics who refuse to learn a better HDL), VHDL would be dead.

Any VHDL apologists care to explain?

Thanks

 

[Jonathan Bromley]

"William Wallace" <msm30@yahoo.com> wrote in message
news:7e4865b7.0308162039.62aaac2f@posting.google.com...

1. Is there a general rule I can use to know when I need to use the
word "is" and when I do not? Also, what good does making somebody
type these two characters do?

It means, for example, that the syntax doesn't need parentheses
around the selector of a "case" statement, because "is" acts as
a separator between the selector and the rest of the statement.

2. Is there a general rule I can use to figure out when two words are
combined into one word (e.g., "elsif") versus being kept as two words
(e.g., "end if")?

Yup. The only such elision in VHDL is "elsif" (a slightly mysterious
spelling; "elif" or "elseif" would perhaps have made more sense).
Contrast with Verilog's absurd statement bracketing syntax, with
the huge collection of elided terminators (endmodule, endcase,
endgenerate... and a scad more of them in SystemVerilog) and
interminable repetition of "begin...end".

3. Is there a general rule I can use to figure out when I need to put
a semicolon (e.g., after the generic section and also the port section
in the component declaration) and when I do not (e.g., not after the
generic section but only after a port section of an instantiation)?

I agree this is fidgety syntax. Semicolon acts as:

- a statement TERMINATOR (one after every statement or declaration)
- a list SEPARATOR (one after every port specification in an
entity, except after the last one)

The second of these is likely to be regularised in VHDL-200x,
so that you can use semicolon at the very end of a port list if
you wish.

As for the instantiation syntax, surely it makes sense that
the port and generic lists of an entity are quite separate
things, but the port and entity bindings on an instance
are part of the same statement?

4. Why if I pass a argument, say a std_logic_vector, to a function
that takes a std_logic_vector, do I need to use data_in(arg'low) in
the function as opposed to data_in(0). Why doesn't VHDL automatically
rejustify a function call, say, function(data(15 downto 8)) to
data_in(7 downto 0) in the function automatically?

So you can find out what you were given. If you want to renormalise
the input vector, you can easily do that using alias, constant or
a variable:

function f (a: in std_logic_vector) return stuff is
constant norm_a: std_logic_vector(a'LENGTH-1 downto 0) := a;
begin
...

This is one of several areas where VHDL has immense superiority
over Verilog. See my recently posted fixed-point arithmetic
package for a more extended example.

5. Is there a better way to bit reverse a bus than "new_bus(7 downto
0) <= old_bus(0) & old_bus(1) & ... & old_bus (7);", which gives my
hands cramps for large busses.

Yup; use a for loop or a generate loop, depending on the situation.
Unlike Verilog, you can do it in a completely general way, thanks to
exactly the thing you were complaining about with the function
arguments. (Needs VHDL-93 for the "reverse_range" attribute;
without that, a bit more work is required but it's still easy.)
There is an appealing recursive formulation too, also impossible
in Verilog, but this version is more practical.

function reverse_any_bus (a: in std_logic_vector)
return std_logic_vector is
variable result: std_logic_vector(a'RANGE);
alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
begin
for i in aa'RANGE loop
result(i) := aa(i);
end loop;
return result;
end; -- function reverse_any_bus

Show me how to do that in Verilog

6. What advantage is there in not allowing an port output to not be
used on the rhs of an assignment in a module, forcing the RTL authors
to create internal versions of such signals (e.g., "signal oData_v
std_logic_vector(3 downto 0);") and later doing an assignment such as
"oData <= oData_v;"?

It gives better consistency between entities and subprograms, but
I agree that it's a bit of a nuisance. On the other hand, creating
an internal signal is hardly a five-star headache.

I have actually seen RTL code from VHDL
engineers who did not know Verilog come up with even more ludicrous
ways of solving this problem (routing an output back into a module as
an input for use on the RHS of assigments inside the module).

There are people writing execrably bad VHDL, just as there are people
writing execrably bad Verilog. That's life.

I have concluded that the people who came up with VHDL syntax were not
working with each other, not referring back to previous decisions they
made when making new ones,

Hmm. Maybe that's why the VHDL LRM is half the thickness of the Verilog
LRM, but is considerably more precise and consistent.

and/or took the concept of "strongly typed"
to a ludicrous extreme.

You mean, like, they chose to USE that concept? There's plenty that
needs fixing about VHDL, but very little of it is stuff that the
Verilog camp are likely to be able to teach us!

It is also my belief that if it weren't for the government mandate,
and the hordes of VHDL-only engineers these mandates created (VHDL
fanatics who refuse to learn a better HDL), VHDL would be dead.

Believe away. You have many supporters.

Any VHDL apologists care to explain?

I prefer to think of myself as an "HDL apologist", as someone who's
been using both Verilog and VHDL for a decade and who is very aware
that both have their considerable strengths and weaknesses.
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Allan Herriman]

Jonathan Bromley wrote:

"itsme" <itsme@gmx.de> wrote in message
news:bi1rho$4k5$00$1@news.t-online.com...


I want to direct read a Picture from a BMP File in a VHDL testbench and
generate out of this some Stimulis for my video processing and store the
video output again in a BMP File.
Is there a library/Package?
As I know there is a TEXTIO package but there must be ASCII data to read.
How can a access raw File data?


In most simulators, and using VHDL-93, you can declare a FILE OF CHARACTER
which will allow you to read standard Unix or Windows byte-stream files.
READ(F, C); will read the next character into C; CHARACTER'POS(C) will
then return its byte value.

Note that this is not guaranteed to be portable across simulators,
but it works OK in my experience.

If using a simulator that supports Tcl/Tk, it might be possible to use
the Tcl/Tk Img package that can read an image file (.bmp, .gif, .jpg,
whatever) into a pixmap image type. This can then be fed pixel by pixel
into the testbench.
I think this may be easier than trying to decode (or generate) the
various file formats in VHDL.

http://aspn.activestate.com/ASPN/docs/ActiveTcl/ActiveTcl8.4.1.0-html/img/index.htm

Regards,
Allan.

 

[Allan Herriman]

Allan Herriman wrote:

Jonathan Bromley wrote:

"itsme" <itsme@gmx.de> wrote in message
news:bi1rho$4k5$00$1@news.t-online.com...


I want to direct read a Picture from a BMP File in a VHDL testbench and
generate out of this some Stimulis for my video processing and store the
video output again in a BMP File.
Is there a library/Package?
As I know there is a TEXTIO package but there must be ASCII data to
read.
How can a access raw File data?



In most simulators, and using VHDL-93, you can declare a FILE OF
CHARACTER
which will allow you to read standard Unix or Windows byte-stream files.
READ(F, C); will read the next character into C; CHARACTER'POS(C) will
then return its byte value.

Note that this is not guaranteed to be portable across simulators,
but it works OK in my experience.


If using a simulator that supports Tcl/Tk, it might be possible to use
the Tcl/Tk Img package that can read an image file (.bmp, .gif, .jpg,
whatever) into a pixmap image type. This can then be fed pixel by pixel
into the testbench.
I think this may be easier than trying to decode (or generate) the
various file formats in VHDL.

http://aspn.activestate.com/ASPN/docs/ActiveTcl/ActiveTcl8.4.1.0-html/img/index.htm

Better still, you can use Tk to display the "Before" and "After" images
directly from your simulator.

Allan.

 

[Martin Thompson]

"itsme" <itsme@gmx.de> writes:

Hi all,
I want to direct read a Picture from a BMP File in a VHDL testbench and
generate out of this some Stimulis for my video processing and store the
video output again in a BMP File.
Is there a library/Package?
As I know there is a TEXTIO package but there must be ASCII data to read.
How can a access raw File data?

Does it have to be a BMP - if you can convert them to PGM (portable
grey map ) or PPM (portable pixel map) you can read and write them
very easily with std VHDL. I even wrote a package to do it, but my
employer owns it unfortunately...

Read up on the formats here
http://netpbm.sourceforge.net/doc/ppm.html
http://netpbm.sourceforge.net/doc/pgm.html

HTH,
MArtin

--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

 

[Amontec Team, Laurent Gau]

itsme wrote:

Hi all,
I want to direct read a Picture from a BMP File in a VHDL testbench and
generate out of this some Stimulis for my video processing and store the
video output again in a BMP File.
Is there a library/Package?
As I know there is a TEXTIO package but there must be ASCII data to read.
How can a access raw File data?

thanks peter



Just translate your binary file to an ASCII file, with a simple parse

script.
But, if you are working on 1MB binary file, your ASCII will be about 8MB.
If that a trouble for your, translate your binary file to a ASCII
version HEX.
But, if you are working on 1MB binary file, your ASCII HEX will be about
2MB.

Laurent
www.amontec.com

 

[Mike Treseler]

itsme wrote:

I want to direct read a Picture from a BMP File in a VHDL testbench and
generate out of this some Stimulis for my video processing and store the
video output again in a BMP File.
Is there a library/Package?
As I know there is a TEXTIO package but there must be ASCII data to read.
How can a access raw File data?

Consider using a hexdump utility like xxd
to convert the file to text, and then a
script or macro to convert the text to an
array of vhdl constants.

see also:
http://groups.google.com/groups?q=file+vhdl+records+my_type


-- Mike Treseler

 

[William Wallace]

A few responses to "Jonathan Bromley" <jonathan.bromley@doulos.com>

function reverse_any_bus (a: in std_logic_vector)
return std_logic_vector is
variable result: std_logic_vector(a'RANGE);
alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
begin
for i in aa'RANGE loop
result(i) := aa(i);
end loop;
return result;
end; -- function reverse_any_bus

Show me how to do that in Verilog

It's a trick. But is it really better than:

`define BITS_n 8
data_out[`BITS_n -1:0] <= data_in[0:`BITS_n:0];

Show me how to do that in VHDL, please! It is much more readable,
understandable, and concise than the 11 lines necessary to do the
same thing with your function.

6. What advantage is there in not allowing an port output to not be
used on the rhs of an assignment in a module, forcing the RTL authors
to create internal versions of such signals (e.g., "signal oData_v
std_logic_vector(3 downto 0);") and later doing an assignment such as
"oData <= oData_v;"?

It gives better consistency between entities and subprograms, but
I agree that it's a bit of a nuisance. On the other hand, creating
an internal signal is hardly a five-star headache.

It is non-obvious and a major nuisance if you have not seen the
workaround before. Many an engineer who has self-taught himself
many other languages will bang his head for a few hours figuring
this VHDLism out. Once you learn the workaround, it's not a big
deal, I suppose.

There are people writing execrably bad VHDL, just as there are people
writing execrably bad Verilog. That's life.

In my experience, a much larger percentage of VHDL designers write
bad code. Just my observation.

and/or took the concept of "strongly typed"
to a ludicrous extreme.

You mean, like, they chose to USE that concept? There's plenty that
needs fixing about VHDL, but very little of it is stuff that the
Verilog camp are likely to be able to teach us!

You act as though being strongly typed is a good thing. I'll take
C over ADA any day, and I'll take Verilog over VHDL as well.

Take two advanced designers with similar design philosophies (code,
test modules exhaustively, or if that is not feasible, identify and
test corner cases, then test the whole system), and strip the
advanced VHDL designer of all of his hack functions he relies
on, and put him head to head against an experienced Verilog
designer similarly stripped of stuff he routinely re-uses,
give them the same design specification, and I firmly believe
that the Verilog designer will get it done, simulated, verified,
and synthesized while the VHDL designer is still trying to
re-create VHDL crutches he has long forgotten were not part
of the language (e.g., support functions). Take two new users,
and the new VHDL designer will barely have time to test at all
by the time the market window closes.

VHDL has unnecessary overhead, and overhead costs money and time
to market. Which is probably why, in my experience, and in the
absence of a government mandate, Verilog is used the vast majority
of the time.

 

[Renaud Pacalet]

reg [`BITS_n -1:0]William Wallace wrote:

A few responses to "Jonathan Bromley" <jonathan.bromley@doulos.com


function reverse_any_bus (a: in std_logic_vector)
return std_logic_vector is
variable result: std_logic_vector(a'RANGE);
alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
begin
for i in aa'RANGE loop
result(i) := aa(i);
end loop;
return result;
end; -- function reverse_any_bus

Show me how to do that in Verilog


It's a trick. But is it really better than:

`define BITS_n 8
data_out[`BITS_n -1:0] <= data_in[0:`BITS_n:0];

Show me how to do that in VHDL, please! It is much more readable,
understandable, and concise than the 11 lines necessary to do the
same thing with your function.

To complete Jonathan's answer I'll say that reversing the bits has two
different possible meanings. Let's take an 8 bits vector:

variable A: BIT_VECTOR(7 downto 0); -- VHDL

reg [7:0] A; // Verilog

The MSB (leftmost) bit is indexed 7 and the LSB (rightmost) is indexed 0.

You may want another representation of the same data where the MSB is
indexed 1 and the LSB 8. In VHDL, as in Verilog, it's very easy:

variable B: BIT_VECTOR(1 to 8); -- VHDL
B := A;

reg [1:8] B; // Verilog
B = A;

But you may also want to modify the data by having the MSB becoming the
LSB and the LSB becoming the MSB. In VHDL it's a bit more difficult and
you need a for loop. As Jonathan explained VHDL attributes may be
helpfull. I thought it was the same in Verilog, without the help of
attributes. Your solution is interesting. I didn't know this syntax.
Neither did my version of Modelsim. Could you explain where it comes
from and what are the associated semantics?

Regards,
--
Renaud Pacalet, ENST, 46 rue Barrault 75634 Paris Cedex 13
###### Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 ######
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