Clock Edge notation

[Willem Oosthuizen]

"Allan Herriman" <allan_herriman.hates.spam@agilent.com> wrote in message
news:6v72iv4lq9bjr0mp5chfcgifefhgqt6pca@4ax.com...

On Fri, 25 Jul 2003 13:37:52 +0200, "Willem Oosthuizen"
willy@asic.co.za> wrote:

Hi,

I there a place where handy VHDL functions/procedures can be posted
/retrieved on the web? The more code I write, the more handy functions I
develop.
It would be nice to be able to share these. I am not talking about VHDL
RTL
source code, but more of packages. Functions like Random,
Integer_fit_Bits
etc.

"Random" is in the package ieee.math_real that is probably already
available in your simulator.

It has this prototype:
procedure UNIFORM (variable Seed1,Seed2:inout integer; variable
Xut real);


Integer_fit_Bits presumably is the same as the various log2 functions
that have been posted in this newsgroup many times.


What other handy functions do you have?

Bye,
Allan.

My point was that I am looking for something like www.openfunctions.org.
doing the same for functions as www.opencore.org does for rtl code.

 

[Rain Adelbert]

I think this is absolutely fine. You get the divided clock out from
flip-flop and it should be clean.
The other thing is, thechnology specific, if your flip-flop is strong enough
to drive the clock line. Normally the synthesis tool solves this for you,
otherwise insert a clock buffer.

Rain


"Matt Gessner" <mgessner@yahoo.com> wrote in message
news:909a6ea3.0307211437.1f27387@posting.google.com...

Hi, all,

I have a question about whether the following is a) synchronous (I believe
it is) and b) advisable:

signal counter: std_logic_vector (4 downto 0);
signal clk: std_logic;
signal cclk: std_logic;

processa: process (clk) is
begin
if rising_edge (clk) then
counter <= counter + 1;
end if;
end process;

cclk <= counter (4);

processb: process (cclk) is
begin
if rising_edge (cclk) then
null; -- do something interesting
end if;
end process;

Part of me screams "No, don't do it!" because I'm making a clock
out of something that's not //really// a clock. Is this is a problem?

Essentially, I'm scaling clk down by 8. In general, is this the
way to do this? Is there something more advisable?

I look forward to your insights.

Thanks -- Matt

 

[Paul Leventis]

Hi Jason,

First off, that's a pretty cool little algorithm... had to prove to myself
that it worked. Let digit = 5 + n, where n = 0..4. We want new_digit =
(digit * 2 + shift_in) % 10 = (5 * 2 + n * 2 + shift_in) % 10 = n * 2 +
shift_in. If we add three, and wrap around at 16 (since 4-bit
representation) then we get ((8 + n) * 2 + shift_in) % 16 = 2 * n +
shift_in.

I'm not sure that I've found the problem with your code, but there were a
number of stylistic issues and one suspicious fragment I figured I'd point
out. I'll add a caveat that I haven't really coded up any VHDL in a year or
so, and prior to that my experience was mostly with structural VHDL. And I
didn't have a compiler handy to try out my ideas. So I imagine I'll find
out I'm wrong and learn something in the process!

(0) I think the first problem is a lack of comments... uncommented code is
always wrong

(1) Process #3. I hate variables. Especially variables mixed with
signals... you must be very disciplined when using variables (I only use
them in for loops...). So I honestly don't know what the code will
translate into, as you are assigning a value to variable, then assigning to
the variable to a signal, then changing the value of the variable. I'm not
sure if the scheduled signal assignment occurs before or after the change in
variable value. Also, I'm not sure that the variable turns into a register
(i.e. has memory) -- either way though, it's not what you want. If it does
become a register, then have 2 24-bit registers (unnecsessary/may not work).
If you don't, then I don't know what will happen. Regardless, I think you
want to first be adding three, THEN shifting. There are two ways I can
think of restructuring this code into something that may work (see below).
The first replaces your variable with a signal that is computed
combinationally outside of the process. The second is an attempt to still
use a variable, based on my limited understanding of this VHDL construct.
Note that neither requires the asynchronous condition (though I'm thinking
it may need an aclr for bcd_out_s...).

if clk = '1' and clk'event then
if load_data = '1' then
bcd_out_s <= (OTHERS => '0');
elsif shift_en_s = '1' then
bcd_out_s <= bcd_out_modified_s(22 downto 0) & ser_out_s;
end if;
end if;
...
bcd_out_modified_s(3 downto 0) <= bcd_out_s(3 downto 0) + "0011" when
bcd_value(3 downto 0) >= "0101" else bcd_value(3 downto 0);
...

or:

if clk = '1' and clk'event then
if load_data = '1' then
bcd_out_s <= (OTHERS => '0');
elsif shift_en_s = '1' then
bcd_value := bcd_out_s;
if bcd_value(3 downto 0) >= "0101" then
bcd_value(3 downto 0) := bcd_value(3 downto 0) + "0011";
end if;
...
bcd_out_s <= bcd_value(22 downto 0) & ser_out_s;
end if;
end if;

I'm sure there are other ways to structure the code, and my way may add an
additional clock cycle or may need an extra bit in the register to work
right, but you get the idea.

(2) Process #3 makes use of an asynchronous clear on the condition of
load_data. If you can do something synchronously instead of asynchronously,
you should. There's no harm in putting another if clause in your clocked
portion of the process to cover the clear while loading case.

(3) Process #2. You have two if statements, both of which affect bin_in_s:
if load_data = '1' then
bin_in_s <= data_in;
end if;
if shift_en_s = '1' then
bin_in_s <= bin_in_s(18 downto 0) & '0';
end if;
While legal, the interpretation (I think) is the same as the following code,
which is cleaner and thus less likely to be incorrect. My experience is
whenever I try to be as smart as the compiler, I end up getting bitten by it
later...
if shift_en_s = '1' then
bin_in_s <= bin_in_s(18 downto 0) & '0';
elsif load_data = '1' then
bin_in_s <= data_in;
end if;

(4) Process #1 & #4. You are instantiating many more registers than
necessary. You could get away without the data_out register (unless you
want to be able to process new data while some other chip takes its time
reading your result, which seems unlikely). Also, you are inserting an
extra cycle of latency with your data_ready & data_out registers. But there
should be nothing functionally wrong there.

(5) Your asynchronous reset may not be safe. The topic of many discussions.
Not the problem you're having now I bet.

Good luck,

Paul Leventis

 

[FE]

Hi Jason,
I found your algorithm in C (see source after the vhdl code) on the net.
It's cool.
I rewrited your code like this (see bellow) and it works fine (I tested):
(bin and bcd width (20 and 24) could be replaced by constants (C_BIN_WIDTH,
C_BCD_WIDTH)).
Hope this will help.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bin2bcd is
port(
i_clk : in std_logic;
i_rst_an : in std_logic;
i_load_data : in std_logic;
i_data : in std_logic_vector(20-1 downto 0);

o_data_rdy_q : out std_logic;
o_data_q : out std_logic_vector(24-1 downto 0)
);
end bin2bcd;

architecture rtl of bin2bcd is
begin
--------------------------------------------------------------------------
----
-- register mapping:
--
-- ------------------------
-- | v_bcd_bin_q |
-- ------------------------
-- | av_bcd_q | |
-- ------------------------
-- | | av_bin_q |
-- ------------------------
-- |xxx| 3 bits overlaps to save 3 clk cycle processing and 3
dff
--
--------------------------------------------------------------------------
----
ps_bin2bcd : process (i_rst_an, i_clk)
variable v_cnt_q : integer range 0 to 17;
variable v_en_shift_q : std_logic;
variable v_data_rdy_q : std_logic;
variable v_bcd_bin_q : unsigned(20+24-3-1 downto 0);
alias av_bin_q : unsigned(20-1 downto 0) is v_bcd_bin_q(20-1 downto 0);
alias av_bcd_q : unsigned(24-1 downto 0) is v_bcd_bin_q(20+24-3-1 downto
20-3);
begin
if i_rst_an = '0' then
v_cnt_q := 0;
v_en_shift_q := '0';
v_bcd_bin_q := (others => '0');
v_data_rdy_q := '0';
elsif rising_edge(i_clk) then
if i_load_data = '1' then
av_bcd_q := (others => '0');
av_bin_q := unsigned(i_data);
v_cnt_q := 0;
v_en_shift_q := '1';
v_data_rdy_q := '0';
elsif v_cnt_q = 17 then
v_bcd_bin_q := v_bcd_bin_q; -- optional assignment
v_cnt_q := v_cnt_q; -- optional assignment
v_en_shift_q := '0';
v_data_rdy_q := '1';
elsif v_en_shift_q = '1' then
for i in 0 to 5 loop
if av_bcd_q(4*i+3 downto 4*i) >= 5 then
av_bcd_q(4*i+3 downto 4*i) := av_bcd_q(4*i+3 downto 4*i) + 3;
end if;
end loop;
v_bcd_bin_q := v_bcd_bin_q sll 1;
v_cnt_q := v_cnt_q + 1;
v_en_shift_q := v_en_shift_q; -- optional assignment
v_data_rdy_q := v_data_rdy_q; -- optional assignment
else
v_bcd_bin_q := v_bcd_bin_q; -- optional assignment
v_cnt_q := v_cnt_q; -- optional assignment
v_en_shift_q := v_en_shift_q; -- optional assignment
v_data_rdy_q := v_data_rdy_q; -- optional assignment
end if;
end if;
o_data_q <= std_logic_vector(av_bcd_q);
o_data_rdy_q <= v_data_rdy_q;
end process;

end rtl;


**********C source code************

#include <stdio.h>
#include <stdlib.h>
#include <conio.h>

#define BIN_SIZE 4
#define MSB_MASK 0x80000000L
#define BCD_SIZE 13

typedef unsigned long BIN;
typedef unsigned char BCD[BCD_SIZE];

main()
{
BIN bin1,bin;
BCD bcd;
int i,j,k,carry;
char temp[9];


printf("enter number:");
scanf("%lu", &bin1);
bin=bin1;

for (i=0; i<= BCD_SIZE; i++) bcd=0;
printf("\n BCD BIN\n");
for (i=0; i<8*BIN_SIZE; i++) {
/* check for overflow */
for (j=0; j<BCD_SIZE; j++) {
if (bcd[j] >= 5) {
bcd[j] += 3;
/* printout for checking */
for (k=BCD_SIZE; k--; ) printf("%4s ", itoa(bcd[k],temp,2));
printf(" %x\n", bin);
}
}
/* shift right */
carry = (bin & MSB_MASK) == MSB_MASK;
bin = bin << 1;
for (j=0; j<BCD_SIZE; j++) {
bcd[j] = (bcd[j] << 1) | carry;
carry = (bcd[j] & 0x10) == 0x10;
bcd[j] = bcd[j] & 0xF;
}
/* printout for checking */
for (k=BCD_SIZE; k--; ) printf("%4s ", itoa(bcd[k],temp,2));
printf(" %x\n", bin);
}
printf("BIN = %lu\n", bin1);
printf("BCD = ");
for (k=BCD_SIZE; k--; ) printf("%d", bcd[k]);
}

regards
FE


"Jason Berringer" <look_at_bottom_of@email.com> wrote in message
news:IlGVa.3393$mv6.617644@news20.bellglobal.com...

Here is the code (after my text) instead of an attachment in case others
cannot read it.

It takes (or should take) 20 to 21 clock cycles to get the data from the
input to the output. I put a few numbers through the simulation the only
correct values are 0 and 1, all other tested were incorrect. I'm pretty
sure
it's a simple error that I'm not catching, I just can't see it at present.
Most of the stuff that I have done has been a bit more simple than this.
The
algorithm works from a sample I've seen (no code just an explanation).
Start
by shifting the most significant bit of your binary number into the least
significant bit of your "units" bcd value, when the number in the "units"
value is 5 or greater add 3 to it. Shift again, if the value is 5 or
greater
add 3 to it, the values will continue to spill over to the "tens",
"hundreds", "thousands", etc. You must add 3 to each of the bcd digits if
any is five or greater, by the last shift (same number of shifts as your
input binary value (in my case 20 bits)) you'll have the bcd
representation.
The example I mentioned above was for a microcontroller.

Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity bin2bcd is
port(
clk : in std_logic;
reset : in std_logic;
load_data : in std_logic;
data_in : in std_logic_vector(19 downto 0);
data_ready : out std_logic;
data_out : out std_logic_vector(23 downto 0)
);
end bin2bcd;

architecture behaviour of bin2bcd is

signal ser_out_s : std_logic;
signal shift_en_s : std_logic;
signal data_ready_s : std_logic;
signal count_s : std_logic_vector(4 downto 0);
signal bin_in_s : std_logic_vector(19 downto 0);
signal bcd_out_s : std_logic_vector(23 downto 0);

begin

process (reset, clk) begin
if reset = '1' then
count_s <= (others => '0');
shift_en_s <= '0';
data_ready_s <= '0';
elsif rising_edge(clk) then
if load_data = '1' then
count_s <= (others => '0');
shift_en_s <= '1';
elsif count_s = "10011" then
count_s <= (others => '0');
shift_en_s <= '0';
data_ready_s <= '1';
else
count_s <= count_s +1;
data_ready_s <= '0';
end if;
end if;
end process;

process (reset, clk) begin
if reset = '1' then
bin_in_s <= (others => '0');
elsif rising_edge(clk) then
if load_data = '1' then
bin_in_s <= data_in;
end if;
if shift_en_s = '1' then
bin_in_s <= bin_in_s(18 downto 0) & '0';
end if;
end if;
end process;

ser_out_s <= bin_in_s(19);

process (reset, clk, load_data)

variable bcd_value : std_logic_vector(23 downto 0);

begin

if reset = '1' or load_data = '1' then
bcd_value := (others => '0');
elsif rising_edge(clk) then
if shift_en_s = '1' then
bcd_value := bcd_value(22 downto 0) & ser_out_s;
bcd_out_s <= bcd_value;
if bcd_value(3 downto 0) >= "0101" then
bcd_value(3 downto 0) := bcd_value(3 downto 0) + "0011";
end if;
if bcd_value(7 downto 4) >= "0101" then
bcd_value(7 downto 4) := bcd_value(7 downto 4) + "0011";
end if;
if bcd_value(11 downto 8) >= "0101" then
bcd_value(11 downto 8) := bcd_value(11 downto 8) + "0011";
end if;
if bcd_value(15 downto 12) >= "0101" then
bcd_value(15 downto 12) := bcd_value(15 downto 12) + "0011";
end if;
if bcd_value(19 downto 16) >= "0101" then
bcd_value(19 downto 16) := bcd_value(19 downto 16) + "0011";
end if;
if bcd_value(23 downto 20) >= "0101" then
bcd_value(23 downto 20) := bcd_value(23 downto 20) + "0011";
end if;
end if;
end if;
end process;

process (reset, clk) begin
if reset = '1' then
data_out <= (others => '0');
data_ready <= '0';
elsif rising_edge(clk) then
if data_ready_s = '1' then
data_out <= bcd_out_s;
end if;
data_ready <= data_ready_s;
end if;
end process;

end behaviour;
"Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
news:GLFVa.9117$cF.3056@rwcrnsc53...

"Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
news:MzFVa.9078$cF.2637@rwcrnsc53...

"Jason Berringer" <look_at_bottom_of@email.com> wrote in message
news:kJCVa.3413$Cx4.543634@news20.bellglobal.com...
Hello, I have attached a portion of code for a binary to bcd
counter,
20
bits parallel input, and a 24 bit BCD output parallel. Although
internally
it converts it to serial to go through the conversion. I'm
attempting
the
shift and add three (if greater than or equal to 5) method, but I am
having
some problems. It works great on the simulator (Aldec Active HDL)
and
I
can
synthesize it but when I put it on the chip I'm getting some odd
things.
I
am using 16 input toggle switches and i debounced pb switch as a
load
switch, and my outputs are LEDs. When I set this up on the board my
outputs
go as follows:

The attachment didn't come through. Can you just include some of the
code
in the body, instead of an attachment?

OK, it did come through but I was looking in the wrong place. Still, it
is
often easier just to include it.

I am much better at reading verilog than VHDL, but it doesn't look right
to
me. Though I think I don't understand the algorithm, I think it needs
to
be
more complicated than that, though if you do an iterative algorithm it
might
not be so hard. How many clock cycles does it take to get the data
from
input to output? How many different values did you put through the
simulator in testing?

-- glen

 

[MK]

You should use conversion on formal, because c1 is output port - it must
looks like:

to_stdulogic(c1) => c1

regards,
MK.


"Anand P Paralkar" <anandp@sasken.com> wrote in message
newsine.LNX.4.33.0308011133070.13011-100000@pcz-anandp.sasken.com...

Hi,

I am trying to instantiate an entity within an architecture. The entity
ports are of type bit and the signals in the architecture, to which these
ports must be associated are of type std_logic. How do I interface ports
of mode "out" and type "bit" with signals that are of type "std_logic".

I have given an example below. Please go through it and the queries below
if you have the time. This would help me in making my point clear.

Thanks,
Anand

--------------------------------------------------------------------------
-----
Example
--------------------------------------------------------------------------
-----
Description
--------------------------------------------------------------------------
-----
cla_gen : The cla_gen entity and architecture form the combinational logic
model for a carry look ahead logic.

cla_16b : The cla_16b entity and architecture form the structural model
for a carry look ahead based 16 bit adder. The architecture
also instantiates a cla based 4 bit adder; The code for which
is not given below.

The architecture of the cla_16b (with std_logic signals) instantiates
cla_gen whose ports are of type bit.
--------------------------------------------------------------------------
-----
Code
--------------------------------------------------------------------------
-----
library ieee; use ieee.std_logic_1164.all;

entity cla_gen is
port (p0, p1, p2, p3, g0, g1, g2, g3, c_in : in bit;
c1, c2, c3 : out bit);
end entity cla_gen;

architecture combo of cla_gen is
begin
c1 <= g0 or (p0 and c_in);
c2 <= g1 or (p1 and (g0 or (p0 and c_in)));
c3 <= g2 or (p2 and (g1 or (p1 and (g0 or (p0 and c_in)))));
end architecture combo;

library ieee; use ieee.std_logic_1164.all;

entity cla_16b is
port (a, b : in std_logic_vector (15 downto 0);
s : out std_logic_vector (15 downto 0);
c_in : in std_logic;
c_out : out std_logic);
end entity cla_16b;

architecture struct of cla_16b is
signal g0, g1, g2, g3, p0, p1, p2, p3, c1, c2, c3 : std_logic;
begin

nib0 : entity work.cla(combo)
port map(a(3 downto 0), b(3 downto 0), c_in, s(3 downto 0),
open, g0, p0);

nib1 : entity work.cla(combo)
port map(a(7 downto 4), b(7 downto 4), c1, s(7 downto 4),
open, g1, p1);

nib2 : entity work.cla(combo)
port map(a(11 downto 8), b(11 downto 8), c1, s(11 downto 8),
open, g2, p2);

nib3 : entity work.cla(combo)
port map(a(15 downto 12), b(15 downto 12), c1, s(15 downto 12),
open, g3, p3);

cla_gen : entity work.cla_gen(combo)
port map(to_bit(p0), to_bit(p1), to_bit(p2), to_bit(p3),
to_bit(g0), to_bit(g1), to_bit(g2), to_bit(g3),
to_bit(c_in),
c1 => ??, c2 => ??,
c3 => ??);

end architecture struct;
--------------------------------------------------------------------------
-----
Queries
--------------------------------------------------------------------------
-----
1. What do I write in place of the "??" above?

2. I have tried writing:

c1 => to_stdulogic(c1)
| |
std_logic bit signal
signal of of cla_gen
cla_16b

However, the compiler (ncvhdl) returns a message:

subprogram call or operator argument type mismatch.

This probably means that the to_stdulogic call is not interpreting
its argument correctly.

--------------------------------------------------------------------------
-----

Thank you for your time.

Thanks,
Anand

 

[Anand P Paralkar]

MK,

I tried that, now the compiler returns an error on the input port.

That is in the instantiation:

cla_gen : entity work.cla_gen(combo)
port map(to_bit(p0), to_bit(p1), to_bit(p2), to_bit(p3),
to_bit(g0), to_bit(g1), to_bit(g2), to_bit(g3),
to_bit(c_in), to_stdulogic(c1) => c1,
to_stdulogic(c2) => c2, to_stdulogic(c3) => c3);

It reports an error as follows:

port map(to_bit(p0), to_bit(p1), to_bit(p2), to_bit(p3),
|
illegal type conversion function

Thanks for your reply.

Thanks,
Anand

 

[MK]

This is because function to_bit has 2 input formal parameters (one is
optional), so it not allowed as conversion function. You need write simple
wrapper:

function my_to_bit(p: std_ulogic) return bit is
begin
return to_bit(p);
end;

and use my_to_bit instead of to_bit in port map.

good luck
MK.

"Anand P Paralkar" <anandp@sasken.com> wrote in message
newsine.LNX.4.33.0308011406310.13011-100000@pcz-anandp.sasken.com...

MK,

I tried that, now the compiler returns an error on the input port.

That is in the instantiation:

cla_gen : entity work.cla_gen(combo)
port map(to_bit(p0), to_bit(p1), to_bit(p2), to_bit(p3),
to_bit(g0), to_bit(g1), to_bit(g2), to_bit(g3),
to_bit(c_in), to_stdulogic(c1) => c1,
to_stdulogic(c2) => c2, to_stdulogic(c3) => c3);

It reports an error as follows:

port map(to_bit(p0), to_bit(p1), to_bit(p2), to_bit(p3),
|
illegal type conversion function

Thanks for your reply.

Thanks,
Anand

 

[Pedro Claro]

Did you try the solution record in the xilinx website?


"Christopher Bunk" <cbunk@rochester.rr.com> wrote in message news:<SmcWa.54845$wk4.25284@twister.nyroc.rr.com>...

Ok, I have two questions.

1. When I run the synthesis tools it breaks up the chip usage into like 5
different categories(slices, flip flop slices, IOBs, GCLK and LUT). It
seems I'm running out of slices. What exactly is a slice and does anyone
have any suggestions on how to use less of these?

2. When I synthesize, I get the following warning: WARNING:Xst:1290 -
Hierarchical block <I3> is unconnected in block <Mmux__n0008>.It will be
removed from the design.

Now I realize this is only a warning and it synthesizes fine, but what
exactly does this mean and how do I get rid of it?

Thanks.

 

[Dennis Shumaker]

I updated my email address..First post does not haev the correct email
address

If someone doesn't know why I am getting the compile error, maybe
soemone could point me to understand what C0044 means? A error
definition book..that has more information.

Thank you

Dennis

user@domain.invalid wrote:

Hello

I am getting a compile error on this line in the file fourbitadder.vhd

SIGNAL im : faulty_resolution2 sulog_fault_array;

C0044: faulty_resolution2 is an undefined resolution function

I have no idea why it says that when it is clearly defined in the code
only a few lines above it!

Anyone know why I am getting this error message?

Thank you in advance

Dennis


------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

PACKAGE problem_2 IS

TYPE fault IS (sa1, sa0, nofault);

TYPE std_ulogic_faultable IS RECORD
log : std_ulogic;
fau : fault;
END RECORD;


TYPE stdlogic_table IS ARRAY (std_ulogic, std_ulogic) OF std_ulogic;
CONSTANT resolution_table : stdlogic_table := (
------------------------------------------------------------
--| U X 0 1 Z W L H - | |
------------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )); -- | - |


TYPE sulog_fault_array is ARRAY (NATURAL RANGE <&gt OF std_ulogic_faultable ;
-- TYPE sulog_fault_array is ARRAY (32 DOWNTO 0) OF std_ulogic_faultable ;

FUNCTION faulty_resolution (drivers : sulog_fault_array ) RETURN std_ulogic_faultable ;

-- SUBTYPE wired_std_ulogic_faultable IS faulty_resolution std_ulogic_faultable;

-- ##### Part D ######
CONSTANT and_table : stdlogic_table := (
------------------------------------------------------------
--| U X 0 1 Z W L H - | |
------------------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' )); -- | - |


CONSTANT xor_table : stdlogic_table := (
------------------------------------------------------------
--| U X 0 1 Z W L H - | |
------------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )); -- | - |


TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;

CONSTANT not_table : stdlogic_1d :=
------------------------------------------------------------
--| U X 0 1 Z W L H - | |
------------------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );


FUNCTION "nand" (l : std_ulogic; r : std_ulogic) RETURN std_ulogic;
FUNCTION "xor" (l : std_ulogic; r : std_ulogic) RETURN std_ulogic;



TYPE fault_vector IS ARRAY (8 DOWNTO 0) OF fault;
TYPE fault_array IS ARRAY (3 DOWNTO 0) OF fault_vector;

END problem_2;

PACKAGE BODY problem_2 IS


FUNCTION faulty_resolution (drivers : sulog_fault_array ) RETURN std_ulogic_faultable IS
-- record std_ulogic_faultable = (log, fau)
-- log = std_ulogic
-- fau = (sa1, sa0, nofault)

VARIABLE logic_temp : std_ulogic ;
VARIABLE fault_temp : fault := nofault;

BEGIN

FOR i IN drivers'RANGE LOOP

IF drivers(i).fau = sa0 THEN
logic_temp := '0';
fault_temp := sa0;
EXIT;
ELSIF drivers(i).fau = sa1 THEN
logic_temp := '1';
fault_temp := sa1;
EXIT;
ELSIF drivers(i).fau = nofault THEN
logic_temp := resolution_table (logic_temp, drivers(i).log);
fault_temp := drivers(i).fau;
end IF;

END LOOP;

RETURN (logic_temp, fault_temp);

END faulty_resolution;

--####### Part D ######

FUNCTION "nand" (l : std_ulogic; r : std_ulogic) RETURN std_ulogic IS
variable temp : std_ulogic;
BEGIN

temp := and_table(l, r);

RETURN not_table(temp);

END "nand";


FUNCTION "xor" (l : std_ulogic; r : std_ulogic) RETURN std_ulogic IS
BEGIN

RETURN xor_table (l, r);

END "xor";

END problem_2 ;


------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.problem_2.ALL;
--
--
-- ## 4-bit Adder
ENTITY fourbitadder IS
GENERIC (faults : fault_array := (
0 => (0=> sa1, OTHERS => sa0),
-- 0 => (OTHERS => nofault),
1 => (OTHERS => nofault),
2 => (OTHERS => nofault),
3 => (OTHERS => nofault)));

PORT (a, b : IN sulog_fault_array(3 DOWNTO 0);
cin : IN std_ulogic_faultable;
sum : OUT sulog_fault_array(3 DOWNTO 0);
cout : OUT std_ulogic_faultable);

END fourbitadder;
--
ARCHITECTURE structural OF fourbitadder IS

FUNCTION faulty_resolution2 (drivers : sulog_fault_array ) RETURN std_ulogic_faultable IS
-- record std_ulogic_faultable = (log, fau)
-- log = std_ulogic
-- fau = (sa1, sa0, nofault)

VARIABLE logic_temp : std_ulogic ;
VARIABLE fault_temp : fault := nofault;
VARIABLE temp_comb : std_ulogic_faultable;

BEGIN

FOR i IN drivers'RANGE LOOP

IF drivers(i).fau = sa0 THEN
logic_temp := '0';
fault_temp := sa0;
EXIT;
ELSIF drivers(i).fau = sa1 THEN
logic_temp := '1';
fault_temp := sa1;
EXIT;
ELSIF drivers(i).fau = nofault THEN
logic_temp := resolution_table (logic_temp, drivers(i).log);
fault_temp := drivers(i).fau;
end IF;

END LOOP;
temp_comb := (logic_temp, fault_temp);

RETURN temp_comb;

END faulty_resolution2;

--SUBTYPE fault_res IS faulty_resolution std_ulogic_faultable ;
--TYPE fault_res_array IS ARRAY (32 DOWNTO 0) OF fault_res;

COMPONENT xor2
PORT (i1, i2 : IN std_ulogic_faultable;
o1 : OUT std_ulogic_faultable);
END COMPONENT;
COMPONENT nand2
PORT (i1, i2 : IN std_ulogic_faultable;
o1 : OUT std_ulogic_faultable);
END COMPONENT;
COMPONENT nand3
PORT (i1, i2, i3 : IN std_ulogic_faultable;
o1 : OUT std_ulogic_faultable);
END COMPONENT;



SIGNAL im : faulty_resolution2 sulog_fault_array;


BEGIN
im(0) <= cin;
-- fulladders

iti : FOR i IN 0 TO 3 GENERATE
-- wires of each fulladder

itj : FOR j IN 0 TO 8 GENERATE
-- inject fault
im(i*8+j).fau <= faults(i)(j);
im(i*8+j).log <= '0' WHEN (faults(i)(j) = sa0) ELSE
'1' WHEN (faults(i)(j) = sa1) ELSE 'Z';
END GENERATE;

--fulladder
im(i*8+1) <= a(i);
im(i*8+2) <= b(i);
x1 : xor2 PORT MAP (im(i*8+1), im(i*8+2), im(i*8+3));
x2 : xor2 PORT MAP (im(i*8), im(i*8+3), im(i*8+7));
n1 : nand2 PORT MAP (im(i*8+1), im(i*8+2), im(i*8+4));
n2 : nand2 PORT MAP (im(i*8), im(i*8+1), im(i*8+5));
n3 : nand2 PORT MAP (im(i*8), im(i*8+2), im(i*8+6));
n4 : nand3 PORT MAP (im(i*8+4), im(i*8+5), im(i*8+6), im((i+1)*8));
sum(i) <= im(i*8+7);
END GENERATE;

cout <= im(32);

END structural;


------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.problem_2.ALL;

ENTITY nand2 IS

PORT (i1, i2 : IN std_ulogic_faultable;
o1 : OUT std_ulogic_faultable);

END nand2;
--
ARCHITECTURE dataflow OF nand2 IS

BEGIN

PROCESS (i1, i2)
BEGIN
IF i1.fau = sa0 OR i2.fau = sa0 THEN
o1 <= ('1', nofault);
ELSIF i1.fau = sa1 THEN
o1 <= (('1' nand i2.log), nofault);
ELSIF i2.fau = sa1 THEN
o1 <= ((i1.log nand '1'), nofault);
ELSE
o1 <= (( i1.log nand i2.log), nofault);
END IF;
END PROCESS;

END dataflow;


------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.problem_2.ALL;

ENTITY nand3 IS

PORT (i1, i2, i3 : IN std_ulogic_faultable;
o1 : OUT std_ulogic_faultable);

END nand3;
--
ARCHITECTURE dataflow OF nand3 IS

BEGIN

PROCESS (i1, i2, i3)
BEGIN
IF i1.fau = sa0 OR i2.fau = sa0 OR i3.fau = sa0 THEN
o1 <= ('1', nofault);
ELSIF i1.fau = sa1 THEN
o1 <= ( (and_table('1',i2.log) nand i3.log), nofault);
ELSIF i2.fau = sa1 THEN
o1 <= ( (and_table(i1.log, '1') nand i3.log), nofault);
ELSIF i3.fau = sa1 THEN
o1 <= ( (and_table(i1.log, i2.log) nand '1'), nofault);
ELSE
o1 <= ( (and_table(i1.log, i2.log) nand i3.log), nofault);
END IF;
END PROCESS;



END dataflow;


------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.problem_2.ALL;


-- ## XOR2

ENTITY xor2 IS
PORT (i1, i2 : IN std_ulogic_faultable;
o1 : OUT std_ulogic_faultable);
END xor2;
--
ARCHITECTURE dataflow OF xor2 IS
BEGIN

PROCESS (i1, i2)
BEGIN
IF i1.fau = sa0 THEN
o1 <= ('0' xor i2.log, nofault);
ELSIF i2.fau = sa0 THEN
o1 <= (i1.log xor '0', nofault);
ELSIF i1.fau = sa1 THEN
o1 <= ('1' xor i2.log, nofault);
ELSIF i2.fau = sa1 THEN
o1 <= (i1.log xor '1', nofault);
ELSE
o1 <= (i1.log xor i2.log, nofault);
END IF;
END PROCESS;

END dataflow;



------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.problem_2.ALL;

-- ## Part d test
ENTITY part_d_test IS
END part_d_test;
--
ARCHITECTURE testbench OF part_d_test IS

COMPONENT fourbitadder
GENERIC (faults : fault_array := (
-- example 0 => (0=> sa1, OTHERS => nofault),
0 => (OTHERS => nofault),
1 => (OTHERS => nofault),
2 => (OTHERS => nofault),
3 => (OTHERS => nofault)));

PORT (a, b : IN sulog_fault_array (3 DOWNTO 0);
cin : IN std_ulogic_faultable;
sum : OUT sulog_fault_array (3 DOWNTO 0);
cout : OUT std_ulogic_faultable);

END COMPONENT;

FOR ALL: fourbitadder USE ENTITY WORK.fourbitadder(structural);

SIGNAL a, b, sum : sulog_fault_array (3 DOWNTO 0);
SIGNAL cin, cout : std_ulogic_faultable;

SIGNAL sum_log : std_ulogic_vector (3 DOWNTO 0);
SIGNAL a_log, b_log : std_ulogic_vector (3 DOWNTO 0) := "0000";
SIGNAL cin_log : std_ulogic := '0';
SIGNAL cout_log : std_ulogic ;

SIGNAL a_fault, b_fault, sum_fault : fault_array(3 DOWNTO 0);

SIGNAL aflt0, aflt1, aflt2, aflt3 : fault;
SIGNAL bflt0, bflt1, bflt2, bflt3 : fault;
SIGNAL sflt0, sflt1, sflt2, sflt3 : fault;
SIGNAL cin_fault, cout_fault : fault;

BEGIN

dut: fourbitadder GENERIC MAP (faults => (
0 => (OTHERS => sa1),
1 => (OTHERS => nofault),
2 => (OTHERS => nofault),
3 => (OTHERS => nofault)))
PORT MAP (a, b, cin, sum, cout);

aflt0 <= a(0).fau;
aflt2 <= a(2).fau;
aflt1 <= a(1).fau;
aflt3 <= a(3).fau;
bflt0 <= b(0).fau;
bflt2 <= b(2).fau;
bflt1 <= b(1).fau;
bflt3 <= b(3).fau;
sflt0 <= sum(0).fau;
sflt2 <= sum(2).fau;
sflt1 <= sum(1).fau;
sflt3 <= sum(3).fau;

cin_fault <= cin.fau;
cout_fault <= cout.fau;

a_log(3 DOWNTO 0) <= (a(3).log, a(2).log, a(1).log, a(0).log);
b_log(3 DOWNTO 0) <= (b(3).log, b(2).log, b(1).log, b(0).log);
sum_log(3 DOWNTO 0) <= (sum(3).log, sum(2).log, sum(1).log, sum(0).log);
cout_log <= cout.log;

PROCESS
BEGIN
cin.fau <= nofault;

a(0).fau <= nofault;
a(1).fau <= nofault;
a(2).fau <= nofault;
a(3).fau <= nofault;

b(0).fau <= nofault;
b(1).fau <= nofault;
b(2).fau <= nofault;
b(3).fau <= nofault;


-- actual sigs
cin.log <= '0';

a(0).log <= '0';
a(1).log <= '0';
a(2).log <= '0';
a(3).log <= '0';

b(0).log <= '0';
b(1).log <= '0';
b(2).log <= '0';
b(3).log <= '0';

--cout.fau <= nofault;

sum(0).fau <= nofault;
sum(1).fau <= nofault;
sum(2).fau <= nofault;
sum(3).fau <= nofault;
wait for 10 NS;
a(0).log <= '1';
wait for 10 NS;
b(0).log <= '1';
wait for 10 NS;
a(1).log <= '1';
a(0).log <= '0';
b(0).log <= '0';
wait for 10 NS;
b(0).log <= '1';
wait for 10 NS;
a(0).log <= '0';
wait for 10 NS;
a(0).log <= '1';
a(1).log <= '1';
a(2).log <= '1';
a(3).log <= '1';
b(0).log <= '0';
b(1).log <= '0';
b(2).log <= '0';
b(3).log <= '0';
WAIT FOR 10 NS;
b(0).log <= '1';
WAIT FOR 10 NS;

WAIT;

END PROCESS;

END testbench;

 

[FE]

Hi Dennis,

faulty_resolution2 is a resolution function of std_ulogic_faultable and not
sulog_fault_array.

So you should write,
signal im : faulty_resolution2 std_ulogic_faultable;

but im must be an array so what you want I think is something like that :
subtype my_resolved_type is faulty_resolution2 std_ulogic_faultable;
type my_resolved_type_array is array (natural range <&gt of
my_resolved_type;

signal im : my_resolved_type_array(32 downto 0);

regards
FE


"Dennis Shumaker" <lenden@attbi.com> wrote in message
news:3F2B1886.4050908@attbi.com...

I updated my email address..First post does not haev the correct email
address

If someone doesn't know why I am getting the compile error, maybe
soemone could point me to understand what C0044 means? A error
definition book..that has more information.

Thank you

Dennis

user@domain.invalid wrote:
Hello

I am getting a compile error on this line in the file fourbitadder.vhd

SIGNAL im : faulty_resolution2 sulog_fault_array;

C0044: faulty_resolution2 is an undefined resolution function

I have no idea why it says that when it is clearly defined in the code
only a few lines above it!

Anyone know why I am getting this error message?

Thank you in advance

Dennis


------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

PACKAGE problem_2 IS

TYPE fault IS (sa1, sa0, nofault);

TYPE std_ulogic_faultable IS RECORD
log : std_ulogic;
fau : fault;
END RECORD;


TYPE stdlogic_table IS ARRAY (std_ulogic, std_ulogic) OF std_ulogic;
CONSTANT resolution_table : stdlogic_table := (
------------------------------------------------------------
--| U X 0 1 Z W L H - | |
------------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )); -- | - |


TYPE sulog_fault_array is ARRAY (NATURAL RANGE <&gt OF
std_ulogic_faultable ;
-- TYPE sulog_fault_array is ARRAY (32 DOWNTO 0) OF
std_ulogic_faultable ;

FUNCTION faulty_resolution (drivers : sulog_fault_array ) RETURN
std_ulogic_faultable ;

-- SUBTYPE wired_std_ulogic_faultable IS faulty_resolution
std_ulogic_faultable;

-- ##### Part D ######
CONSTANT and_table : stdlogic_table := (
------------------------------------------------------------
--| U X 0 1 Z W L H - | |
------------------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' )); -- | - |


CONSTANT xor_table : stdlogic_table := (
------------------------------------------------------------
--| U X 0 1 Z W L H - | |
------------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )); -- | - |


TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;

CONSTANT not_table : stdlogic_1d :=
------------------------------------------------------------
--| U X 0 1 Z W L H - | |
------------------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );


FUNCTION "nand" (l : std_ulogic; r : std_ulogic) RETURN std_ulogic;
FUNCTION "xor" (l : std_ulogic; r : std_ulogic) RETURN std_ulogic;



TYPE fault_vector IS ARRAY (8 DOWNTO 0) OF fault;
TYPE fault_array IS ARRAY (3 DOWNTO 0) OF fault_vector;

END problem_2;

PACKAGE BODY problem_2 IS


FUNCTION faulty_resolution (drivers : sulog_fault_array ) RETURN
std_ulogic_faultable IS
-- record std_ulogic_faultable = (log, fau)
-- log = std_ulogic
-- fau = (sa1, sa0, nofault)

VARIABLE logic_temp : std_ulogic ;
VARIABLE fault_temp : fault := nofault;

BEGIN

FOR i IN drivers'RANGE LOOP

IF drivers(i).fau = sa0 THEN
logic_temp := '0';
fault_temp := sa0;
EXIT;
ELSIF drivers(i).fau = sa1 THEN
logic_temp := '1';
fault_temp := sa1;
EXIT;
ELSIF drivers(i).fau = nofault THEN
logic_temp := resolution_table (logic_temp, drivers(i).log);
fault_temp := drivers(i).fau;
end IF;

END LOOP;

RETURN (logic_temp, fault_temp);

END faulty_resolution;

--####### Part D ######

FUNCTION "nand" (l : std_ulogic; r : std_ulogic) RETURN std_ulogic IS
variable temp : std_ulogic;
BEGIN

temp := and_table(l, r);

RETURN not_table(temp);

END "nand";


FUNCTION "xor" (l : std_ulogic; r : std_ulogic) RETURN std_ulogic IS
BEGIN

RETURN xor_table (l, r);

END "xor";

END problem_2 ;


------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.problem_2.ALL;
--
--
-- ## 4-bit Adder
ENTITY fourbitadder IS
GENERIC (faults : fault_array := (
0 => (0=> sa1, OTHERS => sa0),
-- 0 => (OTHERS => nofault),
1 => (OTHERS => nofault),
2 => (OTHERS => nofault),
3 => (OTHERS => nofault)));

PORT (a, b : IN sulog_fault_array(3 DOWNTO 0);
cin : IN std_ulogic_faultable;
sum : OUT sulog_fault_array(3 DOWNTO 0);
cout : OUT std_ulogic_faultable);

END fourbitadder;
--
ARCHITECTURE structural OF fourbitadder IS

FUNCTION faulty_resolution2 (drivers : sulog_fault_array ) RETURN
std_ulogic_faultable IS
-- record std_ulogic_faultable = (log, fau)
-- log = std_ulogic
-- fau = (sa1, sa0, nofault)

VARIABLE logic_temp : std_ulogic ;
VARIABLE fault_temp : fault := nofault;
VARIABLE temp_comb : std_ulogic_faultable;

BEGIN

FOR i IN drivers'RANGE LOOP

IF drivers(i).fau = sa0 THEN
logic_temp := '0';
fault_temp := sa0;
EXIT;
ELSIF drivers(i).fau = sa1 THEN
logic_temp := '1';
fault_temp := sa1;
EXIT;
ELSIF drivers(i).fau = nofault THEN
logic_temp := resolution_table (logic_temp, drivers(i).log);
fault_temp := drivers(i).fau;
end IF;

END LOOP;
temp_comb := (logic_temp, fault_temp);

RETURN temp_comb;

END faulty_resolution2;

--SUBTYPE fault_res IS faulty_resolution std_ulogic_faultable ;
--TYPE fault_res_array IS ARRAY (32 DOWNTO 0) OF fault_res;

COMPONENT xor2
PORT (i1, i2 : IN std_ulogic_faultable;
o1 : OUT std_ulogic_faultable);
END COMPONENT;
COMPONENT nand2
PORT (i1, i2 : IN std_ulogic_faultable;
o1 : OUT std_ulogic_faultable);
END COMPONENT;
COMPONENT nand3
PORT (i1, i2, i3 : IN std_ulogic_faultable;
o1 : OUT std_ulogic_faultable);
END COMPONENT;



SIGNAL im : faulty_resolution2 sulog_fault_array;


BEGIN
im(0) <= cin;
-- fulladders

iti : FOR i IN 0 TO 3 GENERATE
-- wires of each fulladder

itj : FOR j IN 0 TO 8 GENERATE
-- inject fault
im(i*8+j).fau <= faults(i)(j);
im(i*8+j).log <= '0' WHEN (faults(i)(j) = sa0) ELSE
'1' WHEN (faults(i)(j) = sa1) ELSE 'Z';
END GENERATE;

--fulladder
im(i*8+1) <= a(i);
im(i*8+2) <= b(i);
x1 : xor2 PORT MAP (im(i*8+1), im(i*8+2), im(i*8+3));
x2 : xor2 PORT MAP (im(i*8), im(i*8+3), im(i*8+7));
n1 : nand2 PORT MAP (im(i*8+1), im(i*8+2), im(i*8+4));
n2 : nand2 PORT MAP (im(i*8), im(i*8+1), im(i*8+5));
n3 : nand2 PORT MAP (im(i*8), im(i*8+2), im(i*8+6));
n4 : nand3 PORT MAP (im(i*8+4), im(i*8+5), im(i*8+6), im((i+1)*8));
sum(i) <= im(i*8+7);
END GENERATE;

cout <= im(32);

END structural;


------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.problem_2.ALL;

ENTITY nand2 IS

PORT (i1, i2 : IN std_ulogic_faultable;
o1 : OUT std_ulogic_faultable);

END nand2;
--
ARCHITECTURE dataflow OF nand2 IS

BEGIN

PROCESS (i1, i2)
BEGIN
IF i1.fau = sa0 OR i2.fau = sa0 THEN
o1 <= ('1', nofault);
ELSIF i1.fau = sa1 THEN
o1 <= (('1' nand i2.log), nofault);
ELSIF i2.fau = sa1 THEN
o1 <= ((i1.log nand '1'), nofault);
ELSE
o1 <= (( i1.log nand i2.log), nofault);
END IF;
END PROCESS;

END dataflow;


------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.problem_2.ALL;

ENTITY nand3 IS

PORT (i1, i2, i3 : IN std_ulogic_faultable;
o1 : OUT std_ulogic_faultable);

END nand3;
--
ARCHITECTURE dataflow OF nand3 IS

BEGIN

PROCESS (i1, i2, i3)
BEGIN
IF i1.fau = sa0 OR i2.fau = sa0 OR i3.fau = sa0 THEN
o1 <= ('1', nofault);
ELSIF i1.fau = sa1 THEN
o1 <= ( (and_table('1',i2.log) nand i3.log), nofault);
ELSIF i2.fau = sa1 THEN
o1 <= ( (and_table(i1.log, '1') nand i3.log), nofault);
ELSIF i3.fau = sa1 THEN
o1 <= ( (and_table(i1.log, i2.log) nand '1'), nofault);
ELSE
o1 <= ( (and_table(i1.log, i2.log) nand i3.log), nofault);
END IF;
END PROCESS;



END dataflow;


------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.problem_2.ALL;


-- ## XOR2

ENTITY xor2 IS
PORT (i1, i2 : IN std_ulogic_faultable;
o1 : OUT std_ulogic_faultable);
END xor2;
--
ARCHITECTURE dataflow OF xor2 IS
BEGIN

PROCESS (i1, i2)
BEGIN
IF i1.fau = sa0 THEN
o1 <= ('0' xor i2.log, nofault);
ELSIF i2.fau = sa0 THEN
o1 <= (i1.log xor '0', nofault);
ELSIF i1.fau = sa1 THEN
o1 <= ('1' xor i2.log, nofault);
ELSIF i2.fau = sa1 THEN
o1 <= (i1.log xor '1', nofault);
ELSE
o1 <= (i1.log xor i2.log, nofault);
END IF;
END PROCESS;

END dataflow;



------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.problem_2.ALL;

-- ## Part d test
ENTITY part_d_test IS
END part_d_test;
--
ARCHITECTURE testbench OF part_d_test IS

COMPONENT fourbitadder
GENERIC (faults : fault_array := (
-- example 0 => (0=> sa1, OTHERS => nofault),
0 => (OTHERS => nofault),
1 => (OTHERS => nofault),
2 => (OTHERS => nofault),
3 => (OTHERS => nofault)));

PORT (a, b : IN sulog_fault_array (3 DOWNTO 0);
cin : IN std_ulogic_faultable;
sum : OUT sulog_fault_array (3 DOWNTO 0);
cout : OUT std_ulogic_faultable);

END COMPONENT;

FOR ALL: fourbitadder USE ENTITY WORK.fourbitadder(structural);

SIGNAL a, b, sum : sulog_fault_array (3 DOWNTO 0);
SIGNAL cin, cout : std_ulogic_faultable;

SIGNAL sum_log : std_ulogic_vector (3 DOWNTO 0);
SIGNAL a_log, b_log : std_ulogic_vector (3 DOWNTO 0) := "0000";
SIGNAL cin_log : std_ulogic := '0';
SIGNAL cout_log : std_ulogic ;

SIGNAL a_fault, b_fault, sum_fault : fault_array(3 DOWNTO 0);

SIGNAL aflt0, aflt1, aflt2, aflt3 : fault;
SIGNAL bflt0, bflt1, bflt2, bflt3 : fault;
SIGNAL sflt0, sflt1, sflt2, sflt3 : fault;
SIGNAL cin_fault, cout_fault : fault;

BEGIN

dut: fourbitadder GENERIC MAP (faults => (
0 => (OTHERS => sa1),
1 => (OTHERS => nofault),
2 => (OTHERS => nofault),
3 => (OTHERS => nofault)))
PORT MAP (a, b, cin, sum, cout);

aflt0 <= a(0).fau;
aflt2 <= a(2).fau;
aflt1 <= a(1).fau;
aflt3 <= a(3).fau;
bflt0 <= b(0).fau;
bflt2 <= b(2).fau;
bflt1 <= b(1).fau;
bflt3 <= b(3).fau;
sflt0 <= sum(0).fau;
sflt2 <= sum(2).fau;
sflt1 <= sum(1).fau;
sflt3 <= sum(3).fau;

cin_fault <= cin.fau;
cout_fault <= cout.fau;

a_log(3 DOWNTO 0) <= (a(3).log, a(2).log, a(1).log, a(0).log);
b_log(3 DOWNTO 0) <= (b(3).log, b(2).log, b(1).log, b(0).log);
sum_log(3 DOWNTO 0) <= (sum(3).log, sum(2).log, sum(1).log, sum(0).log);
cout_log <= cout.log;

PROCESS
BEGIN
cin.fau <= nofault;

a(0).fau <= nofault;
a(1).fau <= nofault;
a(2).fau <= nofault;
a(3).fau <= nofault;

b(0).fau <= nofault;
b(1).fau <= nofault;
b(2).fau <= nofault;
b(3).fau <= nofault;


-- actual sigs
cin.log <= '0';

a(0).log <= '0';
a(1).log <= '0';
a(2).log <= '0';
a(3).log <= '0';

b(0).log <= '0';
b(1).log <= '0';
b(2).log <= '0';
b(3).log <= '0';

--cout.fau <= nofault;

sum(0).fau <= nofault;
sum(1).fau <= nofault;
sum(2).fau <= nofault;
sum(3).fau <= nofault;
wait for 10 NS;
a(0).log <= '1';
wait for 10 NS;
b(0).log <= '1';
wait for 10 NS;
a(1).log <= '1';
a(0).log <= '0';
b(0).log <= '0';
wait for 10 NS;
b(0).log <= '1';
wait for 10 NS;
a(0).log <= '0';
wait for 10 NS;
a(0).log <= '1';
a(1).log <= '1';
a(2).log <= '1';
a(3).log <= '1';
b(0).log <= '0';
b(1).log <= '0';
b(2).log <= '0';
b(3).log <= '0';
WAIT FOR 10 NS;
b(0).log <= '1';
WAIT FOR 10 NS;

WAIT;

END PROCESS;

END testbench;

 

[Mike Treseler]

user@domain.invalid wrote:

SIGNAL im : faulty_resolution2 sulog_fault_array;

C0044: faulty_resolution2 is an undefined resolution function

I have no idea why it says that when it is clearly defined in the code
only a few lines above it!

Sometimes the compiler message misses the first error, which
in this case may be that faulty_resolution2 failed to compile
and maybe that is why it is undefined.

Consider testing just faulty_resolution2 with a simpler testbench.

-- Mike Treseler

 

[hamed]

"Markus Sponsel" <msponsel@nospam.profichip.com> wrote in message news:<bgktt5$pqok5$1@ID-40100.news.uni-berlin.de>...

hamed wrote:
Hi.Can anynoe help me to find a correct VHDL code for CAN DataLink
layer? I want it as a guide to write my own code.(It is not for
commercial use) Thanks&bye

opencores.org has a finished CAN controller project. Though I don't
know whether it works and/or supports all modes it may be a good
starting point. But if you insist building your own code, why don't
you download the CAN specification and build your own controller
from scratch?

best regards,

Markus Sponsel

========================================
profichip GmbH
Einsteinstraße 6
91074 Herzogenaurach
Germany
============================================

Thanks for your attention Markus.The CAN code you mentioned is
written by
Mr Shehrayar Shahin and he has send it to me via emial.But it is not
tested yet and it is not so readable for me( I can't understand the
characteristics of CAN by studing this code ).I have downloaded the
CAN specification ( CANA and CANB ) and I have studied them but still
some properties of CAN are not obvious for me.( For example I have
some questions about Error handling and synchronization of nodes
).That's why I need some thing more usefull and reliable.( A correct
and reliable code or an article which describes CAN in more details )

best regards

Hamed pishvayazdi

 

[Jonathan Bromley]

"hamed" <hamedpi@yahoo.com> wrote in message
news:fb139aff.0308060043.1bd7d31f@posting.google.com...

Thanks for your attention Markus.
[...]
That's why I need some thing more usefull and reliable.( A correct
and reliable code or an article which describes CAN in more details )

Take a look at http://www.mjschofield.com/. It will be much
more helpful than trying to understand a CANbus core.

I agree that the error management in CAN is complicated,
but you are wrong if you complain that it's not CLEAR from
the spec - it is very clearly specified indeed. Sorry
to bring bad news, but you've simply got to go away and
sit in a quiet corner somewhere and read the spec carefully
until you understand it.

Good luck
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Yahoo]

I copied these lines from some other postings. Search this group for
" Type conversion with characters "

int_x <= CHARACTER'POS(char_a);
char_a <= CHARACTER'VAL(int_x);


use ieee.numeric_std.all;
....
slv_vec <= STD_LOGIC_VECTOR(TO_UNSIGNED(CHARACTER'POS(char_a), Nbits));

where Nbits is the number of bits slv_vec'LENGTH.

Good luck,
Troy


Sunday wrote:

Hi all,

I've some problems with type conversion :

How convert a character into a std_logic_vector (7 downto 0) ? (I've
tried std_logic_vector(value) and to_stdlogicvector(value) but these are
not clodely related types and it's don't work ...)

And ... how to do the inverse, a std_logic_vector (7 downto 0) into a
character ?


Thanks for your help.

Stéphane. (bystef@club-internet.fr)

 

[Mike Treseler]

hamed wrote:

Thanks for your attention Markus.The CAN code you mentioned is
written by
Mr Shehrayar Shahin and he has send it to me via emial.But it is not
tested yet and it is not so readable for me( I can't understand the
characteristics of CAN by studing this code ).

No matter how well written core code is,
I can only completely understand a non-trivial
synth entity with the help of simulation waveforms.

Compile and Run the testbench, study the transactions,
then read the spec.

-- Mike Treseler

 

[Jerry]

"smu" <pas@d.adresse> wrote in message news:<3f2fd735$0$16171$626a54ce@news.free.fr>...

I try to find a elegant way to code a component in order to employ it with
different value of a constant.
....
You will have to use generics and for..generate.

Since you are using attributes to specify single rom16x1 component
contents, the solution is not the nicest one:
--------start---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity c_nibble is
generic ( busmax : integer := 3;
inits : string := "926C4B5A99CC552A" );
port ( input : in std_logic_vector(3 downto 0);
output : out std_logic_vector(busmax downto 0));
end c_nibble;

architecture c_nibble_a of c_nibble is
component rom16x1
port( a3, a2, a1, a0 : in std_logic;
o : out std_logic);
end component;
attribute init : string;
begin
rom: for i in busmax downto 0 generate
attribute init of blk : label is
inits((busmax-i)*4+1 to (busmax-i)*4+4 );
begin
blk: rom16x1 port map ( a3 => input(3), a2 => input(2), a1 => input(1),
a0 => input(0), o => output(i));
end generate rom;
end c_nibble_a;
-----------stop------------

VHDL 93 compliant compiler is required to handle this code.

Good luck!

Jerry

 

[smu]

"Ajeetha Kumari" <aji@noveldv.com> a écrit dans le message de news:
8df95881.0308060742.41a91a0b@posting.google.com...

Hi,
Look for GENERATE construct, I think that should fit your need.

HTH,
Ajeetha

I know GENERATE but can I use it with ATTRIBUTE ?
If yes, how uses it in the declaratory part of the ARCHITECTURE block ?

Thanks in advance

smu

http://www.noveldv.com
"smu" <pas@d.adresse> wrote in message
news:<3f2fd735$0$16171$626a54ce@news.free.fr>...
I try to find a elegant way to code a component in order to employ it
with
different value of a constant.

The code is :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity c_nibble is
Port ( input : in std_logic_vector(3 downto 0);
output : out std_logic_vector(3 downto 0));
end c_nibble;

 

[smu]

Which would be the nicest solution to initialize the ROM blocks ?

smu

"Jerry" <jaroslawk@hotmail.com> a écrit dans le message de news:
711e889f.0308061422.2cb4adab@posting.google.com...

"smu" <pas@d.adresse> wrote in message
news:<3f2fd735$0$16171$626a54ce@news.free.fr>...
I try to find a elegant way to code a component in order to employ it
with
different value of a constant.
....
You will have to use generics and for..generate.
Since you are using attributes to specify single rom16x1 component
contents, the solution is not the nicest one:
--------start---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity c_nibble is
generic ( busmax : integer := 3;
inits : string := "926C4B5A99CC552A" );
port ( input : in std_logic_vector(3 downto 0);
output : out std_logic_vector(busmax downto 0));
end c_nibble;

architecture c_nibble_a of c_nibble is
component rom16x1
port( a3, a2, a1, a0 : in std_logic;
o : out std_logic);
end component;
attribute init : string;
begin
rom: for i in busmax downto 0 generate
attribute init of blk : label is
inits((busmax-i)*4+1 to (busmax-i)*4+4 );
begin
blk: rom16x1 port map ( a3 => input(3), a2 => input(2), a1 =
input(1),
a0 => input(0), o => output(i));
end generate rom;
end c_nibble_a;
-----------stop------------

VHDL 93 compliant compiler is required to handle this code.

Good luck!

Jerry

 

[Mike Treseler]

smu wrote:

Which would be the nicest solution to initialize the ROM blocks ?

This rom has been nice to me:

http://groups.google.com/groups?q=this_rom

-- Mike Treseler

 

[Mike Treseler]

SneakerNet wrote:

The receive module of the uart has these I/Os:
clock: input
baudclock: input
RxD: input
Data_FromPC[7..0]: output

That would be Data_To_PC

RxComplete: output

The I/O's are self-explanatory.
Now how can i use the RxComplete signal to implement the buffer? Help. Any
info/advice appreciated.

1 8 8
RxD]---[UART]---/--[FIFO]--/---[Data_To_PC



-- Mike Treseler