Clock Edge notation

kingfischer@rediffmail.com (Kingfischer) writes:
I have a question about VHDL If Statement. I have shown two examples below.
Kindly comment if they are same or not ....or how they are percieved.

If( fruit = (apple or orange or mango or banana)) then

If (( fruit=apple) or (fruit = orange) or (fruit = mango) or (fruit =banana))then
Click to expand...
If I do your homework, will you have the school issue the diploma in my
name?

They're not the same, but the reason why is left as an exercise for the
student.
 
cristian wrote:
Thanks very much for all your feedback. Though, it seems to me that I
did not get the right answer yet.

First, Alan's answer regarding using 'POS, even though is not
synthesisable, it would not help since I have other than binary/seq
kind of encoding. On the other side, the problem of declaring an
std_logic_vector constant with the specific encoding (same solution
that Paul brought out and close to the Rick's point); this approach
will create one constant per each state of the SM. Therefore, there
will not be a 'common' state variable for all the states. Remember, I
need to something like this:
oe_rst <= sv(1) and not sv(2) and not sv(3);
So, I need to have access to the 'common' state variables.

I investigated a little further and found an intersting posting in
this group associated with the 'POS. Search the following string in
the VHDL group:

non-constant 'pos, or other method of state debugging

Though, the solution is just suitable for binary encoding.
Click to expand...
Two points, first if you are not trying to optimize the decoding of your
outputs, I don't understand why you need separate access to the bits in
your state variable. But I will ignore my lack of understanding.

The second point is that using an SLV will give you *exactly* what you
are asking for. You can either use the SLV as the state variable in the
FSM description, or as I suggested, you can use your enumerated signal
in the FSM and assign an SLV to the value of the state variable. In
either case you can then access the bits individually. The fact that
you use constants to define the SLV values does not prevent you from
accessing the individual bits.

type states is
(b_busy,backoff,base_address,card_present,timer_dat,timer_read,timer_write);
attribute syn_enum_encoding: string;
attribute syn_enum_encoding of states : type is "000 001 011 111 110 101
100";
SIGNAL state_enum : states;
signal state_slv : std_logic_vector(2 downto 0);

process (clk, reset) begin
case (state_enum) is
when b_busy =>
if input_a = '0' then
state_enum <= backoff;
end if;
when backoff =>
state_enum <= b_busy;
end case;
end process;

process (state) begin
case (state) of
b_busy => state_slv <= "000";
backoff => state_slv <= "001";
.
.
.
end case;
end process;

output_a <= state_slv(0) and state_slv(1) or state_slv(2);
output_b <= state_slv(2) and state_slv(1) xor state_slv(0);

If you want to delete the enumerated signal, you can make the names
b_busy, backoff, etc, constants with the values of "000", "001", etc.
This will eliminate one of the processes.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
Patrick wrote:
Hello everybody,

I would like to use Modelsim and Simulink to simulate my VHDL code...

But the minimum time step is 1 ns !!!

Is it possible to cosimulate VHDL with Simulink and have ŕ 1 ps time step ?

I tried also Simulink with ActiveHDL and I have the same problem !!!

Is it Simulink which have this limitation ?

Thanks to all VHDL designer...
Click to expand...
Put this in your modelsim(.ini) configuration file:

; Simulator resolution
Resolution = ps


Regards,
--
==================================================================
Johan Wouters === +32-16-395 616/619 (Tel/Fax)
Senior ASIC designer === Interleuvenlaan 86
TranSwitch Easics === B-3001 Leuven, BELGIUM
mailto:johanw@easics.be === http://www.easics.com
 
Hi Andre,

what does back-annotate assignments exactly mean?
Click to expand...
It basically means that, for instance, pin locations chosen by Quartus are
now converted to 'hard' assignments in the currently-used .qsf file.

Quartus will let you go into all sorts of detail, down to individual LE
placement. Most of the time you'll only want the pinout to be
back-annotated.

You will very likely get into trouble with your PCB guy though, as the
automatic pin placements that Quartus produces are not the most optimal
ones for PCB design.

If you want to try out different pinouts, Quartus II 4.1 has the ability to
create several revisions of a project, including different pinouts, logic
options etc.

Best regards,


Ben
 
Rakesh Sharma wrote:

ERROR:NgdBuild:755 - Line 2 in 'musicmp3.ucf': Could not find net(s) 'rxd' in
the design. To suppress this error use the -aul switch, specify the correct
net name or remove the constraint.
ERROR:NgdBuild:755 - Line 4 in 'musicmp3.ucf': Could not find net(s) 'clk' in
the design. To suppress this error use the -aul switch, specify the correct
net name or remove the constraint.
Click to expand...
Consider declaring signals named rxd and clk.

-- Mike Treseler
 
Rakesh Sharma wrote:

Hi,

I am getting the following error in Xilinx:-

Annotating constraints to design from file "musicmp3.ucf" ...
ERROR:NgdBuild:755 - Line 2 in 'musicmp3.ucf': Could not find net(s) 'rxd' in
the design. To suppress this error use the -aul switch, specify the correct
net name or remove the constraint.
ERROR:NgdBuild:755 - Line 4 in 'musicmp3.ucf': Could not find net(s) 'clk' in
the design. To suppress this error use the -aul switch, specify the correct
net name or remove the constraint.
ERROR:parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "musicmp3.ucf".

Writing NGDBUILD log file "musicmp3.bld"...


The UCF file looks like :-

#PACE: Start of Constraints extracted by PACE from the Design
NET "rxd" LOC = "P202" ;
NET "pwm_output" LOC = "P110" ;
NET "clk" LOC = "P80" ;


The code goes like this :-

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_misc.all;
use work.functions.all;


ENTITY musicmp3 IS
PORT (
clk : IN std_logic;
RxD : IN bit;
PWM_output : OUT bit);
END musicmp3;

ARCHITECTURE translated OF musicmp3 IS

COMPONENT async_receiver
PORT (
clk : IN std_logic;
RxD : IN bit;
RxD_data_ready : OUT bit;
RxD_data : OUT bit_vector(7 DOWNTO 0);
RxD_endofpacket : OUT bit;
RxD_idle : OUT bit);
END COMPONENT;


SIGNAL RxD_data_ready : bit;
SIGNAL RxD_data : bit_vector(7 DOWNTO 0);
SIGNAL RxD_data_reg : bit_vector(7 DOWNTO 0);
SIGNAL tmp : bit_vector(7 DOWNTO 0);
SIGNAL PWM_accumulator : bit_vector(8 DOWNTO 0);
SIGNAL PWM_output_xhdl1 : bit;


BEGIN
PWM_output <= PWM_output_xhdl1;
deserialer : async_receiver
PORT MAP (
clk => clk,
RxD => RxD,
RxD_data_ready => RxD_data_ready,
RxD_data => RxD_data);


PROCESS
BEGIN
WAIT UNTIL (clk'EVENT AND clk = '1');
IF (RxD_data_ready = '1') THEN
RxD_data_reg <= RxD_data;
END IF;
END PROCESS;


PROCESS
VARIABLE s : BIT_VECTOR(7 downto 0);
VARIABLE DInt : INTEGER := 0;
VARIABLE EInt : INTEGER := 0;
BEGIN
WAIT UNTIL (clk'EVENT AND clk = '1');
-- PWM_accumulator <= "0" & PWM_accumulator(7 DOWNTO 0) + RxD_data_reg;

s := PWM_accumulator(7 DOWNTO 0);
DInt := to_integer(s);
EInt := to_integer(RxD_data_reg);

DInt := DInt + EInt;

PWM_accumulator <= to_bit(9, DInt);

END PROCESS;
PWM_output_xhdl1 <= PWM_accumulator(8) ;

END translated;


What can be wrong? Thanks in advance


Assign a signal to the output and the optimizer won't remove your logic.
Click to expand...
You must have an error saying your FPGA is empty.

Regards
Thomas
 
Eli Bendersky wrote:

When I'm designing the code and simulating it, these long counters
are impossible. Running even 10 ms in Modelsim on a large design
takes a lot of time, not mentioning seconds. So, my approach so far has
been to cut these counters, for simulation.
Click to expand...
Consider inferring the counters from code.
Simulate the code before synthesis.
Modelsim runs more quickly in this case.

Since your design
is synchronous, you can verify timing statically
after place and route without using modelsim.

-- Mike Treseler
 
"Yaseen Zaidi" <yaseenzaidi@NETZERO.com> wrote in message
news:a31921fc.0410242057.2fbe3c42@posting.google.com...
Hello there,

I've got a hard-wired asyncrhonous reset coming into GCK on a Spartan
XC2S200 device. The reset is used within three different processes in
Click to expand...
I you must instantiate a IBUFG on the reset signal in your hdl code in order
to use GCK as non clock signal. Xilinx Spartan3 Starterkit (designed by
Digilent) has this kind of problem that reset is connected to global clock.
Instantiating IBUFG fixes the mapper problem for it.

Antti
 
Eli Bendersky a écrit:
Hi all,
[...]
I seek some methodology that will help me with this. No doubt, it's a
problem people run into all the time. Should I define
a package with all the counters in it, and modify all-at-once ? What
are the approaches to handling this ?
Click to expand...
Hello
I use a generic parameter, usually called "fast_sim", and shorten the
count-periods whan its value is true. At the top level, this parameter
is false by default but the testbench overrides this so that the
parameter is true for simulation

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/
 
Eli Bendersky wrote:

What do you mean by "inferring the counters from the code" ??
Click to expand...
I mean n_v := n_v + 1; in a synchronous process
rather than instancing a vendor core/netlist.
Synth code sims faster than a primitive netlist.
Variables sim faster than signals.
If it's still too slow, use Mr Mantinge's advice
of a generic switch that defaults to the synth value.

-- Mike Treseler
 
Mike Treseler a écrit:
use Mr Mantinge's advice
Click to expand...
It's 'Matringe', actually :eek:)


--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/
 
Michel Bieleveld wrote:

I have a problem, as far as I know procedures can change
signals/variables as long as the procedures are defined within the
scope where the variables are defined.
Click to expand...
Variables must be passed a parameters to a procedure.

It seems like that the
variables within the procedure do not change the variable outside the
procedure
Click to expand...
If you pass the process variable, the procedure can change
its value. Variable scope is local to the procedure or process.
Pass the variable or use a signal.

-- Mike Treseler
 
Michel Bieleveld wrote:
But I thought the difference between (pure) functions and procedures
is that procedures can have side effects.
True
Click to expand...

In this case changing a
variable defined in the process from which I am calling the procedure.
Click to expand...
Yes, but only if the variable is passed from process scope
to procedure scope.

-- Mike Treseler
 
Yes, Xilinx has a simulation library for CoreGen. The quickest way to get
the correct answer would be to look on their web site. (I am at home and
don't have quick access to the directory structure to tell you where to find
what.) Actually, since it seems you've done the same thing with unisim
and/or simprim, you should be able to find the source very quickly. Yhey
are all in the same area; they all use the same command/script--just
different arguments for the compile.

Jason
"Jeremy Webb" <jeremy.webb@ieee.org> wrote in message
news:2bd56510.0410220956.712fd993@posting.google.com...
Hi.

I'm having issues simulating my design that uses a Xilinx
CoreGenerator core. I imported the XilinxCoreLib directory, but
ModelSim doesn't recognize the files as a library. Does anyone know if
Xilinx provides a pre-compiled ModelSim library similar to those for
unisim and simprim? Or, has anyone successfully simulated a Xilinx
Core in VHDL, for example a fifo?

Thanks,

Jeremy
Click to expand...
 
If you really need all the counts in the top entity
then the way you've done it can't be simplified much.
If the counts are used internally but not directly output
to pins, I would make them process variables.

-- Mike Treseler
 
rickman wrote:
john wrote:

Hello,

I have basic questions regarding sequential machines

Q.1: Is the following way is the right way to define sequential
machine?


There are many ways to implement a FSM (Finite State Machine). This one
is fine. But why do you only have four states, but use an 8 bit vector
to indicate state?



signal State : unsigned(7 downto 0);
signal nextstate : unsigned(7 downto 0);
constant E0 : unsigned(7 downto 0):="00000000";
constant E1 : unsigned(7 downto 0):="00000001";
constant E2 : unsigned(7 downto 0):="00000010";
constant E3 : unsigned(7 downto 0):="00000011";

Process (State,nextstate)
Begin

Case State is


When E0=
..............
nextstate<=E1;

When E1=
...............
nextstate<=E2;


When E2 =
...............
nextstate<=E3;
When E3=

................
nextstate<=E0;

When others =
nextstate <= E0;
End case;
End Process;

Process (DPR_CLK,State,nextstate)
Begin

If (CLK'event And CLK='1') Then

State <= nextstate;
End If;
End Process;
End DPR_ARCH;

------------------------------------------------------------------------------

Q.2: some times the sequential mahine loose its direction. like state
E0 to E2,
What would be the solution?


The code looks ok, so I would suspect some hardware issues. Do you have
clean power, clean clock. What board is this on? Does it work
correctly in simulation?



Q.3: And whats the difference between
When others =

nextstate <= E0;

AND
When others =

nextstate <= NULL;


This is not valid code unless you have defined NULL to be an 8 bit SLV
constant. You mean...

When others =
NULL;

This is like saying NOP. The compiler will interpret that as hold the
previous state which will infer a latch separate from the register you
are inferring in the clocked process. I don't think that is what you
want. This is also true if you fail to account for all the posible
synthesizable states of your signal. That means you don't have to
consider X's and U's, etc, but you have to consider all possible
combination of 1's and 0's.



When we power up the CPLD, then by default the cpld goes to the state
E0, if
we use
When others =

nextstate <= E0;


No, it can power up in state E1 and then procede through E2 and E3
before getting to state E0. You may not care, but the point is that you
are not resetting to state E0. Even if it reaches E0 after one clock
cycle, it first had to start in an invalid state on power up. To
initialize to a specified state, you need to add a reset signal of some
sort or specify an initial state. How to do this depends on your
tools.



or the state machine will never run if we use

When others =

nextstate <= NULL;
Please adivce me that I am right or wrong?


Again, this will create a latch from your process with the case
statement. And it will lock up in the invalid state.


------------------------------------------------------------------------------

Q.3 Is sequential machine is the only best way to generate the cycles
for reading and
writing the Memory or is there an another way to do it?


This FSM is just a counter. Why not use a counter?
Click to expand...
you can also write it like this

http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/vtex9.html
 
On 28 Oct 2004 14:54:44 -0700, Eric Smith
<eric-no-spam-for-me@brouhaha.com> wrote:

CORDIC can easily be used for angles in units other than radians, as
well. I usually use angles measured as a fraction of a unit circle,
e.g., radians/2*pi. I've heard various names proposed for such a
unit of angular measure, but nothing seems definitive.
Click to expand...
Heh. Points. There are 32 points around the unit circle.

- Brian
(N, N by W, WNW, NW by N, NW, NW by W, ... :)
 
thomas wrote:
you can also write it like this

http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/vtex9.html
Click to expand...
I noticed that this doc puts the FSM case statement into a clocked
process. This will work fine if you don't mind your output signals
being clocked (and therefor delayed). Otherwise it can be easier to use
a non-clocked process for the FSM case statement. Then you can define
outputs that depend on the current state and optionally the inputs
(Mealy vs. Moore). Of course the downside is that a non-clocked process
requires you to specify the *entire* sensitivity list!

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
andy wrote:
I am coding an architecture wth a block statement
Click to expand...
If this isn't homework,
then
consider using processes
or entity instances instead of blocks;
else
http://groups.google.com/groups?q=vhdl+block+statement+begin
end if; -- Mike Treseler
 
andy wrote:

ARCHITERCURE struct OF myent IS

...

BEGIN
...
b1: BLOCK IS

i_comp1: conmp1
PORT MAP (....)
BEGIN

END;

END struct;

and I cannot conmpile such

CONFIGURATION myent_struct_conf OF myent
FOR i_comp1: comp1
USE CONFIGURATION work.comp1_conf
END FOR;
END CONFIGURATION;
Click to expand...
The block statement has to be considered:
http://www.microlab.ch/courses/vlsi/vhdl-ieee/TUTORIAL/IEEE/HTML/1076_1.HTM#1.3.1

So (without testing it) the following should be o.k.:

CONFIGURATION myent_struct_conf OF myent
FOR b1:
FOR i_comp1: comp1
USE CONFIGURATION work.comp1_conf
END FOR;
END FOR;
END CONFIGURATION;


Ralf
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top