Clock Edge notation

Hongtu wrote:

whenever I use modelsim to start simulation, the memory uesed by modelsim
will exceed 4G memory, and modelsim crashs. I am using Sun server with 16G
RAM. Can anyone tell me whether it is the problem of my design or the bug with
modelsim. Is there another way to write memory simulation model that uses much
less memory during simulation?
Click to expand...
If the array is sparse you could dynamically reserve the memory. Also use variable
instead of signal for the array, because signal has much more state and consumes more
memory.

You could also use bit* types because they have less states than std_logic type.

And if you want to use 64b modelsim you need to install that separately and set the
scripts accordingly. 64b modelsim is not normally used, because it is ~25%
slower than the 32b version.

--Kim
 
Weng Tianxiang wrote:
I would like to know which logic is best in ASIC implementation for
following equation in schematics entry:

B <= not (A1 and A2 and ... and A16);

The best solution for speed is using one large NAND with 16 inputs or
anything else?
Click to expand...
Don't worry too much about such things. In general Synopsys is more than
capable of making that decision for you. You can help Synopsys a tad
though, by creating a bit of an AND tree using (). It's most likely
Synopsys will use 2 or 4 input ANDs, so something like
B <= not ((((A1 and A2) and (A3 and A4) and ((A5 and A6) and (A7 and A8)))
and (((A9 and A10) and (A11 and A12)) and ((A13 and A14) and (A15 and
A16))))

Regards,

Pieter Hulshoff
 
Have you considered creating pages at opencores.org for
your cores? To me it looks as if opencores.org is the place where
one can find the most free cores in one place.

Wishbone-compliant versions would be nice as well, since
Wishbone seems to be more widespread than Amba among free cores and
would ease integration.

Thanks for releasing these great cores under a free license.

Philipp
 
In article <b8a9a7b0.0410052245.2b68cfb0@posting.google.com>,
ALuPin <ALuPin@web.de> wrote:
Hi,

I have the following problem:

When I archive my project on disk H
there are user libraries defined for the project which are
also on H.

When I run the .qar-file everything is ok (I have copied the archived
project to disk E). But how can I manage that the user libraries are
not linked to H anymore?
I mean if I want to safe a running system and make some tests on the
design on H or on the user libraries on H then I would not have the
original design anymore.

That is how can I freeze everything of the original design?
Click to expand...
You could just make a copy of the whole directory tree so you save every
file involved.

Obviously you have to save the source *.vhd files. You also have to save
the *.qar and the *.acf (I think).

If you copy them back in, you have to "touch" them so that they are newer
than the compiled results. If you don't Quartus may not recompile them.

--
--
kensmith@rahul.net forging knowledge
 
Raghavendra wrote:
Hi all,
Flip flop differs from a latch because of edge detection
circuit.How edge detection circuit is implemented.
Click to expand...
By two latches in succesion, the first has an active low enable
(transparant while its enable is low), the second active high. These two
latches form a so called master-slave pair.

Google is your friend. See e.g.
http://bwrc.eecs.berkeley.edu/Classes/ICDesign/EE141_f03/Lectures/Lecture24-Sequential.pdf

Paul.
 
Paul Uiterlinden wrote:
Raghavendra wrote:

Hi all,
Flip flop differs from a latch because of edge detection
circuit.How edge detection circuit is implemented.


By two latches in succesion, the first has an active low enable
(transparant while its enable is low), the second active high. These two
latches form a so called master-slave pair.

Google is your friend. See e.g.
http://bwrc.eecs.berkeley.edu/Classes/ICDesign/EE141_f03/Lectures/Lecture24-Sequential.pdf


Paul.
One Flip-flop is enough if your input signal is synchronous with the clock.
Click to expand...

Best regards,
Laurent
www.amontec.com
 
Weng Tianxiang wrote:
Hi,
I would like to know which logic is best in ASIC implementation for
following equation in schematics entry:

B <= not (A1 and A2 and ... and A16);

The best solution for speed is using one large NAND with 16 inputs or
anything else?
Click to expand...
Once again, recursion is the answer:

-- done in a recursively called function.
function and_reduce (arg : std_logic_vector )
return std_logic is
variable Upper, Lower : std_logic;
variable Half : integer;
variable BUS_int : std_logic_vector ( arg'length - 1 downto 0 );
variable Result : std_logic;
begin
if (arg'LENGTH < 1) then -- In the case of a NULL range
Result := '1'; -- Change for version 1.3
else
BUS_int := to_ux01 (arg);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := BUS_int ( BUS_int'right ) and BUS_int ( BUS_int'left );
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := and_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := and_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := Upper and Lower;
end if;
end if;
return Result;
end;

function nand_reduce (arg : std_logic_vector )
return std_logic is
begin
return not and_reduce (arg);
end;

This will give you the most efficient possible synthesis.
Most tools will make an efficent synthesis of this, but if you
are using one of the "built in" synthesis tools you are best
holding it's hand.
 
gda wrote:
what are the differences between RISC processor and CISC processor?
Click to expand...
Reduced Instruction Set Computer versus
Complex Instruction Set Computer

Have a look at the instruction set at assembler level - read the
assembler manual. Take two examples for each category. A Z80 may be a
good choice for CISC and MSP430 a good one for RISC.

Ralf
 
I want to know why 16 input NAND is inferior to 2 levels of 4 input
equivalent logic in terms of speed.

Could you please give me an explanation.
Click to expand...
A first guess would be :

Look at the N-Mos tree

__|
--||__
|
__|
--||__
|
.
.
.
__|
--||__
|
__|
--||__
|


Each MOS gate threshold is relative to it's source potential.
Now, the potential difference between source and drain of all
theses MOS is not zero ...
Let's say they are 0.1v.
The sixteenth MOS will have a threshold voltage 1.5v above the
first one ...

(totally arbitrary numbers ...)


Sylvain
 
I want to know normally what a suggested max number of inputs for a NAND device is.
Click to expand...
I'd look at what your ASIC manufacturer is offering you.

Theorically, it doesn't offers you interconnected MOS, but a NAND gate and you
don't know about the non-symetry or whatever caracteristics the in/out have.
All you know is that they are "good enough" so that it effectivly behave like
a NAND.

If you manufacturer offers you a 16 NAND gate guaranted for the same delay as a
2 NAND gate, I'd go for it ...

As all others told, you must look at what they offer you.


Sylvain
 
What I really want to do is to write 2 patents, one of which needs a
NAND of 19 inputs, another of N inputs. What should I correctly draw
in schematics entry without leaving any legal loopholes in the future?
In 19 input case, there are several combinations of optimized logics:
first level: 2*9, 3*5+4, 4*4+3, 5*3+4, 6*3.

Any suggestions are welcome.
Click to expand...
Well, I guess that you can just note a 19 input black box implementing a NAND.

I don't have any legal competence except common sense, but if implementing
the NAND as 2 9 inputs ones allows a competitor to copy your whole design
just changing that, that's just plain stupid !



Sylvain
 
Weng Tianxiang wrote:
Tom,
Thank you and others.

What I really want to do is to write 2 patents, one of which needs a
NAND of 19 inputs, another of N inputs. What should I correctly draw
in schematics entry without leaving any legal loopholes in the future?
In 19 input case, there are several combinations of optimized logics:
first level: 2*9, 3*5+4, 4*4+3, 5*3+4, 6*3.

Any suggestions are welcome.
Click to expand...
For something as important as a patent, you need to consult a patent
expert. If you want my limited knowledge on the matter, you want to
make a patent as general as possible. If the implimentation of the NAND
function is not important to the patent, then just make it a box
implementing a NAND function without specifying the details. The more
you spec, the easier it will be to work around the patent.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
Eric Smith wrote:
Raghavendra wrote:
Flip flop differs from a latch because of edge detection
circuit.How edge detection circuit is implemented.

Paul Uiterlinden <no@spam.nl> writes:
By two latches in succesion, the first has an active low enable
(transparant while its enable is low), the second active high. These
two latches form a so called master-slave pair.

That's how the pulse-triggered flip-flops worked, but that technique has
not been in common use for a long time. It is not truly edge-sensitive,
because it is sensitive to input changes during the entire low period of
the clock, not just a narrow window near the rising edge.
Click to expand...
I'm not clear why you say it is "sensitive" to input changes in the low
clock period. The input can change many times while the clock is low,
but only the last state of the input before the clock rises will be
remembered by the first latch and therefore by the second latch which is
the output.


One of the earliest true edge-triggered D flip-flops was the SN7474.
There's a logic diagram at the bottom right of the first page of the
TI data sheet, which can be found here:
http://focus.ti.com/docs/prod/folders/print/sn7474.html

It's a little tricky to understand; it is helpful to redraw the
logic diagram with the asynchronous preset and clear inputs omitted.
I haven't found any good written description of how it works, but
there's probably one in a digital design textbook somewhere.

An example of an edge-triggered J-K/ flip-flop is the SN74109. There's
a logic diagram in its data sheet as well.
Click to expand...
--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
In article <qhekk8vesk.fsf@ruckus.brouhaha.com>,
Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote:
Raghavendra wrote:
Flip flop differs from a latch because of edge detection
circuit.How edge detection circuit is implemented.

Paul Uiterlinden <no@spam.nl> writes:
By two latches in succesion, the first has an active low enable
(transparant while its enable is low), the second active high. These
two latches form a so called master-slave pair.

That's how the pulse-triggered flip-flops worked, but that technique has
not been in common use for a long time. It is not truly edge-sensitive,
because it is sensitive to input changes during the entire low period of
the clock, not just a narrow window near the rising edge.
Click to expand...
I think someone didn't read carefully before posting. The master/slave
flip flop does implement the edge triggered logic.


There's a logic diagram at the bottom right of the first page of the
TI data sheet, which can be found here:
http://focus.ti.com/docs/prod/folders/print/sn7474.html
Click to expand...
The 7474 is a slightly tricky master-slave circuit. The tricky bit is
that the power connection of the master is driven by a transistor running
from the clock input. The master section is only powered as a flip-flop
when the clock is high. When the clcok is low, the base of one transistor
or the other is pulled low depending on the state of the D input.

--
--
kensmith@rahul.net forging knowledge
 
Weng Tianxiang wrote:

I want to know normally what a suggested max number of inputs for a NAND device is.
Click to expand...
Your synthesis tool will decide, what fits best. Even if you have a 100
bit NAND, it will create a bunch of combinational logic, that just
computes this operation - but, as easily can be seen, not with a single
NAND.

In typical ASIC libraries bigger gates have a higher delay than smaller
ones (have a look at the vital description of you library). Therefore
even if you describe a 8 bit NAND the compiler may say "no way" and
infer a block of smaller and faster gates for the desired function.

Ralf
 
Paul Uiterlinden <no@spam.nl> writes:
By two latches in succesion, the first has an active low enable
(transparant while its enable is low), the second active high. These
two latches form a so called master-slave pair.
Click to expand...
I wrote:
That's how the pulse-triggered flip-flops worked, but that technique has
not been in common use for a long time. It is not truly edge-sensitive,
because it is sensitive to input changes during the entire low period of
the clock, not just a narrow window near the rising edge.
Click to expand...
kensmith@green.rahul.net (Ken Smith) writes:
I think someone didn't read carefully before posting. The master/slave
flip flop does implement the edge triggered logic.
Click to expand...
Quoting from "The Art of Digital Design" by Prosser and Winkel,
Second Edition, Chapter 4:

The master-slave flip-flop appears to be an attractive edge-driven
device. Why are we not content with this design? Because the
master flip-flop is still a 1's catcher during the positive half
of the clock cycle. This means that R and S must stabilize during
the negative half of the clock, since the master flip-flop will
react to any T glitches during the positive clock phase. We could
greatly simplify our digital circuit designs if we could eliminate
the 1's-catching behavior. We need a flip-flop that samples its
inputs only on a clock edge and changes its outputs only as the
result of the clock edge. Such a device is called a <i>pure edge-
driven flip-flop</i>.

Unfortunately the authors do not explain the construction of such
a device, though the 7474 and 74109 are real-world examples of it.

Metastability is not explained until Chapter 12.

The 7474 is a slightly tricky master-slave circuit.
Click to expand...
The 7474 is not a master-slave flip-flop. It actually contains three
S-R flip-flops in a non-obvious configuration, very much unlike what
Paul Uiterlinden described.
 
hakim wrote:

so here goes! I have multiple processes within an architecture of a
VHDl entity that writes to common signals. I understand that this is a
case of multiple drivers and that it is incorrect to have two
processes drive diff values on the signals simultaneously.
but i precisely know how my process executions overlap and am sure
that no two process will drive values at the same time. As in, if one
drives either 0 or 1 on the signal, all others are definitely driving
a 'Z' (or basically tristated).
Click to expand...
A tri-state driver is described with:

process(enable,data_in)
begin
if (enable='1') then
data_out<=data_in;
else data_out<=(others=>'Z');
end if;
end process;

Make it easy for the synthesis tool and use this tri-state description
explictly. (In other words: write in a biger process to a dummy signal
(data_in) and gate this dummy signal in an extra tri-state driver.)

data_out must be a resolved data type (std_logic(_vector)). You may
write to data_out from many tri-state describing processes.

Make sure, that your target supports tri-state drivers.

Ralf
 
rickman wrote:

I'm not clear why you say it is "sensitive" to input changes in the low
clock period. The input can change many times while the clock is low,
but only the last state of the input before the clock rises will be
remembered by the first latch and therefore by the second latch which is
the output.
Click to expand...
I agree. The master latch(mux) is enabled by the constant clock.
The data setup requirement is to the rising edge, where
the slave latch(mux) is enabled. This is exactly how the
Actel ACT1 devices made D-flops.

-- Mike Treseler
 
Eric Smith wrote:

Quoting from "The Art of Digital Design" by Prosser and Winkel,
Second Edition, Chapter 4:

The master-slave flip-flop appears to be an attractive edge-driven
device. Why are we not content with this design? Because the
master flip-flop is still a 1's catcher during the positive half
of the clock cycle.
Click to expand...
They are either talking about a different circuit, or they
got it wrong. The master latch(mux) follows the D input
input, but the only "catching" behavior is at the rising
clock edge when the master data passes to the slave latch(mux).

-- Mike Treseler
 
hakim wrote:

that no two process will drive values at the same time. As in, if one
drives either 0 or 1 on the signal, all others are definitely driving
a 'Z' (or basically tristated).
Click to expand...
Use a mux structure to combine your outputs
in a single process. FPGAs of recent vintage
do not allow internal tri-state nodes.

-- Mike Treseler
 
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