PLL tricks

[Bill Sloman]

On 28/09/2014 7:26 AM, Phil Hobbs wrote:

On 9/27/2014 3:14 PM, rickman wrote:
On 9/27/2014 1:54 PM, Phil Hobbs wrote:
On 9/26/2014 10:24 PM, rickman wrote:
On 9/26/2014 7:58 PM, Phil Hobbs wrote:
On 9/26/2014 1:57 PM, rickman wrote:
On 9/26/2014 1:13 PM, Phil Hobbs wrote:
On 9/26/2014 10:53 AM, Bill Sloman wrote:
On 26/09/2014 11:08 PM, Phil Hobbs wrote:
On 9/26/2014 3:02 AM, rickman wrote:
On 9/25/2014 10:26 PM, Ralph Barone wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:
Den torsdag den 25. september 2014 18.10.53 UTC+2 skrev John
Larkin:
On Thu, 25 Sep 2014 09:43:14 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 25.09.2014 um 04:40 schrieb John Larkin:

<snip>

And the rest??? Doesn't that have NRE design costs?

Not on the same scale at all. One can design a PLL on a napkin in a few
minutes. The parlour tricks are (1) analogue conditioning of the 10
MHz; (2) resampling the divider output to get rid of its jitter and
timing drift; (3) characterization when you're done. All three of those
things still have to be done with the FPGA approach.

Not exactly.

You need a whole lot less analog conditioning of the 10MHz input,
because you can rely on the digital filtering to get rid of most of the
analog noise.

You don't have to resample any divider output, because that job's done
numerically.

Characterisation is always necessary.

Methinks he doth protest *too* much. I also think you are hand waving
now.

Nope. I've done similar things both ways. What exactly did you not
agree with, and why?

Actually the need for analog conditioning the 10 MHz is greatly reduced
in the digital approach as this can be done in the digital domain. There
is *no* need to resample anything in the digital approach.

You have an exaggerated idea of the timing coherence of ADCs and FPGAs
over temperature, then.

The A/D converter is going to be in the same ball-park as the comparator
and D-type flip-flop that John Larkin wants to use.

The FPGA is operating on sampled data, so it's propagation delays don't
come into it.

Logic slows down significantly with increasing
temperature, and a picosecond is not a long time. You may think I'm
arm-waving, but I haven't seen a lot of carefully supported numerical
estimates from you--just a lot of generalities. You also haven't
addressed my point about DSP standing or falling by the exact equal
spacing of the data samples, which ISTM is fatal to your view.

The 155.52MHz VCXO delivers data samples as equally spaced as you can
get from anything short of an atomic clock. The samples don't fit neatly
into the 10MHz period, but there are digital signal processing schemes
that can cope with that. Non-linear mulitparameter least square curve
fitting would be a gross over-kill, but it makes the point.

As for the rest, the 10 MHz will have to be cleaned up in analogue
somehow, because otherwise its jitter will show up in the FPGA's
output--the analogy between DSP and real genuine analogue signal
processing stands or falls by the samples being evenly spaced.
Most of the time that's not such a worry, but for 1 ps timing accuracy, it
most emphatically is.

Not sure which 10 MHz you are talking about, from the bang bang
detector or the signal processing based approach. I'm not sure why
there would be a 10 MHz signal in the signal processing approach.

Because that's what you're locking to, of course.

Oh, you mean the reference clock... The DSP can do a lot of "cleaning
up". Once you are in the digital domain this comes without all the
analog vagaries.

How _exactly_ would you clean up the clock you're locking to in the
digital domain, without depending on the reference or VCXO for
essentially ideal sampling? Analogue bandpass filters, I understand.
AFAICT your proposal is "pay no attention to the man behind the curtain!"

You may understand analog bandpass filters, but you do seem to be weaker
on digital filtering.

One way of working would be to fit successive 1000 sample chunks of data
as if the VCXO were running at exactly 155.52MHz and the reference was
exactly 10MHz, and extract absolute phase. The shift in absolute phase
from one chunk to the next is your frequency error, delivered at
15.552MHz. Since the 155.52MHz is unlikely to be more than +/-100ppm off
- as delivered from the manufacturer - there won't be enough phase creep
over 1000 samples to mess up simple-mind - DFT - phase extraction.

You might have to interpolate one sample per chunk to create the effect
of an integral number of samples. I'd leave that to the number-crunching
experts.

--
Bill Sloman, Sydney

 

[rickman]

On 9/28/2014 1:01 AM, John Larkin wrote:

On Sat, 27 Sep 2014 21:08:28 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

On Saturday, September 27, 2014 9:24:33 PM UTC-4, John Larkin wrote:
On Sat, 27 Sep 2014 16:40:59 -0700 (PDT), dagmargoo...@yahoo.com wrote:
On Saturday, September 27, 2014 6:33:53 PM UTC-4, John Larkin wrote:

[time-trim DAC before 10MHz digitizer]

That's the time equivalent of adding a ripple-removing waveform to the
phase comparator output.

I don't think so. The bangbang pd only acquires a limited amount of
information, namely 80 Kbits/sec. There's nothing we can add
downstream of that to increase the info (or decrease the noise.) If we
enable more comparison edges, we get more info to work with; or. for
the same loop filter, less noise at its output.

I meant that you could, alternatively, pass those same reference edges
through the phase detector, producing a periodic ripple, and cancel
that (and the artifacts from unequal sampling intervals) with a
periodic ripple-cancelling waveform.

I don't think that works. The edges that are 100 ps early always make
a 0, and the edges that are 100 ps late always make a 1, so they add
ripple but no useful phase-error information. They only help if they
are moved into the zero-time window.

The single-test bangbang PD has a transfer function like

---------------------
/
/
/
---------
^
clk


so we want to shift the new non-phase-0 tests in time so that they add
in their linear ranges.


---------------------
/
/
/
---------


---------------------
/
/
/
---------


---------------------
/
/
/
---------
^
clk

not


---------------------
/
/
/
---------


---------------------
/
/
/
---------------


---------------------
/
/
/
---------------------
^
clk


The reason I like my idea, aside from it being my idea, is that it's
simple, flexible, and I know it will work.

You make a valid point about the ripple canceling not working. But how
will you adjust the timing of the clock edge so well that it will be
useful? Are you really thinking of biasing the rising edge of the
squared up 10 MHz clock? This seems like a point in the circuit that is
not very well defined to be treating as an analog signal.

Why not adjust the reference voltage of the comparator? Then you are
working with a well defined slope of the 10 MHz sine wave and can make
predictable adjustments.

What is the rise time of the comparator output you plan to use?

--

Rick

 

[DecadentLinuxUserNumeroUn]

On Sat, 27 Sep 2014 19:45:17 -0400, rickman <gnuarm@gmail.com> Gave us:

That wouldn't last long. This crowd would get thrown out of any bar I
would want to frequent. lol

Yer just jealous because you can't shoot pool worth a shit, even
though all you drink is soda.

 

On Sunday, September 28, 2014 1:01:02 AM UTC-4, John Larkin wrote:

On Sat, 27 Sep 2014 21:08:28 -0700 (PDT), dagmargoo..@yahoo.com wrote:

I meant that you could, alternatively, pass those same reference edges
through the phase detector, producing a periodic ripple, and cancel
that (and the artifacts from unequal sampling intervals) with a
periodic ripple-cancelling waveform.

I don't think that works. The edges that are 100 ps early always make
a 0, and the edges that are 100 ps late always make a 1, so they add
ripple but no useful phase-error information. They only help if they
are moved into the zero-time window.

You're right. I was (wrongly) thinking "edge-triggered" instead of
"sampled."

So, with complicated logic, you can select extra reference edges to use
in guiding the VCXO, in addition to the edges that line up every 12.5uS.

That certainly gives more phase information, updated more frequently.

The D-flop-as-phase-detector has the very attractive quality of being a
fast, well-defined, hopefully non-drifty delay.

Cheers,
James

 

[Bill Sloman]

On Sunday, 28 September 2014 16:05:16 UTC+10, dagmarg...@yahoo.com wrote:

On Sunday, September 28, 2014 1:01:02 AM UTC-4, John Larkin wrote:
On Sat, 27 Sep 2014 21:08:28 -0700 (PDT), dagmargoo..@yahoo.com wrote:

I meant that you could, alternatively, pass those same reference edges
through the phase detector, producing a periodic ripple, and cancel
that (and the artifacts from unequal sampling intervals) with a
periodic ripple-cancelling waveform.

I don't think that works. The edges that are 100 ps early always make
a 0, and the edges that are 100 ps late always make a 1, so they add
ripple but no useful phase-error information. They only help if they
are moved into the zero-time window.

You're right. I was (wrongly) thinking "edge-triggered" instead of
"sampled."

So, with complicated logic, you can select extra reference edges to use
in guiding the VCXO, in addition to the edges that line up every 12.5uS.

That certainly gives more phase information, updated more frequently.

But not as much information as a linear phase detector, such as a product detector - say an AD834 - or a switching detector which can be as simple as a long-tailed pair. If you don't want a full-scale range of 100nsec, use more complicated switching waveforms and a long-tailed triple to ignore the stuff going on outside the +/-6.43nsec window of interest.

The D-flop-as-phase-detector has the very attractive quality of being a
fast, well-defined, hopefully non-drifty delay.

But it's got more delay than simpler circuits and it's fatally non-linear.

--
Bill Sloman, Sydney

 

[Bill Sloman]

On Sunday, 28 September 2014 16:05:16 UTC+10, dagmarg...@yahoo.com wrote:

On Sunday, September 28, 2014 1:01:02 AM UTC-4, John Larkin wrote:
On Sat, 27 Sep 2014 21:08:28 -0700 (PDT), dagmargoo..@yahoo.com wrote:

I meant that you could, alternatively, pass those same reference edges
through the phase detector, producing a periodic ripple, and cancel
that (and the artifacts from unequal sampling intervals) with a
periodic ripple-cancelling waveform.

I don't think that works. The edges that are 100 ps early always make
a 0, and the edges that are 100 ps late always make a 1, so they add
ripple but no useful phase-error information. They only help if they
are moved into the zero-time window.

You're right. I was (wrongly) thinking "edge-triggered" instead of
"sampled."

So, with complicated logic, you can select extra reference edges to use
in guiding the VCXO, in addition to the edges that line up every 12.5uS.

That certainly gives more phase information, updated more frequently.

But not as much information as a linear phase detector, such as a product detector - say an AD834 - or a switching detector which can be as simple as a long-tailed pair. If you don't want a full-scale range of 100nsec, use more complicated switching waveforms and a long-tailed triple to ignore the stuff going on outside the +/-6.43nsec window of interest.

The D-flop-as-phase-detector has the very attractive quality of being a
fast, well-defined, hopefully non-drifty delay.

But it's got more delay than simpler circuits and it's fatally non-linear.

--
Bill Sloman, Sydney

 

[Kevin Aylward]

"John Larkin" wrote in message
news:4qie2alha115etc597v39e52nvrtnvav0t@4ax.com...

Consider this:

If we square up the 10 MHz reference, and the 155.52 MHz oscillator
were somehow locked to it, the edges line up at 80 KHz, namely every
12.5 us. So the bangbang phase detector only delivers one bit of
information (namely early/late) 80K times per second. That may be too
noisy to discipline a cheap 155 MHz VCXO.

Why not just use a non-cheap 155.52 MHz VCXO?

There aren't all that many 155.52's around.

Correct, but there are wades of exact 38.88 MHz and 19.44 MHz XTAL VCXOs
about. I know, my current OSC ASIC uses them

There are also x4 multiplier chips that are designed to solve this
particular 155.52 MHz problem from those frequencies.

This is bog standard. Obtain a 155.52 MHz VCXO from a (tank) multiplied up
from 38.88 MHz or 19.44 MHz VCXO

Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

 

[Bill Sloman]

On 28/09/2014 2:11 PM, rickman wrote:

On 9/27/2014 8:11 PM, Bill Sloman wrote:
On Sunday, 28 September 2014 08:33:53 UTC+10, John Larkin wrote:
On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin
jlarkin@highlandtechnology.com> wrote:

snip

I was going to have a time trim DAC for temperature compensation
anyhow, so this is almost free. The DAC doesn't need to be super fast,
since the near-miss events are fairly scattered in the 1944-state
space.

Your "time-trim DAC" probably ought to be an MC100EP195, as has been
proposed earlier.

http://www.onsemi.com/pub_link/Collateral/MC10EP195-D.PDF

The catch is visible in Figure 4 of that data sheet. While the part
offers a nominally 10psec granularity over a delay range which starts
anywhere from 1.65 to 2.75nsec and can be as long as 9.5 to 15.8nsec,
the actual delay varies from part to part, and with temperature. The
temperature drift is about 15psec/degree Celcius on the longest delay.

If you use the part to set up a mark-to-space ratio at constant
frequency and digitise the DC value of the filtered waveform, you can
calibrate the delay with considerable precision and very rapidly -
when I worked out a scheme it looked as if we could have measured
every delay within a few milliseconds, though that was for the
MC100E195 which was a 7-bit rather than an 10-bit device.

That is not what he has drawn on his napkin.

Whence my "probably ought to be". As you say, he doesn't seem to have
thought about his "time trim DAC" in any detail. I was doing a lot of
that in 1988 and 1989, and the scars a still with me.

He seems to be summing a
bias voltage to the differential 10 MHz square wave to adjust the point
on the rising edge that crosses the threshold in the D-FF. This is
applying assumptions to the analog nature of both the D-FF inputs and
the comparator outputs. Clearly this is intended to be a fine
adjustment as it can only work over the rise time of the digital
differential signal.

You tend to need to set up are fairly linear and predictable ramp to
make it work. We didn't find that too difficult - we were doing fine
interpolation on an 800MHz clock, which meant that we needed to have at
least 1.25nsec of straight and ripple-free ramp - which meant that the
ramp was closer to 2.5nsec long. There were a couple of DACs to get the
DC levels and slope correct, and regular automatic measurement and
correction to keep them correct. Happily we were running a pair of
timing cards, and could use one to calibrate the other.

The device you link to is one (or one very like it) used by a friend in
a unit he built for the Naval Observatory to provide a 1 PPS output from
their newest atomic clock. Seems this clock uses a 100 MHz output as
it's timing reference.

Have you looked at the way they work? The Rubidium standard uses a
6,834.682,610.904 Hz microwave oscillator (6.9GHz) to hit the relevant
atomic hyperfine transition, and seems to get it by multiplying up a
suitable frequency from a quartz-crystal-based VCXO. Quite where an
MC100EP195 would fit into that isn't clear.

--
Bill Sloman, Sydney

 

[rickman]

On 9/28/2014 3:23 AM, Bill Sloman wrote:

On 28/09/2014 2:11 PM, rickman wrote:

The device you link to is one (or one very like it) used by a friend in
a unit he built for the Naval Observatory to provide a 1 PPS output from
their newest atomic clock. Seems this clock uses a 100 MHz output as
it's timing reference.

Have you looked at the way they work? The Rubidium standard uses a
6,834.682,610.904 Hz microwave oscillator (6.9GHz) to hit the relevant
atomic hyperfine transition, and seems to get it by multiplying up a
suitable frequency from a quartz-crystal-based VCXO. Quite where an
MC100EP195 would fit into that isn't clear.

My friend didn't build the atomic clock. He built the 1 pps circuit. I
think I described it here once already. The clock has a 100 MHz output.
They have a number of atomic clocks with different accuracies and
receive signals from other clocks around the world. These are all fed
into a Kalman filter which appears to be able to improve its result
using even the poorer accuracy signals.

I guess the filter is using the 1 ppm signal because my friend's circuit
received the 1 ppm from the filter to pick an edge of the 100 MHz clock
to sync his 1 pps to. The circuit then applied a phase adjustment using
this chip (or another one like it) to get the 1 pps in sync with the
signal from the Kalman filter. I'm pretty sure once it was solidly in
sync with both the 100 MHz from the clock and the 1 pps from the Kalman
filter it was then used as one of the sources for the Kalman filter.

In the clock, how do they detect the difference in frequency of the
multiplied VCXO and the Rubidium transition?

--

Rick

 

[Tauno Voipio]

On 28.9.14 11:45, rickman wrote:

On 9/28/2014 3:23 AM, Bill Sloman wrote:
On 28/09/2014 2:11 PM, rickman wrote:

The device you link to is one (or one very like it) used by a friend in
a unit he built for the Naval Observatory to provide a 1 PPS output from
their newest atomic clock. Seems this clock uses a 100 MHz output as
it's timing reference.

Have you looked at the way they work? The Rubidium standard uses a
6,834.682,610.904 Hz microwave oscillator (6.9GHz) to hit the relevant
atomic hyperfine transition, and seems to get it by multiplying up a
suitable frequency from a quartz-crystal-based VCXO. Quite where an
MC100EP195 would fit into that isn't clear.

My friend didn't build the atomic clock. He built the 1 pps circuit. I
think I described it here once already. The clock has a 100 MHz output.
They have a number of atomic clocks with different accuracies and
receive signals from other clocks around the world. These are all fed
into a Kalman filter which appears to be able to improve its result
using even the poorer accuracy signals.

I guess the filter is using the 1 ppm signal because my friend's circuit
received the 1 ppm from the filter to pick an edge of the 100 MHz clock
to sync his 1 pps to. The circuit then applied a phase adjustment using
this chip (or another one like it) to get the 1 pps in sync with the
signal from the Kalman filter. I'm pretty sure once it was solidly in
sync with both the 100 MHz from the clock and the 1 pps from the Kalman
filter it was then used as one of the sources for the Kalman filter.

In the clock, how do they detect the difference in frequency of the
multiplied VCXO and the Rubidium transition?

The classical method is to sweep the VCXO slightly and observe the
changes in the Rb cell absorption. A servo balances the sweep to
be symmetrical about the sweet point.

IIRC, there was an article about it in an older HP Journal.

--

Tauno Voipio

 

[Bill Sloman]

On Monday, 29 September 2014 00:37:11 UTC+10, DecadentLinuxUserNumeroUno wrote:

On Sun, 28 Sep 2014 00:16:20 -0400, rickman <gnuarm@gmail.com> Gave us:
On 9/27/2014 11:26 PM, Bill Sloman wrote:

<snip>

Interesting analogy.

I am quite sure that we can leave it to you to fuck it up.

If this were a pool hall,

No one said anything about a pool hall. The reference was about
shooting pool. As in POOL SHOTS. You know... the physics of the game,
not your retarded social/anti-social crybaby bullshit.

Presumably one shoots pool in a pool hall, or some similar place containing pool tables. The original sophisticated reference to pool was yours

" Yer just jealous because you can't shoot pool worth a shit, even
though all you drink is soda. "

I'd likely find a place
where people follow the rules

You'll need to try a different planet for that one. Even our most
sophisticated and highly educated twerps in this world still think that
rules do not apply to them. There are hundreds of thousands of idiots
on the road each day, who still think that it being illegal to drive
with a cell phone shoved in their face does not apply to them.

They probably aren't sophisticated or highly educated - it doesn't
take much sophistication to appreciate that a cell phone - even hands
free - can be a dangerous distraction while driving.

more and know how to be courteous to one
another.

I am courteous to fellow men and women whom deserve it.

A slightly implausible claim.

> You didn't make the list, circus flea. Well over 80% of all Usenet users will not.

DecadentLinuxUserNumeroUno seems to share krw's conviction that he knows better than most other people. It doesn't strike me that he's correct, but other's opinions may differ.

But this isn't a pool hall.

So much for YOUR retarded analogy.

Heck, if it were there are a
number of folks here who would have been banned long ago.

Certainly all crybaby pussies first.

DecadentLinuxUserNumeroUno being the kind of crybaby pussy who
throws a hissy fit because people don't conform to the antiquated
usenet line-length rules, and require him to reformat their posts,
so that he can read them on his glass teletype.

In a pool hall no one cares how good you are if you only come to make
trouble all the time.

Make trouble?

You're an abject idiot suffering more from the various members of the
Zimmerman Complex family of mental disturbances than the asshole who's
actions the term was coined for.

You will fail to comprehend that one as well, however.

Would that be the George Zimmerman who shot Traynor Martin? Or do you have
some even more obscure reference in mind? Rickman isn't actually an abject
- or any other kind of - idiot, so your claim that he is is fair evidence
that your own judgment is less than sound.

It is all you have left to do in life. You are a lingerer.

Haven't you lingered long enough? Isn't that big chest grab in the
guy just waiting around for your next session on the porcelain throne?

DecadentLinuxUserNumeroUno can be charming when he puts some effort into it.

Sadly, he's still a reincarnation of AlwaysWrong.

--
Bill Sloman, Sydney

 

[Bill Sloman]

On Monday, 29 September 2014 02:00:38 UTC+10, John Larkin wrote:

On Sat, 27 Sep 2014 23:05:16 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:
On Sunday, September 28, 2014 1:01:02 AM UTC-4, John Larkin wrote
On Sat, 27 Sep 2014 21:08:28 -0700 (PDT), dagmargoo..@yahoo.com wrote:

I meant that you could, alternatively, pass those same reference edges
through the phase detector, producing a periodic ripple, and cancel
that (and the artifacts from unequal sampling intervals) with a
periodic ripple-cancelling waveform.

I don't think that works. The edges that are 100 ps early always make
a 0, and the edges that are 100 ps late always make a 1, so they add
ripple but no useful phase-error information. They only help if they
are moved into the zero-time window.

You're right. I was (wrongly) thinking "edge-triggered" instead of
"sampled."

So, with complicated logic, you can select extra reference edges to use
in guiding the VCXO, in addition to the edges that line up every 12.5uS.

It's not complicated. Just a RAM with DAC values and a couple of
flags. The DAC was going to be there already.

That certainly gives more phase information, updated more frequently.

Given that phase testing every 12.5 us may be marginal, it might be
good to at least allow a trick like this.

The D-flop-as-phase-detector has the very attractive quality of being a
fast, well-defined, hopefully non-drifty delay.

I can't think of anything more stable.

Sadly, being non-linear, it doesn't do much for the rest of the system.

Multiplying and switching phase detectors can be more or less linear and actually contain fewer components, which does help their stability, but if you don't want to think about that, I suppose you won't.

--
Bill Sloman, Sydney

 

[Bill Sloman]

On Monday, 29 September 2014 02:20:31 UTC+10, DecadentLinuxUserNumeroUno wrote:

On Sun, 28 Sep 2014 09:17:45 -0700 (PDT), Bill Sloman
bill.sloman@gmail.com> Gave us:

The original sophisticated reference to pool was yours

But NOT a pool hall, you stupid, illiterate twerp.

DecadentLinuxUserNumeroUno only plays pool in the pool room in his enormous mansion. He's too far above the rest of us to catch references to the kind of life the rest of us plebians live.

Admittedly " Yer just jealous because you can't shoot pool worth a shit, even
though all you drink is soda " doesn't sound like a reference to the kind of pool played in upper-class mansions, but what would I know about that - give or take an episode or two from "Downton Abbey"?

--
Bill Sloman, Sydney

 

[rickman]

On 9/28/2014 6:33 AM, Tauno Voipio wrote:

On 28.9.14 11:45, rickman wrote:

In the clock, how do they detect the difference in frequency of the
multiplied VCXO and the Rubidium transition?


The classical method is to sweep the VCXO slightly and observe the
changes in the Rb cell absorption. A servo balances the sweep to
be symmetrical about the sweet point.

IIRC, there was an article about it in an older HP Journal.

That would seem to create a bunch of jitter in the clock edges. I
suppose they have a second PLL that removes the jitter?

--

Rick

 

[DecadentLinuxUserNumeroUn]

On Sun, 28 Sep 2014 00:16:20 -0400, rickman <gnuarm@gmail.com> Gave us:

>On 9/27/2014 11:26 PM, Bill Sloman wrote:

snipped slotard's stupidity.

>Interesting analogy.

I am quite sure that we can leave it to you to fuck it up.

> If this were a pool hall,

No one said anything about a pool hall. The reference was about
shooting pool. As in POOL SHOTS. You know... the physics of the game,
not your retarded social/anti-social crybaby bullshit.

I'd likely find a place
where people follow the rules

You'll need to try a different planet for that one. Even our most
sophisticated and highly educated twerps in this world still think that
rules do not apply to them. There are hundreds of thousands of idiots
on the road each day, who still think that it being illegal to drive
with a cell phone shoved in their face does not apply to them.

more and know how to be courteous to one
another.

I am courteous to fellow men and women whom deserve it. You didn't
make the list, circus flea. Well over 80% of all Usenet users will not.

> But this isn't a pool hall.

So much for YOUR retarded analogy.

Heck, if it were there are a
number of folks here who would have been banned long ago.

Certainly all crybaby pussies first.

In a pool
hall no one cares how good you are if you only come to make trouble all
the time.

Make trouble?

You're an abject idiot suffering more from the various members of the
Zimmerman Complex family of mental disturbances than the asshole who's
actions the term was coined for.

You will fail to comprehend that one as well, however.

It is all you have left to do in life. You are a lingerer.

Haven't you lingered long enough? Isn't that big chest grab in the
guy just waiting around for your next session on the porcelain throne?

 

On Sunday, September 28, 2014 3:07:38 AM UTC-4, Kevin Aylward wrote:

"John Larkin" wrote:
dagmargoo...@yahoo.com wrote:
John Larkin wrote:

If we square up the 10 MHz reference, and the 155.52 MHz oscillator
were somehow locked to it, the edges line up at 80 KHz, namely every
12.5 us. So the bangbang phase detector only delivers one bit of
information (namely early/late) 80K times per second. That may be too
noisy to discipline a cheap 155 MHz VCXO.

Why not just use a non-cheap 155.52 MHz VCXO?

There aren't all that many 155.52's around.

Correct, but there are wades of exact 38.88 MHz and 19.44 MHz XTAL VCXOs
about. I know, my current OSC ASIC uses them

There are also x4 multiplier chips that are designed to solve this
particular 155.52 MHz problem from those frequencies.

Or just get a custom 155.52 MHz super-fine VCXO. I don't think they're
even very expensive, it's on the order of getting a custom crystal.

This is bog standard. Obtain a 155.52 MHz VCXO from a (tank) multiplied up
from 38.88 MHz or 19.44 MHz VCXO.

As someone who has made 908 MHz from 14.4MHz in production with a
multi-stage tank-based multiplier, I still don't understand how a
tank x4 multiplier can ensure John accurate phase.

You bang the tank and it rings--so far so good. But if the tank isn't
*perfectly* tuned, it rings off frequency, and the 'ring' cycles wander
off phase, right?

You'd need a varactor, phase-detector, and a feedback loop to keep the
tank tuned perfectly true, AFAICT, introducing additional problems on
several fronts.

ISTM a custom 155.52 MHz VCXO is literally rock-stable, provides the
best performance attainable, and eliminates a great deal of design
risk and nuisance.

If the best-attainable VCXO isn't good enough, it's still a better
starting place for any other measures that would come after.

Without giving away any secrets, can you indicate what I've missed?

Thanks,
James Arthur

 

[John Larkin]

On Sat, 27 Sep 2014 23:05:16 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

On Sunday, September 28, 2014 1:01:02 AM UTC-4, John Larkin wrote:
On Sat, 27 Sep 2014 21:08:28 -0700 (PDT), dagmargoo..@yahoo.com wrote:

I meant that you could, alternatively, pass those same reference edges
through the phase detector, producing a periodic ripple, and cancel
that (and the artifacts from unequal sampling intervals) with a
periodic ripple-cancelling waveform.

I don't think that works. The edges that are 100 ps early always make
a 0, and the edges that are 100 ps late always make a 1, so they add
ripple but no useful phase-error information. They only help if they
are moved into the zero-time window.

You're right. I was (wrongly) thinking "edge-triggered" instead of
"sampled."

So, with complicated logic, you can select extra reference edges to use
in guiding the VCXO, in addition to the edges that line up every 12.5uS.

It's not complicated. Just a RAM with DAC values and a couple of
flags. The DAC was going to be there already.

That certainly gives more phase information, updated more frequently.

Given that phase testing every 12.5 us may be marginal, it might be
good to at least allow a trick like this.

The D-flop-as-phase-detector has the very attractive quality of being a
fast, well-defined, hopefully non-drifty delay.

I can't think of anything more stable.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[John Larkin]

On Sun, 28 Sep 2014 08:07:38 +0100, "Kevin Aylward"
<ExtractkevinRemove@kevinaylward.co.uk> wrote:

"John Larkin" wrote in message
news:4qie2alha115etc597v39e52nvrtnvav0t@4ax.com...


Consider this:

If we square up the 10 MHz reference, and the 155.52 MHz oscillator
were somehow locked to it, the edges line up at 80 KHz, namely every
12.5 us. So the bangbang phase detector only delivers one bit of
information (namely early/late) 80K times per second. That may be too
noisy to discipline a cheap 155 MHz VCXO.

Why not just use a non-cheap 155.52 MHz VCXO?

There aren't all that many 155.52's around.

Correct, but there are wades of exact 38.88 MHz and 19.44 MHz XTAL VCXOs
about. I know, my current OSC ASIC uses them

There are also x4 multiplier chips that are designed to solve this
particular 155.52 MHz problem from those frequencies.

This is bog standard. Obtain a 155.52 MHz VCXO from a (tank) multiplied up
from 38.88 MHz or 19.44 MHz VCXO

Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

The X4 multiplier would have to produce edges that are strictly
periodic to picoseconds. Can that be done?

CTS does make a surfmount 155.52 fundamental VCXO that claims very low
jitter. Samples are coming, I think.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[John Larkin]

On Sun, 28 Sep 2014 13:33:50 +0300, Tauno Voipio
<tauno.voipio@notused.fi.invalid> wrote:

On 28.9.14 11:45, rickman wrote:
On 9/28/2014 3:23 AM, Bill Sloman wrote:
On 28/09/2014 2:11 PM, rickman wrote:

The device you link to is one (or one very like it) used by a friend in
a unit he built for the Naval Observatory to provide a 1 PPS output from
their newest atomic clock. Seems this clock uses a 100 MHz output as
it's timing reference.

Have you looked at the way they work? The Rubidium standard uses a
6,834.682,610.904 Hz microwave oscillator (6.9GHz) to hit the relevant
atomic hyperfine transition, and seems to get it by multiplying up a
suitable frequency from a quartz-crystal-based VCXO. Quite where an
MC100EP195 would fit into that isn't clear.

My friend didn't build the atomic clock. He built the 1 pps circuit. I
think I described it here once already. The clock has a 100 MHz output.
They have a number of atomic clocks with different accuracies and
receive signals from other clocks around the world. These are all fed
into a Kalman filter which appears to be able to improve its result
using even the poorer accuracy signals.

I guess the filter is using the 1 ppm signal because my friend's circuit
received the 1 ppm from the filter to pick an edge of the 100 MHz clock
to sync his 1 pps to. The circuit then applied a phase adjustment using
this chip (or another one like it) to get the 1 pps in sync with the
signal from the Kalman filter. I'm pretty sure once it was solidly in
sync with both the 100 MHz from the clock and the 1 pps from the Kalman
filter it was then used as one of the sources for the Kalman filter.

In the clock, how do they detect the difference in frequency of the
multiplied VCXO and the Rubidium transition?


The classical method is to sweep the VCXO slightly and observe the
changes in the Rb cell absorption. A servo balances the sweep to
be symmetrical about the sweet point.

IIRC, there was an article about it in an older HP Journal.

https://dl.dropboxusercontent.com/u/53724080/Gear/Efratom.pdf


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[DecadentLinuxUserNumeroUn]

On Sun, 28 Sep 2014 09:17:45 -0700 (PDT), Bill Sloman
<bill.sloman@gmail.com> Gave us:

The original sophisticated reference to pool was yours

But NOT a pool hall, you stupid, illiterate twerp.