PLL tricks

[John Larkin]

On Fri, 12 Sep 2014 14:11:10 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 09/11/2014 10:59 PM, dagmargoodboat@yahoo.com wrote:
On Thursday, September 11, 2014 8:24:15 PM UTC-4, John Larkin wrote:
On Thu, 11 Sep 2014 17:00:06 -0700 (PDT), dagmargoo...@yahoo.com
wrote:
On Thursday, September 11, 2014 12:29:36 PM UTC-4, John Larkin
wrote:
On Thu, 11 Sep 2014 11:52:01 -0400, Phil Hobbs wrote:
On 09/11/2014 11:38 AM, Bill Sloman wrote:

It's a can of worms. Any noise on the rails can creep on
and shift the switching point. A product phase detector is
a lot more forgiving.

John has shipping products with 1-ps jitter. I have a
digital delay box of his that has 5 ps of jitter, which is
about 35 dB better than the SRS box I used to have. So
rather than preening yourself, you might listen and learn.

No Phil, you're mistaken. John's a mechanic / fiddler who only
gets things right accidentally. NOOTTTTT!

There's nothing wrong with mechanics, and nothing wrong with
fiddling or accidental solutions.

I was kidding of course. The best designers I've known have always
been great mechanical and otherwise-thinkers and tinkerers too.

Feynman made one of his breakthroughs imagining twirling pie plates.
At a diner, IIRC.

Design is, fundamentally, fiddling, namely exploring an enormous
solution space and finding something that works well. Brains can do
that, somehow. Fiddling is an acquired skill.

Yes. And lots of fiddling at an early age helps.

Equations seldom design stuff.

Yep. Equations usually describe stuff someone already did, help
others duplicate, and sometimes refine it.

That's unduly pessimistic. Before designing an instrument, I always
calculate how good it _could_ be, from first principles where possible.

Sure, but you have to have an architecture to start with.

Sometimes staring at an equation does suggest an architecture.

That way I can (a) select the best possible approach, and (b) know when
it isn't there yet. I couldn't do my job without crunching a fair bit
of math. My rule of thumb is that the final result gets within 1 dB of
the theory most of the time, and within 3 dB almost always (i.e. unless
I've made a math blunder or failed to think of some physical effect that
turns out to be important).

You're more math-y than I am, so I tend to simulate more [1].
Electronic circuits are often sufficiently nonlinear that simulation
is more useful than algebra. When you can trust it, of course.

And there's always soldering.

[1] or have a lackey do the math.



--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Phil Hobbs]

On 09/12/2014 03:02 PM, John Larkin wrote:

On Fri, 12 Sep 2014 14:11:10 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 09/11/2014 10:59 PM, dagmargoodboat@yahoo.com wrote:
On Thursday, September 11, 2014 8:24:15 PM UTC-4, John Larkin wrote:
On Thu, 11 Sep 2014 17:00:06 -0700 (PDT), dagmargoo...@yahoo.com
wrote:
On Thursday, September 11, 2014 12:29:36 PM UTC-4, John Larkin
wrote:
On Thu, 11 Sep 2014 11:52:01 -0400, Phil Hobbs wrote:
On 09/11/2014 11:38 AM, Bill Sloman wrote:

It's a can of worms. Any noise on the rails can creep on
and shift the switching point. A product phase detector is
a lot more forgiving.

John has shipping products with 1-ps jitter. I have a
digital delay box of his that has 5 ps of jitter, which is
about 35 dB better than the SRS box I used to have. So
rather than preening yourself, you might listen and learn.

No Phil, you're mistaken. John's a mechanic / fiddler who only
gets things right accidentally. NOOTTTTT!

There's nothing wrong with mechanics, and nothing wrong with
fiddling or accidental solutions.

I was kidding of course. The best designers I've known have always
been great mechanical and otherwise-thinkers and tinkerers too.

Feynman made one of his breakthroughs imagining twirling pie plates.
At a diner, IIRC.

Design is, fundamentally, fiddling, namely exploring an enormous
solution space and finding something that works well. Brains can do
that, somehow. Fiddling is an acquired skill.

Yes. And lots of fiddling at an early age helps.

Equations seldom design stuff.

Yep. Equations usually describe stuff someone already did, help
others duplicate, and sometimes refine it.

That's unduly pessimistic. Before designing an instrument, I always
calculate how good it _could_ be, from first principles where possible.

Sure, but you have to have an architecture to start with.

Normally a few possibilities, generated by some quality white-board
time. (Preferably with some smart colleagues.)

Sometimes staring at an equation does suggest an architecture.


That way I can (a) select the best possible approach, and (b) know when
it isn't there yet. I couldn't do my job without crunching a fair bit
of math. My rule of thumb is that the final result gets within 1 dB of
the theory most of the time, and within 3 dB almost always (i.e. unless
I've made a math blunder or failed to think of some physical effect that
turns out to be important).

You're more math-y than I am, so I tend to simulate more [1].
Electronic circuits are often sufficiently nonlinear that simulation
is more useful than algebra. When you can trust it, of course.

And there's always soldering.

[1] or have a lackey do the math.

It's really hard to get good minions nowadays. Beautiful Layout
Hunchback just did her first thin-film RTD--22 mm square filled with
serpentine traces, 2.5 mil lines and spaces, with a 28-mm pigtail (4-pin
FFC for Kelvin connections). Made with 1/3 ounce copper, it turns out
to be right around 100 ohms, and one of those places in Shenzhen is
making us 40 of them for $100 shipped.

Sure is cheaper than buying them from Omega!

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Jan Panteltje]

On a sunny day (Fri, 12 Sep 2014 12:02:30 -0700) it happened John Larkin
<jlarkin@highlandtechnology.com> wrote in
<ueg61a5nrr0q77ht8sbskhgp7mm1q5pj1n@4ax.com>:

That way I can (a) select the best possible approach, and (b) know when
it isn't there yet. I couldn't do my job without crunching a fair bit
of math. My rule of thumb is that the final result gets within 1 dB of
the theory most of the time, and within 3 dB almost always (i.e. unless
I've made a math blunder or failed to think of some physical effect that
turns out to be important).

You're more math-y than I am, so I tend to simulate more [1].
Electronic circuits are often sufficiently nonlinear that simulation
is more useful than algebra. When you can trust it, of course.

And there's always soldering.

[1] or have a lackey do the math.

Electronics is like driving a car or flying like a bird.
You do not, as bird, use take off weight, calculate needed runway length,
get weather report, fuel..., vectors, you just flap the wings and go.
But even birds learn bottom up, the first time is critical
when they fall out of the nest from high altitude.
The birds have, like we have, a neural net to do the 'math'.
They had rat brain cells control a flight simulator, just a few of those:
http://www.research.ufl.edu/publications/explore/v10n1/extract2.html

'Math' as we know it, is just a small sub circuit made of some neurons.
There is a guy who can say pi to 100,000 digits from his head:
http://www.foxnews.com/story/2006/10/04/japanese-man-recites-first-100000-digits-pi/
Is he calculating? is he remembering? how many neurons are invoved?
Maybe we say, when 'designing ' a circuit, "estimating".
I usually estimate LC circuits almost correct.
There was a while ago somebody who presented a chart for that here,
something like that is apparently in my head, formed from experiment, experience,
the way any neural net learns.

In the same way or for the same reason I am always hungry for new input
to train the net.
Math? Slimulations? Perhaps sometimes.
I have only been surprised once by a slimulation, it predicted an oscillation
that I thought could not happen, had to 'adjust' my 'model'.

Usually you only need very basic math to get orders of magnitude idea.
Phil Hobbs is right if you want the theoretical maximum you can do the math and check
how far you are away from it, or how much noise is the minimum, and even then there are surprises,
as the recent discussion in sci.astro about holographic noise in gravity wave detectors shows.
http://www.quantumconsciousness.org/worldhologram.htm
http://www.geo600.org/
http://holometer.fnal.gov/
(for if you like lasers).

For normal human equipment usually it is all not so critical, analog...
We see and hear with bigger errors.
And there is a lot we have not discovered yet, about interaction and communication...
Maybe better too.

 

On Friday, September 12, 2014 12:51:26 PM UTC-4, Bill Sloman wrote:

On Friday, 12 September 2014 23:37:43 UTC+10, dagmarg...@yahoo.com wrote:
On Friday, September 12, 2014 12:14:57 AM UTC-4, Bill Sloman wrote:
On Friday, 12 September 2014 10:24:15 UTC+10, John Larkin wrote
On Thu, 11 Sep 2014 17:00:06 -0700 (PDT), dagmargoo...@yahoo.com wrote:
On Thursday, September 11, 2014 12:29:36 PM UTC-4, John Larkin wrote:

snip

There's nothing wrong with mechanics, and nothing wrong with fiddling
or accidental solutions. Design is, fundamentally, fiddling, namely
exploring an enormous solution space and finding something that works
well. Brains can do that, somehow. Fiddling is an acquired skill.

Equations seldom design stuff.

It helps if the brain is well stocked with design solutions.

John's told him that a DDS output would be "jittery".

It is. The DDS outputs a quantized waveform that can be pretty rough.

Technically speaking, it isn't "jittering". The artifacts are deterministic, rather than random.

It jitters when you phase detect its edges. If you don't, the phase detector
output is sensitized to changes in reference or VCO duty-cycles.

The output is not an exact integer multiple of the DDS' clock, which means the DDS cycles through its DAC codes (as opposed to repeatedly using the same set over and over), creating a much-lower error frequency and phase error waveform related to the DAC's imperfections.

Considered as an error signal on the perfect sine wave desired, it's a series of ramps which can be low-pass filtered out. 15.52 of them per cycle is actually fairly high frequency noise, and a couple of poles of low pass-filtering would clean it up considerably.

155.52 MHz is only four octaves up. If you're outputting 10MHz, a couple poles
is just -48dB.

> It won't create any kind of frequency error. I can imagine that there might be a small residual amplitude error that could translate into a periodic phase shift error which could repeat at 80kHz, which could be problem if you used an edge-based phase detector.

Yes, that's what I was suggesting.

> With a product-based phase detector, this would average out a lot faster.

But, the product-based detector introduces duty-cycle sensitivity. Drift.

The DAC might be very good to where its inaccuracies are acceptable. We haven't examined that yet.

If his brain had been better stocked, it would have told him that DDS would be pushing out a stair-case approximation to 10MHz sine wave, with the steps on the staircase reflecting 155.52MHz content (plus odd harmonics of 155.52 MHz which would be easy to low pass filter down to negligible proportions).

The 10MHz is the master reference; we're trying to generate 155.52e6 from it.

Not exactly. You are trying to lock a 155.52MHz output to a 10MHz reference.

Yes, that's how you generate 155.52MHz from a 10MHz master reference.

> Trying to generate 155.52MHz from it produces images of frequency multipliers, which won't work, since 155.52MHz isn't a harmonic of 10MHz.

Right, so the first impulse is to lock the loop at the GCD of 10MHz and
155.52MHz, 80KHz.

I showed how a multiplier lets the phase detector run at 640KHz, an 8x
improvement. More improvement might be possible.

I'm talking about using the DDS to synthesize a PLL reference signal from the 10MHz standard, not using the DDS to output 155.52MHz.

The only way you can do that is by buying a DDS with a built-in VCO which can be locked to an external reference.

Unless on-chip resonators have improved, any in-built VCO will have horrible
jitter compared to an external VCXO.

http://www.analog.com/static/imported-files/data_sheets/AD9915.pdf

offers a 2.4 to 2.5GHz VCO which you could set at precisely 2.44GHz by choosing a 244 divide ratio (anything even from 20 to 510 seems to be on offer) and let it lock the divided output to the 10MHz reference.

You can then program any output frequency you want - page 17/18 of the data sheet tells you how - and with the AD9915 you really can get any rational number ratio you want.

Sadly, the AD9915 is expensive - $143.10 each for 5 to 9 from Newark - and Newark don't have any in stock, though there seem to be three in the UK workshop.

John asked to synthesize 155.52 from 10MHz originally but did comment later about doing the reverse, which made room for confusion.

It's quite a bit cheaper.

I later understood John was trying to use the DDS to divide the 155.52MHz
feedback signal to 10MHz so he could run the PLL phase detector at 10MHz.

That adds an awful lot of circuitry and delay into the signal path--I'd
think that would jitter.

If the DDS is synthesizing 10MHz from a 155.52MHz reference, the DDS is outputting a 15.52 step 10MHz "sinewave." 15.52 steps is a pretty rough waveform.

But a low pass filter would clean it up a lot.

Not to ppm, and if you try you may destabilize the PLL.

e.g., if the PLL error signal is messy, add in a jitter-compensating signal.

e.g., do fractional division with an integer number of clocks plus a varying analog ramp delay. That would let you keep a much higher reference frequency.

Even a ramp with horrible resolution is way less jittery than alternating the divider modulii.

That's in the same ball-park as using a DDS to go from 155.52MHz to a synthesised 10MHz.

We're solving different problems.

Depends how high you get above the playing field. John wants a 155.52MHz clock with at least the sort of stability you can get from a good quality 10MHz quartz crystal reference oscillator. There are quite a few ways to get from A to B.

http://www.freqelec.com/pdf/rfs_12pg.pdf

offers even better frequency stability and - with option 008 "1 Hz to 10 MHz sq. wave, TTL Comp., 5 MHz to 20 MHz sine wave." an output which could be an exact integer sub-multiple of 155.52MHz. An output at 9.7200MHz might be handy.

That uses a rubidium source to discipline a programmable VCXO, where the
short-term phase performance is limited by the VCXO.

That costs a ton in power and complexity, but has no better phase performance
than my scheme: disciplining an 80MHz VCXO to the 10MHz master, then
dividing to 640KHz and running the PLL detector there.

Sadly, the rubidium reference frequency at 6.835GHz isn't an integral multiple of 155.52MHz. Caesium - at 9.193 GHz - isn't any better.

snipped pedestrian stuff

The <pedestrian stuff> worked as well, while saving an order of magnitude
in space, delay, power, and money.

All of that's old-school, meant to be solid and simple. '57 Chevy.

And clumsy. The MC100EP195 could do the same kind of job in a smaller package.

No. The MC100ep195 generates inexactly-spaced edges that jitter and drift.
My scheme produces exactly-spaced edges with minimal jitter. Phase drift
would be phase detector-limited.

> The temperature sensitivity of the delay it generates is nasty, and the 10psec resolution means that it's never going to be good for direct synthesis, but it would probably be good enough for a good-enough-for-long-term-stability scheme for generating a monitoring 10MHz output from the 155.52MHz source to be compared with the 10MHz reference crystal by a product detector feeding back through low-pass filter into a nice slow integrator to keep the VCO at the right frequency in the long term.

If the 155.52 MHz VCXO's short-term stability is that good then there's no
need to up the phase detector frequency in the first place. Just run at
80KHz and be done with it.

That might actually be a viable solution: use a really good 155.52MHz VCXO,
one that doesn't need to be disciplined that often.

Today, a DDS PLL-reference generator might be simpler. Clocked at a non-integer multiple of the output frequency, say, 250MHz, a DDS could produce a stair-stepped 960KHz (=155.52e6/162) approximation to a sinewave (for the 155.52MHz PLL) reference, with ~260 steps in it.

There'd be a lot of easily-filtered 250MHz in the output, and a not-so-easily-filtered DAC-error beat frequency component that might be small enough not to matter.

The AD9915 is off the shelf and pretty much complete. $143.10 isn't cheap, but for eight units, what you pay for the off-the-shelf solution is recovered in reduced design time. $1,144.80 doesn't buy a lot of design time.

It's faster than the number you had in mind - at 2.44GHz versus 250MHz - and the non-binary modulus it offers seems to get rid of the DAC-error beat frequency component.

Where do you get the 2.44GHz?

ISTM phase jitter using the internal clock multiplier would be awful. If you
use the external clock, you've merely added the problem of making 2.44GHz.

TANSTAAFL.

Cheers,
James Arthur

 

[John Larkin]

On Fri, 12 Sep 2014 15:13:39 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 09/12/2014 03:02 PM, John Larkin wrote:
On Fri, 12 Sep 2014 14:11:10 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 09/11/2014 10:59 PM, dagmargoodboat@yahoo.com wrote:
On Thursday, September 11, 2014 8:24:15 PM UTC-4, John Larkin wrote:
On Thu, 11 Sep 2014 17:00:06 -0700 (PDT), dagmargoo...@yahoo.com
wrote:
On Thursday, September 11, 2014 12:29:36 PM UTC-4, John Larkin
wrote:
On Thu, 11 Sep 2014 11:52:01 -0400, Phil Hobbs wrote:
On 09/11/2014 11:38 AM, Bill Sloman wrote:

It's a can of worms. Any noise on the rails can creep on
and shift the switching point. A product phase detector is
a lot more forgiving.

John has shipping products with 1-ps jitter. I have a
digital delay box of his that has 5 ps of jitter, which is
about 35 dB better than the SRS box I used to have. So
rather than preening yourself, you might listen and learn.

No Phil, you're mistaken. John's a mechanic / fiddler who only
gets things right accidentally. NOOTTTTT!

There's nothing wrong with mechanics, and nothing wrong with
fiddling or accidental solutions.

I was kidding of course. The best designers I've known have always
been great mechanical and otherwise-thinkers and tinkerers too.

Feynman made one of his breakthroughs imagining twirling pie plates.
At a diner, IIRC.

Design is, fundamentally, fiddling, namely exploring an enormous
solution space and finding something that works well. Brains can do
that, somehow. Fiddling is an acquired skill.

Yes. And lots of fiddling at an early age helps.

Equations seldom design stuff.

Yep. Equations usually describe stuff someone already did, help
others duplicate, and sometimes refine it.

That's unduly pessimistic. Before designing an instrument, I always
calculate how good it _could_ be, from first principles where possible.

Sure, but you have to have an architecture to start with.

Normally a few possibilities, generated by some quality white-board
time. (Preferably with some smart colleagues.)

Sometimes staring at an equation does suggest an architecture.


That way I can (a) select the best possible approach, and (b) know when
it isn't there yet. I couldn't do my job without crunching a fair bit
of math. My rule of thumb is that the final result gets within 1 dB of
the theory most of the time, and within 3 dB almost always (i.e. unless
I've made a math blunder or failed to think of some physical effect that
turns out to be important).

You're more math-y than I am, so I tend to simulate more [1].
Electronic circuits are often sufficiently nonlinear that simulation
is more useful than algebra. When you can trust it, of course.

And there's always soldering.

[1] or have a lackey do the math.

It's really hard to get good minions nowadays. Beautiful Layout
Hunchback just did her first thin-film RTD--22 mm square filled with
serpentine traces, 2.5 mil lines and spaces, with a 28-mm pigtail (4-pin
FFC for Kelvin connections). Made with 1/3 ounce copper, it turns out
to be right around 100 ohms, and one of those places in Shenzhen is
making us 40 of them for $100 shipped.

Sure is cheaper than buying them from Omega!

Cheers

Phil Hobbs

Copper RTD? On a flex PCB? Cool. Copper has a nice linear TC.

Now you need copper thickness control, if the absolute resistance
matters.

Do you have a good source for flex PCBs? We have a couple of projects
that will use flex, with transmission lines and zigzag inductors, and
we'll probably have to iterate some, and experiment with losses and
things.

I'm also thinking about making a transmission-line transformer out of
flex. Inagine a circle with pigtails extending out opposite sides,
primary and secondary windings, and clamping that inside the gap of a
pot core.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Phil Hobbs]

On 09/12/2014 03:40 PM, John Larkin wrote:

On Fri, 12 Sep 2014 15:13:39 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 09/12/2014 03:02 PM, John Larkin wrote:
On Fri, 12 Sep 2014 14:11:10 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 09/11/2014 10:59 PM, dagmargoodboat@yahoo.com wrote:
On Thursday, September 11, 2014 8:24:15 PM UTC-4, John Larkin
wrote:
On Thu, 11 Sep 2014 17:00:06 -0700 (PDT),
dagmargoo...@yahoo.com wrote:
On Thursday, September 11, 2014 12:29:36 PM UTC-4, John
Larkin wrote:
On Thu, 11 Sep 2014 11:52:01 -0400, Phil Hobbs wrote:
On 09/11/2014 11:38 AM, Bill Sloman wrote:

It's a can of worms. Any noise on the rails can
creep on and shift the switching point. A product
phase detector is a lot more forgiving.

John has shipping products with 1-ps jitter. I have
a digital delay box of his that has 5 ps of jitter,
which is about 35 dB better than the SRS box I used
to have. So rather than preening yourself, you might
listen and learn.

No Phil, you're mistaken. John's a mechanic / fiddler
who only gets things right accidentally. NOOTTTTT!

There's nothing wrong with mechanics, and nothing wrong
with fiddling or accidental solutions.

I was kidding of course. The best designers I've known have
always been great mechanical and otherwise-thinkers and
tinkerers too.

Feynman made one of his breakthroughs imagining twirling pie
plates. At a diner, IIRC.

Design is, fundamentally, fiddling, namely exploring an
enormous solution space and finding something that works
well. Brains can do that, somehow. Fiddling is an acquired
skill.

Yes. And lots of fiddling at an early age helps.

Equations seldom design stuff.

Yep. Equations usually describe stuff someone already did,
help others duplicate, and sometimes refine it.

That's unduly pessimistic. Before designing an instrument, I
always calculate how good it _could_ be, from first principles
where possible.

Sure, but you have to have an architecture to start with.

Normally a few possibilities, generated by some quality
white-board time. (Preferably with some smart colleagues.)

Sometimes staring at an equation does suggest an architecture.


That way I can (a) select the best possible approach, and (b)
know when it isn't there yet. I couldn't do my job without
crunching a fair bit of math. My rule of thumb is that the
final result gets within 1 dB of the theory most of the time,
and within 3 dB almost always (i.e. unless I've made a math
blunder or failed to think of some physical effect that turns
out to be important).

You're more math-y than I am, so I tend to simulate more [1].
Electronic circuits are often sufficiently nonlinear that
simulation is more useful than algebra. When you can trust it, of
course.

And there's always soldering.

[1] or have a lackey do the math.

It's really hard to get good minions nowadays. Beautiful Layout
Hunchback just did her first thin-film RTD--22 mm square filled
with serpentine traces, 2.5 mil lines and spaces, with a 28-mm
pigtail (4-pin FFC for Kelvin connections). Made with 1/3 ounce
copper, it turns out to be right around 100 ohms, and one of those
places in Shenzhen is making us 40 of them for $100 shipped.

Sure is cheaper than buying them from Omega!

Cheers

Phil Hobbs

Copper RTD? On a flex PCB? Cool. Copper has a nice linear TC.

Now you need copper thickness control, if the absolute resistance
matters.

Right. It doesn't matter for this iteration. A useful rule of thumb is
that 1/2 oz copper is 1 milliohm per square at 25C. This flex has 1/3
ounce, so that's 1.5 milliohm/sq. The pattern has about 62,000 squares,
which I know because I wrote a small program that generated the
serpentine pattern as a .BMP file, and BLH imported it into Eagle and
connected it up.

Do you have a good source for flex PCBs? We have a couple of
projects that will use flex, with transmission lines and zigzag
inductors, and we'll probably have to iterate some, and experiment
with losses and things.

Dunno if it's good--this is our first try. BLH has their contact info
but she's goofing off this afternoon. Their prototype offering is 10
pieces of anything that will fit into a 50 mm square, two layers with
solder mask and silk for $85. The film is yellow, so maybe it's even
Kapton.

I'm also thinking about making a transmission-line transformer out
of flex. Inagine a circle with pigtails extending out opposite
sides, primary and secondary windings, and clamping that inside the
gap of a pot core.

As long as you don't screw it up with impedance discontinuities due to
the ferrite coming too close at the apertures, it 'll probably work fine.

Back to measuring the absorption spectra of hen's eggs.

Cheers

Phil


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

On Tuesday, September 9, 2014 8:48:22 PM UTC-4, Tom Miller wrote:

"John Larkin" wrote:

If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exac
frequency ratio anyhow.

Use a VCOCXO, a very stable oscillator and a long time constant in the loop.

GPSDOs use 1-pps for the loop.

All things considered, this answer wins the prize if a VCXO can be found
that stays put well enough, phase-wise, when tweaked every 1/80KHz.

The GPSDOs might not directly compare--all they care about is frequency.
John needs super-stable phase too.

Cheers,
James Arthur

 

Jan Panteltje <panteltje@yahoo.com> wrote:

You do not, as bird, use take off weight, calculate needed runway
length, get weather report, fuel..., vectors, you just flap the wings
and go.

Sort of related: European starlings (Sturnus vulgaris) develop about
10 to 15 W of metabolic power, and deliver about 1 to 2.5 W at the
wings. I hadn't thought about it much before I read the paper, but I
was suprised at how small those numbers are. It's almost like the
design has been iterated for millions of years, or something.
(Reference: http://jeb.biologists.org/content/204/19/3311 )

Matt Roberds

 

[Phil Hobbs]

On 9/12/2014 3:37 PM, Jan Panteltje wrote:

On a sunny day (Fri, 12 Sep 2014 12:02:30 -0700) it happened John Larkin
jlarkin@highlandtechnology.com> wrote in
ueg61a5nrr0q77ht8sbskhgp7mm1q5pj1n@4ax.com>:

That way I can (a) select the best possible approach, and (b) know when
it isn't there yet. I couldn't do my job without crunching a fair bit
of math. My rule of thumb is that the final result gets within 1 dB of
the theory most of the time, and within 3 dB almost always (i.e. unless
I've made a math blunder or failed to think of some physical effect that
turns out to be important).

You're more math-y than I am, so I tend to simulate more [1].
Electronic circuits are often sufficiently nonlinear that simulation
is more useful than algebra. When you can trust it, of course.

And there's always soldering.

[1] or have a lackey do the math.

Electronics is like driving a car or flying like a bird.
You do not, as bird, use take off weight, calculate needed runway length,
get weather report, fuel..., vectors, you just flap the wings and go.

So _that's_ why your schematics look like birds' nests.

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Phil Hobbs]

On 9/12/2014 3:58 PM, dagmargoodboat@yahoo.com wrote:

On Friday, September 12, 2014 2:11:10 PM UTC-4, Phil Hobbs wrote:
On 09/11/2014 10:59 PM, dagmargoo...@yahoo.com wrote:
On Thursday, September 11, 2014 8:24:15 PM UTC-4, John Larkin wrote:
On Thu, 11 Sep 2014 17:00:06 -0700 (PDT), dagmargoo...@yahoo.com
wrote:
On Thursday, September 11, 2014 12:29:36 PM UTC-4, John Larkin
wrote:

There's nothing wrong with mechanics, and nothing wrong with
fiddling or accidental solutions.

I was kidding of course. The best designers I've known have always
been great mechanical and otherwise-thinkers and tinkerers too.

Feynman made one of his breakthroughs imagining twirling pie plates.
At a diner, IIRC.

Design is, fundamentally, fiddling, namely exploring an enormous
solution space and finding something that works well. Brains can do
that, somehow. Fiddling is an acquired skill.

Yes. And lots of fiddling at an early age helps.

Equations seldom design stuff.

Yep. Equations usually describe stuff someone already did, help
others duplicate, and sometimes refine it.

That's unduly pessimistic. Before designing an instrument, I always
calculate how good it _could_ be, from first principles where possible.

That way I can (a) select the best possible approach, and (b) know when
it isn't there yet. I couldn't do my job without crunching a fair bit
of math. My rule of thumb is that the final result gets within 1 dB of
the theory most of the time, and within 3 dB almost always (i.e. unless
I've made a math blunder or failed to think of some physical effect that
turns out to be important).

Granted, in your situation.

More often I'm trying to solve novel problems. A long time ago, it was
making clean BPSK SS UHF cheaply from a cheap crystal, at micropower,
fast-settling, with a lot of other constraints. There simply isn't an
equation that outputs a novel topology.

Quite so. OTOH calculating the fundamental limits as a function of the
crystal Q and transistor noise can be pretty illuminating. A few years
ago when I was building stabilized lasers for downhole applications, I
had to go into a lot of that stuff, and learned a lot. (Leeson's
equation for oscillator noise is sort of the electronic analogue of the
Schawlow-Townes minimum line width of a laser.)

If you can't calculate how good it _could_ be, how do you know when
you're done? It's a pity to declare victory and leave, when there's
another 20 dB available with affordable devices. (Yes, I know about
engineering being the art of "good enough for the lowest cost", but
better performance is always worth something--you can trade it for a
higher selling price, wider spec limits, and/or a quieter life.)

More recently I was tasked loading a device with a ~500A max inrush onto
a supply made to trip-out around a tenth of that, with everything COTS
and "untouchable," lest the certifications be spoiled. That too was
solved with a novel external topology, custom for the application.

Put a penny into the fusebox, Ralph.

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Bill Sloman]

On Saturday, 13 September 2014 09:40:44 UTC+10, dagmarg...@yahoo.com wrote:

On Friday, September 12, 2014 12:51:26 PM UTC-4, Bill Sloman wrote:
On Friday, 12 September 2014 23:37:43 UTC+10, dagmarg...@yahoo.com wrote:
On Friday, September 12, 2014 12:14:57 AM UTC-4, Bill Sloman wrote:
On Friday, 12 September 2014 10:24:15 UTC+10, John Larkin wrote
On Thu, 11 Sep 2014 17:00:06 -0700 (PDT), dagmargoo...@yahoo.com wrote:
On Thursday, September 11, 2014 12:29:36 PM UTC-4, John Larkin wrote:

<snip>

With a product-based phase detector, this would average out a lot faster.

But, the product-based detector introduces duty-cycle sensitivity. Drift.

Digital dividers generate rather precise and stable duty cycles. That's really unlikely to be a problem.

The product detector is going to have some kind of DC off-set - like every op amp in the analog signal processing chain that converts it's output into a DC voltage to control the VCO - but it's going to be small and pretty stable.

The DAC might be very good to where its inaccuracies are acceptable. We haven't examined that yet.

If his brain had been better stocked, it would have told him that DDS would be pushing out a stair-case approximation to 10MHz sine wave, with the steps on the staircase reflecting 155.52MHz content (plus odd harmonics of 155.52 MHz which would be easy to low pass filter down to negligible proportions).

The 10MHz is the master reference; we're trying to generate 155.52e6 from it.

Not exactly. You are trying to lock a 155.52MHz output to a 10MHz reference.

Yes, that's how you generate 155.52MHz from a 10MHz master reference.

There's a cause and effect implication in your choice of words that strikes me a potentially misleading.

Trying to generate 155.52MHz from it produces images of frequency multipliers, which won't work, since 155.52MHz isn't a harmonic of 10MHz.

Right, so the first impulse is to lock the loop at the GCD of 10MHz and
155.52MHz, 80KHz.

I showed how a multiplier lets the phase detector run at 640KHz, an 8x
improvement. More improvement might be possible.

Obviously.

I'm talking about using the DDS to synthesize a PLL reference signal from the 10MHz standard, not using the DDS to output 155.52MHz.

The only way you can do that is by buying a DDS with a built-in VCO which can be locked to an external reference.

Unless on-chip resonators have improved, any in-built VCO will have horrible jitter compared to an external VCXO.

The AD9915 offers a tenfold faster VCO than the one you had in mind. The data sheet provides a lot of data on pages 13 and 14 of the data sheet on the phase noise performance, but in dBc/Hz, which doesn't mean anything to me.. The phase noise is unlikely to be impressive, but the on-chip VCO is restricted to the range 2.4 to 2.5GHz, so it is probably better than the number you first thought of.

http://www.analog.com/static/imported-files/data_sheets/AD9915.pdf

offers a 2.4 to 2.5GHz VCO which you could set at precisely 2.44GHz by choosing a 244 divide ratio (anything even from 20 to 510 seems to be on offer) and let it lock the divided output to the 10MHz reference.

You can then program any output frequency you want - page 17/18 of the data sheet tells you how - and with the AD9915 you really can get any rational number ratio you want.

Sadly, the AD9915 is expensive - $143.10 each for 5 to 9 from Newark - and Newark don't have any in stock, though there seem to be three in the UK workshop.

John asked to synthesize 155.52 from 10MHz originally but did comment later about doing the reverse, which made room for confusion.

It's quite a bit cheaper.

I later understood John was trying to use the DDS to divide the 155.52MHz
feedback signal to 10MHz so he could run the PLL phase detector at 10MHz.

That adds an awful lot of circuitry and delay into the signal path--I'd
think that would jitter.

The extra circuitry is all in the path that leads to a slowly varying - essentially DC signal - that control his 155.52MHz VCO or - better - VCXO (which it looks as if he can buy off the shelf from ON-Semiconductor - give or take the usual nonsense about minimum order quantities, and the actual existence of physical stock sitting on physical shelves).

Any jitter in that path can get filtered out. You can actually stabilise the PLL feedback loop despite having a lot of delay in the filters before and after the phase detector. Floyd M Gardner walks you through it in "Phaselock Techniques" and I'm sure that there are more modern texts which do it more painlessly.

If the DDS is synthesizing 10MHz from a 155.52MHz reference, the DDS is outputting a 15.52 step 10MHz "sinewave." 15.52 steps is a pretty rough waveform.

But a low pass filter would clean it up a lot.

Not to ppm, and if you try you may destabilize the PLL.

Only if you don't understand PLL design.

e.g., if the PLL error signal is messy, add in a jitter-compensating signal.

e.g., do fractional division with an integer number of clocks plus a varying analog ramp delay. That would let you keep a much higher reference frequency.

Even a ramp with horrible resolution is way less jittery than alternating the divider modulii.

That's in the same ball-park as using a DDS to go from 155.52MHz to a synthesised 10MHz.

We're solving different problems.

Depends how high you get above the playing field. John wants a 155.52MHz clock with at least the sort of stability you can get from a good quality 10MHz quartz crystal reference oscillator. There are quite a few ways to get from A to B.

http://www.freqelec.com/pdf/rfs_12pg.pdf

offers even better frequency stability and - with option 008 "1 Hz to 10 MHz sq. wave, TTL Comp., 5 MHz to 20 MHz sine wave." an output which could be an exact integer sub-multiple of 155.52MHz. An output at 9.7200MHz might be handy.

That uses a rubidium source to discipline a programmable VCXO, where the
short-term phase performance is limited by the VCXO.

That costs a ton in power and complexity, but has no better phase performance
than my scheme: disciplining an 80MHz VCXO to the 10MHz master, then
dividing to 640KHz and running the PLL detector there.

The power is inconsequential. The complexity is pretty much all inside the module you buy from Freqelec - or whichever of it's competitors you might choose to go for. If John only needs to make eight or whatever it is, buying in the complexity is usually a good idea.

The Freqelec package seems to incorporate a 50.255MHz VCO (probably a VCXO) which is unlikely to be much different to your 80MHz VCXO or the 155.52MHz VCXO that John probably ought to buy from ON-Semiconductor (if he can and if it really is a good quality VCXO).

Sadly, the rubidium reference frequency at 6.835GHz isn't an integral multiple of 155.52MHz. Caesium - at 9.193 GHz - isn't any better.

snipped pedestrian stuff

The <pedestrian stuff> worked as well, while saving an order of magnitude
in space, delay, power, and money.

But it has to be designed in detail, laid out onto a board and so forth. It strikes me as adding a lot of complexity while not offering all that much in the way of advantage.

All of that's old-school, meant to be solid and simple. '57 Chevy.

And clumsy. The MC100EP195 could do the same kind of job in a smaller package.

No. The MC100ep195 generates inexactly-spaced edges that jitter and drift..

But in a signal path that ends up at the slowly changing DC voltage the control the VCXO frequency output. The fact that the nominally 2.5nsec to 8.9nsec delay through the MC100ep195 would increase as part got hotter does impose a temperature dependent phase shift between the 10MHz reference and the 155.52MHz VCXO output, but there are similar propagation delays through any collection of logic.

My scheme produces exactly-spaced edges with minimal jitter. Phase drift
would be phase detector-limited.

There are propagation delays through your divider set-up. Not knowing what logic family (or programmable logic device) you have in mind, I can't say whether they are better or worse, but I do know that they aren't in a signal path where the jitter adds directly to the jitter on the output of the 155..52MHz
VCXO. That path is in there to keep the frequency right,and when disciplining a VCXO the bandwidth of the feed-back loop is usually kept pretty low.

The temperature sensitivity of the delay it generates is nasty, and the 10psec resolution means that it's never going to be good for direct synthesis, but it would probably be good enough for a good-enough-for-long-term-stability scheme for generating a monitoring 10MHz output from the 155.52MHz source to be compared with the 10MHz reference crystal by a product detector feeding back through low-pass filter into a nice slow integrator to keep the VCO at the right frequency in the long term.

If the 155.52 MHz VCXO's short-term stability is that good then there's no
need to up the phase detector frequency in the first place. Just run at
80kHz and be done with it.

True, but this thread is all about letting John do it faster.

That might actually be a viable solution: use a really good 155.52MHz VCXO,
one that doesn't need to be disciplined that often.

It needs to be disciplined continuously but the optimal bandwidth for the PLL feedback path does depend on the long term stability of the crystal oscillator.

Today, a DDS PLL-reference generator might be simpler. Clocked at a non-integer multiple of the output frequency, say, 250MHz, a DDS could produce a stair-stepped 960KHz (=155.52e6/162) approximation to a sinewave (for the 155.52MHz PLL) reference, with ~260 steps in it.

There'd be a lot of easily-filtered 250MHz in the output, and a not-so-easily-filtered DAC-error beat frequency component that might be small enough not to matter.

The AD9915 is off the shelf and pretty much complete. $143.10 isn't cheap, but for eight units, what you pay for the off-the-shelf solution is recovered in reduced design time. $1,144.80 doesn't buy a lot of design time.

It's faster than the number you had in mind - at 2.44GHz versus 250MHz - and the non-binary modulus it offers seems to get rid of the DAC-error beat frequency component.

Where do you get the 2.44GHz?

244 times 10MHz. The AD9915 VCO can be run anywhere in the narrow range 2.4GHz to 2.5GHz, which means that the divider ratios that you are allowed to program are 240, 242, 244, 246, 248 and 250. Something in the middle seemed a sensible choice.

> ISTM phase jitter using the internal clock multiplier would be awful.

I posted a link to the data sheet. You could have worked out how awful it was - if you know what dBc/Hz actually means - by looking at pages 13 and 14

> If you use the external clock, you've merely added the problem of making 2.44GHz.

Well, you can use any external clock frequency up 2.5GHz. Back in the 1980s you could buy very nice (if bulky and non-cheap) YIG-tuned oscillators that ran that fast. Chemically thinned quartz oscillator crystals seem to go up to about 700MHz, and SAW devices do seem to be able to go quite a lot faster, though I've never been motivated to dig into them.

I imagine that if the AD9915 VCO is as bad as you expect it to be, that approach stops making sense. The AD9915 isn't the only DDS that Analog Devices makes with a built-in VCO, and Linear Technology has a fractional-N part with a VCO that runs even faster

http://cds.linear.com/docs/en/datasheet/6948f.pdf

The Linear Technology VCO offers four over-lapping frequency ranges, each one a lot wider the AD9915's 2.4 to 2.5GHz - LT's lowest range is 2.240 to 3..740GHz which does suggest that their tank circuit has a lower Q than the AD9915's.

> TANSTAAFL.

All design involves balancing costs and benefits. I'm not interested enough to work out what dBc/Hz actually mean, but it looks as if you aren't either, and John would be out of his depth if he tried to find out.

Some of the people who post here are probably clever enough - or at least deep enough into working out noise floors - that we can hope for an illuminating response from them.

Phil Hobbs would probably be happy to advertise expertise in that area, and could well have it.

--
Bill Sloman, Sydney

 

[Jasen Betts]

On 2014-09-11, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

Nope. With binary, the DDS output frequency is an integer multiple of
f_ref/2**N, whereas with BCD it's an integer multiple of f_ref/10**M.
So you can write the same integer, but it won't produce the same output
frequency.

it needen't be. the phase accmulator can have any limit you want.
you only beed to add an extra constant after every zero crossing.




--
umop apisdn


--- news://freenews.netfront.net/ - complaints: news@netfront.net ---

 

[Dimitrij Klingbeil]

On 10.09.2014 02:48, Tom Miller wrote:

"John Larkin" <jlarkin@highlandtechnology.com> wrote in message
news:bl3v0apm50e5lrfir5kdjpgla5ob71acip@4ax.com...

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.

Use a VCOCXO, a very stable oscillator and a long time constant in the
loop.

Hi John

Additionally (provided you get the DDS to "hit" 10MHz sufficiently
exactly) consider removing part of the steps in the "stairstep" DAC
output by "blanking them out" with something like this:

http://bayimg.com/kaAAoaagG (warning: messy handwriting)

The whole thing is essentially a "track and resonate" circuit - like a
classic "track and hold", but with the "hold" part replaced by a free
running resonator (quartz or LC or whatever kind suits you best).

The idea is to move the main part of the noise spectrum from 155-ish MHz
and its multiples to a higher frequency (250-ish MHz or as high as the
switch will do) and its multiples in order to make filtering easier. In
theory one could move the noise into the GHz, but hardly any real world
analog switch will be able to drive so narrow pulses. If a PO3B3305A can
hit anything above 250MHz that's probably as high as reasonably
expectable. At low frequencies something like this should be really
easy, but your required frequency is really pushing it.

Of course it's more of a wild guess than a real design and it depends on
an already very fast analog switch, driven to the limit of its switching
rate, to be "fast enough" - which i'm not entirely sure that it will be.
Anyway, maybe it gives you some ideas...

Regards
Dimitrij

 

[rickman]

On 9/11/2014 8:24 PM, John Larkin wrote:

But it still won't allow me to make exactly 10 MHz from a binary DDS
clocked at 155.52.

Why does it have to be a binary DDS? This has already been discussed
here that you can make a DDS roll over at any number you want. I
believe someone already did the math for you. I simply pointed out a
few optimizations that would be useful if you were using it to
synthesize a sine wave.

Now you are talking about producing a clock which is idiot simple
really. In fact this circuit is no longer a DDS, but rather what I
believe is called an NCO... don't hold me to that term, I find there are
many names for these rather similar circuits and I can't keep them all
straight. The point is, yes, you can produce a 10 MHz clock *exactly*
from your 155.52 MHz reference. You can also get a remainder at the
time of the clock if you want to use that to trim your VCXO.

--

Rick

 

[Bill Sloman]

On Saturday, 13 September 2014 03:32:37 UTC+10, John Larkin wrote:

On Fri, 12 Sep 2014 03:31:49 +0100, Mike Perkins <spam@spam.com
wrote:
On 11/09/2014 11:20, Mike Perkins wrote:
On 10/09/2014 00:54, John Larkin wrote:

We can compare with this single cycle (with a 100ns period) with the
cycle we have from the reference 10MHz using a phase comparator.

We have all come across DDS's that use a binary count, but there is no
reason why the count can't be modulo an alternative number. Of course
the phase table length must suit.

A scheme like that would work if all I needed was a stable frequency.

But I also want picosecond timing accuracy. Things like DACs, lowpass
filters, and phase detectors will all have drift with time and
temperature, and a picosecond is a cruel unit of measure.

The picosecond timing accuracy can only between successive cycles of the 155.52MHz VCXO, and you maintain that by maintaining the VCXO frequency stability at precisely 155.5200000 MHz vis a vis a 10.0000 MHz crystal clock.

The PPL loop that ties the 155.52MHz VCXO output to the 10MHz reference output stops long term phase shift between the two, but control only the relative phase-shift, not the absolute phase shift.

Short term phase jitter inside the PLL feedback path doesn't matter, so long as it long-term averages to less than a picosecond - or whatever - before it can build up enough to shift the phase of the 155.52MHz VCXO.

The fact that a phase detector operating at 80kHz could have a 1psec relative stability misses the point that dividing the 155.52MHz down to 80kHz introduces more than a 1psec of phase shift, as does dividing 10MHz down to 80kHz.

Insisting on 1psec absolute cycle to cycle stability in the phase detector, ignores all of that, and the delays through the filtering after the phase detector which is absolutely necessary if the noise on the phase detector output isn't going to produce phase noise on the sine wave coming out of the VCXO.

> An ECL bangbang phase detector is the only thing I can think of that has picosecond time stability, and it looks like it must work at 80 KHz. As Phil suggests, it could be the DC part of a compound loop.

A product detector is going to have a similar timing stability, even if it doesn't have data-sheet entries saying what they are, and it's going to be a lot less sensitive to local noise sources (like spikes on the rails) because they average out, rather than being broad-band sampled at switching time.

Concentrating on the propagation delays in the phase detector, while ignoring the propagation delays in the components feeding it, and those processing its output, does look rather like tunnel-vision.

--
Bill Sloman, Sydney

 

[Jan Panteltje]

On a sunny day (Fri, 12 Sep 2014 19:28:21 -0400) it happened Phil Hobbs
<hobbs@electrooptical.net> wrote in <54138195.8000608@electrooptical.net>:

If you can't calculate how good it _could_ be, how do you know when
you're done?

When it meets customer specs man!

 

[Jan Panteltje]

On a sunny day (Fri, 12 Sep 2014 19:19:41 -0400) it happened Phil Hobbs
<hobbs@electrooptical.net> wrote in <54137F8D.3040706@electrooptical.net>:

On 9/12/2014 3:37 PM, Jan Panteltje wrote:
On a sunny day (Fri, 12 Sep 2014 12:02:30 -0700) it happened John Larkin
jlarkin@highlandtechnology.com> wrote in
ueg61a5nrr0q77ht8sbskhgp7mm1q5pj1n@4ax.com>:

That way I can (a) select the best possible approach, and (b) know when
it isn't there yet. I couldn't do my job without crunching a fair bit
of math. My rule of thumb is that the final result gets within 1 dB of
the theory most of the time, and within 3 dB almost always (i.e. unless
I've made a math blunder or failed to think of some physical effect that
turns out to be important).

You're more math-y than I am, so I tend to simulate more [1].
Electronic circuits are often sufficiently nonlinear that simulation
is more useful than algebra. When you can trust it, of course.

And there's always soldering.

[1] or have a lackey do the math.

Electronics is like driving a car or flying like a bird.
You do not, as bird, use take off weight, calculate needed runway length,
get weather report, fuel..., vectors, you just flap the wings and go.

So _that's_ why your schematics look like birds' nests.

Yup!

 

[Phil Hobbs]

On 9/12/2014 8:07 PM, Jasen Betts wrote:

On 2014-09-11, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

Nope. With binary, the DDS output frequency is an integer multiple of
f_ref/2**N, whereas with BCD it's an integer multiple of f_ref/10**M.
So you can write the same integer, but it won't produce the same output
frequency.

it needen't be. the phase accmulator can have any limit you want.
you only beed to add an extra constant after every zero crossing.

Unless I'm mistaking your meaning, all that does is change the duty cycle.

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Jasen Betts]

On 2014-09-13, Phil Hobbs <hobbs@electrooptical.net> wrote:

On 9/12/2014 8:07 PM, Jasen Betts wrote:
On 2014-09-11, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

Nope. With binary, the DDS output frequency is an integer multiple of
f_ref/2**N, whereas with BCD it's an integer multiple of f_ref/10**M.
So you can write the same integer, but it won't produce the same output
frequency.

it needen't be. the phase accmulator can have any limit you want.
you only beed to add an extra constant after every zero crossing.

Unless I'm mistaking your meaning, all that does is change the duty cycle.

it means you can count 1000000 per cycle, or 999983, if that works
better, you're not limited to a power of 2

just watch the carry out of the accululator and when it hits add an
extra amount to bridge the gap between desired and total count.

eg for a 13 count on a 4 bit accumulator you'd add 3

so if the step size is 5 it's go from 15 to 7 (by way of 4)

T P
---------
0 15
1 7 (was 4)
2 12
3 4 (was 1)
4 9
5 14
6 6 (was 3)
7 11
8 3 (was 0)
9 8
10 13
11 5 (was 2)
12 10
13 15


you could get a tidier result by adding 5 when the P < 8 (= 16 -5 -3 )
and 8 ( = 5 + 3 ) otherwise.

Or possibly simpler add 8 on the clock after a carry (falling edge of
the high bit) and 5 otherwise, that leaves a gap in the P values at 5
,6,7 so you'd need to chop the wave table into two parts,



thus if you need to divide by pi you can get very close with a 355
valued phase accumulator and a step of 133.

--
umop apisdn


--- news://freenews.netfront.net/ - complaints: news@netfront.net ---

 

[rickman]

On 9/13/2014 12:44 AM, Bill Sloman wrote:

The PPL loop that ties the 155.52MHz VCXO output to the 10MHz reference output stops long term phase shift between the two, but control only the relative phase-shift, not the absolute phase shift.

I don't follow this at all. What is the difference between the two in
this case? There will be a relative measurement and that will be
brought to zero by the loop. So what is the "absolute" phase shift? Or
are you talking about the short term phase shift of the VCXO?


> Short term phase jitter inside the PLL feedback path doesn't matter, so long as it long-term averages to less than a picosecond - or whatever - before it can build up enough to shift the phase of the 155.52MHz VCXO.

That is not clear to me. "Build up" is not something I can picture in
this circuit. Any deviation will result in noise and phase shift of the
VCXO output. The question is just how large that deviation is. I guess
you are saying that the filter can average out the deviations well
enough. John seems to think that can cause other problems or maybe he
just doesn't have confidence in this idea because he hasn't played with
it yet. He admits he is not a math guy and prefers to test and simulate.


> The fact that a phase detector operating at 80kHz could have a 1psec relative stability misses the point that dividing the 155.52MHz down to 80kHz introduces more than a 1psec of phase shift, as does dividing 10MHz down to 80kHz.

What I read was that John would divide one of the frequencies to
determine which edge of the clock to compare, but the comparison would
be done between the two clocks, not the divided clock. The divided
clock would be used as an enable on the phase comparison in effect.


> Insisting on 1psec absolute cycle to cycle stability in the phase detector, ignores all of that, and the delays through the filtering after the phase detector which is absolutely necessary if the noise on the phase detector output isn't going to produce phase noise on the sine wave coming out of the VCXO.

You can't do any better than the phase comparator. So I can see why he
want's that as good as possible. But the delays introduced *after* the
phase comparator will not produce phase errors. That delay is only of
consequence to the loop stability.

--

Rick