PLL tricks

[Bill Sloman]

On Thursday, 11 September 2014 08:19:33 UTC+10, John Larkin wrote:

On Wed, 10 Sep 2014 22:44:34 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 10.09.2014 um 18:49 schrieb John Larkin:

Thing about a DDS is that it can only output edges aligned with input
edges. In my case, 10MHz and 155.52 MHz edges align once every 12.5
usec. Changing the DDS radix can let me synthesize 10.000 MHz from
155.52, but it can only do that by jittering edges around an average
value. So, that would put me back to needing analog precision in the
phase detector. Less than before, but still intimidating.

There is no jitter, the low pass after the DAC is part of the game.

A DAC, lowpass (or bandpass) filter, and comparator get me back into
the high-precision analog business as regards picosecond timing
accuracy.

The DAC is built into the DDS. The low-pass filter doesn't have to be high-precision analog - it's just filtering out the spurs at 155.52MHz and its odd multiples.

If your 10MHz reference oscillator is producing a decent sine wave (which shouldn't be difficult to arrange) and you use tolerably linear multiplying detector - my first thought would be an AD834, but it has been around for a while now - the residual spurs won't produce much in the way of DC output.

The comparator shouldn't have been there in the first place.

You will need an integrator (with a resistor in series with the integrating capacitor to turn the phase-detector output into a drive voltage for the VCXO, but that's all low-frequency stuff.

But now, with plenty 24*24 Multipliers in an FPGA, that are obscenely
cheap and that run at hundreds of MHz, I would do the phase comparision
in the digital domain. Then you get a near-DC control voltage that
is oversampled at 10 or even 155 MSPS, easy to filter.

But where do you get the 24-bit number you want to multiply? You've got to count 100msec worth of 155.52MHz to get 2^24. that makes for a rather slow control loop.

When the 10 MHz ref is only 0/1, even a multiplier might be a
luxury. And the DAC also, a PWM output might do.

Ooohps, I'm getting Joergish!

Not anything like as Joergish as you like to think. Joerg is good at electronics.

> Yikes! You'll be chopping firewood next.

That he may be able to manage.

--
Bill Sloman, Sydney

 

[Gerhard Hoffmann]

Am 11.09.2014 um 07:40 schrieb josephkk:

The DDS concept is an integer divide system, binary or BCD makes no
difference.

No, it's neither an integer divide system nor does BCD make no difference.

A counter is an integer divide system.

The frequency resolution of a 48 bit DDS is f_clock/2**48 which is
anything but integer and you can get only multiples of the
resolution out. You may be very close to your intended frequency
but microHz away and that gives you a constant phase creep.

With a BCD DDS your step size can be f_clock / 10e6 and that
that is an advantage if you need a frequency that can be
exactly written in a few decimal digits.


And also, you need the lowpass after the dds only if you
cross the boundary from a sampled to a continuous system.

For example in a software defined radio it is perfectly
legal to multiply the data from the antenna ADC with the
output from the sin&cos table to convert them to an IF
or to baseband. There is no low pass involved.


That makes it attractive to do the phase comparison in the
sampled domain and to d/a convert only the tune voltage to
the VCXO which is just nervous DC.

The loop integrator would be digital, too; it's just an adder
and a register. Sorry, no precision op amp and foil capacitors.

There is not much need to maximize loop bandwidth to
correct the 1/f noise, the telecom people ignore the first
few KHz altogether, where it's hard.

Those ps numbers carry a completely different meaning in
normal time distribution and navigation.

Gerhard

 

[Mike Perkins]

On 10/09/2014 00:54, John Larkin wrote:

If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.

An idea came to me that may or may not be of interest.

You can get multi-bit DACs at several hundred MSPS and higher but I
presume there is an upper limit to your project inventory.

The use of a DDS has been mentioned and of course most DDS's would use a
binary 32 bit counter.

Have you considered using a non-binary count, one that is a multiple of
125? Your lookup phase table would also need to be modified and 3 * 2>>n
would need to be subtracted when the counter wraps round.

Then use a phase comparator at 10MHz with very simple filtering to drive
your VXCO.

You could use a multiple of 155.52MHz to drive the DDS though most FPGA
would only play ball at fundamental. If a FPGA has a DDR interface is
used then certainly it is possible to double up on samples even with a
slow FPGA and indeed is something I have done.

This would maintain a perfect phase relationship between the 10MHz and
the 155.52MHz.

--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk

 

[Bill Sloman]

On Friday, 12 September 2014 01:03:22 UTC+10, Phil Hobbs wrote:

On 09/11/2014 08:42 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

The DDS concept is an integer divide system, binary or BCD makes
n difference.

No, it's neither an integer divide system nor does BCD make no
difference.

A counter is an integer divide system.

The frequency resolution of a 48 bit DDS is f_clock/2**48 which is
anything but integer and you can get only multiples of the
resolution out. You may be very close to your intended frequency
but microHz away and that gives you a constant phase creep.

But you can change the frequency by one resolution step from time to
time, and reverse the phase creep - if you need to. Half a microHerz
is rather more precise than John Larkin's 10MHz clock is ever going
to be. With an atomic clock system, you might want to manipulate the
phase creep, but not here.

With a BCD DDS your step size can be f_clock / 10e6 and that that
is an advantage if you need a frequency that can be exactly written
in a few decimal digits.

But you can write exactly the same number in rather fewer hexadecimal
digits, as long as you remember to include the trailing zeros as
digits.

Nope. With binary, the DDS output frequency is an integer multiple of
f_ref/2**N, whereas with BCD it's an integer multiple of f_ref/10**M.

It's still the same number, even if it won't generate the same frequency.

Essentially, using decimal numbers is a bad idea. It uses more silicon area to achieve much the same result.

So you can write the same integer, but it won't produce the same output
frequency.

Obviously.

And if you knew your reference clock frequency that precisely.

Or, as is quite likely, other things are locked to that same reference,
and need to interoperate.

That's a problem of clock distribution - which is interesting in it's own right, but not what's been being talked about here.

The big problem with the DDS idea is the DAC+filter. In order to get
rid of the jitter sidebands down to 1 ps, the analog stuff has to be
accurate and stable to about 1 ps * 2 pi *155.2 MHz ~= 0.1%.

Rubbish. The DAC is just producing a tolerable approximation to a sine wave, and the imperfections should get largely get filtered out before the DDS output gets into the phase detector. Most of the side-band products get filtered after the detector anyway, and any DC that's left is a constant (and small) phase offset, not a frequency offset (if you do it anything like right).

> The bang-bang PLL is pretty good for the price.

It's a can of worms. Any noise on the rails can creep on and shift the switching point. A product phase detector is a lot more forgiving.

I'm not sure it wouldn't work fine at 80 kHz, if John doesn't need the
wide control bandwidth.

If he went out and bought a decent VXCO, which was an off-the-shelf item 20 years ago, and ON-Semiconductor now seems to offer as an SMD component, he could live with a really slow and heavily filtered phase detector running at 80kHz, but either a DDS or a fractional-N divider could be made to work at 10MHz and would give much faster feedback.

In a frequency multiplier, the RMS _phase_noise_ goes up by a factor of
N, but that's because the period gets shorter and the _jitter_ stays the
same (provided you get rid of the jitter of the dividers).

So John, how about that 80 kHz bang-bang thing with a picosecond ECL
D-flop following each divider? Your loop bandwidth will be smaller, but
the jitter should be fine.

Resynchronising TTL outputs with an ECL bistable would work fine. The last time I did that was with a 200MHz clock and the delay tolerance through the TTL was more than 5nsec, so we got the user to pick the one of four possible edges that was furthest away from the actual TTL transition and select it with a pair of switches.

Worked fine until some half-witted graduate student hooked up the balanced clock drives wrong way round, which moved the active edge from the best place to the worst place ...

It was the usual tidying up ten years after the original design kind of job, so it was all a bit rough.

--
Bill Sloman, Sydney

 

[Bill Sloman]

On Friday, 12 September 2014 00:19:42 UTC+10, John Larkin wrote:

On Wed, 10 Sep 2014 22:40:12 -0700, josephkk

joseph_barrett@sbcglobal.net> wrote:



On Wed, 10 Sep 2014 07:21:30 -0700, John Larkin

jlarkin@highlandtechnology.com> wrote:



On Wed, 10 Sep 2014 10:54:45 +0200, Gerhard Hoffmann

ghf@hoffmann-hochfrequenz.de> wrote:



Am 10.09.2014 um 01:54 schrieb John Larkin:



I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but

that sounds jitterey to me, and it looks like I can't hit the exact

frequency ratio anyhow.



Dividing EXACTLY with a DDS can be surprisingly hard, one could

find that one is always off by 2e-32 or 2e-48 or whatever

but one is never exactly on the spot, never really synchronous.





Right. One rounding bit out of 48, or even 64, would give me a slow

phase creep.







Once, there was a BCD coded DDS from Stanford IIRC that

could get it exact for easy-to-write decimal numbers.



Yeah, decimal might work.

Today one could put it into an FPGA. A BCD based adder
is easy. I have put a VHDL-only sine table on opencores.org
that should also be easy to modify.

That is interesting. We might look into a decimal DDS.

The DDS concept is an integer divide system, binary or BCD makes no
difference.

No, it's a fractional multiply concept, and some fractions can be
expressed exactly in some radixes but not in others.

Try expressing 1/5 as a binary fractional.

1/101 (binary).

When you can pick a fraction of 2^48 you can usually express what you want more accurately than you can measure it or specify it.

--
Bill Sloman, Sydney

 

[Bill Sloman]

On Friday, 12 September 2014 01:37:17 UTC+10, Phil Hobbs wrote:

On 09/11/2014 09:03 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 08:19:33 UTC+10, John Larkin wrote:
On Wed, 10 Sep 2014 22:44:34 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 10.09.2014 um 18:49 schrieb John Larkin:

Thing about a DDS is that it can only output edges aligned with
input edges. In my case, 10MHz and 155.52 MHz edges align once
every 12.5 usec. Changing the DDS radix can let me synthesize
10.000 MHz from 155.52, but it can only do that by jittering
edges around an average value. So, that would put me back to
needing analog precision in the phase detector. Less than
before, but still intimidating.

There is no jitter, the low pass after the DAC is part of the
game.

A DAC, lowpass (or bandpass) filter, and comparator get me back
into the high-precision analog business as regards picosecond
timing accuracy.

The DAC is built into the DDS. The low-pass filter doesn't have to be
high-precision analog - it's just filtering out the spurs at
155.52MHz and its odd multiples.

The DDS will have to have a high speed clock, e.g. 500 MHz or 1 GHz.

Not in this context.

If you want something - as John does - to let you compare your 155.52MHZ VCO with a good quality 10MHz reference oscillator, the DDS is driven directly from the 155.52MHz oscillator John wants to stabilise and lock to the 10MHz reference oscillator.

A fractional-N divider would be cheaper, but messier.

You can buy DDS with a built-in frequency multiplier.

http://www.analog.com/static/imported-files/data_sheets/AD9915.pdf

has an internal VCO that runs between 2.4 and 2.5 GHz which could be locked to a multiple of 10MHz reference, but if you'd bought that you'd use it to generate the 155.52MHz output directly, and leave all the phase detection etc to the insides of the Analog Devices chip.

The digital spurs have a different phase relationship with the sine wave
output on different cycles, so they need to be filtered out to an
accuracy of about

H ~ delta phi = 1 ps * 2 pi * 155.2 MHz = 0.1%.

Only if you were silly enough to use an edge sensitive phase detector. Product phase detectors are lot more tolerant and forgiving.

That has to happen between 155.2 MHz and f_fast - 155.2 MHz, which for a
500 MHz f_fast is a pretty sharp filter. It can be done, but it doesn't
happen by accident.

Happily, it doesn't need to be done that well, or anything like that well.

If your 10MHz reference oscillator is producing a decent sine wave
(which shouldn't be difficult to arrange) and you use tolerably
linear multiplying detector - my first thought would be an AD834, but
it has been around for a while now - the residual spurs won't produce
much in the way of DC output.

The drift will be horrible. 1 ps is 62 microradians at 10 MHz, so a
drift of 0.006% of full scale eats up the whole timing margin. It's
dramatically harder at 80 kHz, because the resulting jitter goes as N,
unlike the bang-bang loop.

What drift?

The whole point of a second order phase locked loop with an integrator driving the VCO is that the waveform coming out of the divider from the VCO is forced into a fixed phase relationship with the waveform coming out of the reference.

High frequency harmonic content on the DDS output would mean that the fixed phase relationship wouldn't be quite where it would be for a pure sine wave, but it won't move around unless the harmonic content changes, which it won't.

Floyd M. Gardner is a full bottle on the subject. The loop filter I've got in mind (and have used from time to time) is figure 6.1 (b) in his book.

--
Bill Sloman, Sydney

 

[Bill Sloman]

On Friday, 12 September 2014 01:52:01 UTC+10, Phil Hobbs wrote:

On 09/11/2014 11:38 AM, Bill Sloman wrote:
On Friday, 12 September 2014 01:03:22 UTC+10, Phil Hobbs wrote:
On 09/11/2014 08:42 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

The DDS concept is an integer divide system, binary or BCD
makes n difference.

No, it's neither an integer divide system nor does BCD make no
difference.

A counter is an integer divide system.

The frequency resolution of a 48 bit DDS is f_clock/2**48 which
is anything but integer and you can get only multiples of the
resolution out. You may be very close to your intended
frequency but microHz away and that gives you a constant phase
creep.

But you can change the frequency by one resolution step from time
to time, and reverse the phase creep - if you need to. Half a
microHerz is rather more precise than John Larkin's 10MHz clock
is ever going to be. With an atomic clock system, you might want
to manipulate the phase creep, but not here.

With a BCD DDS your step size can be f_clock / 10e6 and that
that is an advantage if you need a frequency that can be
exactly written in a few decimal digits.

But you can write exactly the same number in rather fewer
hexadecimal digits, as long as you remember to include the
trailing zeros as digits.

Nope. With binary, the DDS output frequency is an integer multiple
of f_ref/2**N, whereas with BCD it's an integer multiple of
f_ref/10**M.

It's still the same number, even if it won't generate the same
frequency.

Essentially, using decimal numbers is a bad idea. It uses more
silicon area to achieve much the same result.

So you can write the same integer, but it won't produce the same
output frequency.

Obviously.

And if you knew your reference clock frequency that precisely.

Or, as is quite likely, other things are locked to that sam
reference, and need to interoperate.

That's a problem of clock distribution - which is interesting in it's
own right, but not what's been being talked about here.

The big problem with the DDS idea is the DAC+filter. In order to
get rid of the jitter sidebands down to 1 ps, the analog stuff has
to be accurate and stable to about 1 ps * 2 pi *155.2 MHz ~= 0.1%.

Rubbish. The DAC is just producing a tolerable approximation to a
sine wave, and the imperfections should get largely get filtered out
before the DDS output gets into the phase detector.

Quit pontificating and do the math. It's as I said. Phase error due to
additive signals goes as the spur amplitude divided by the maximum phase
slope of the desired signal. 'Tain't rocket science.

Not in a product detector. And the phase error is static and should be small. The higher frequency harmonics cancel out in proportion to the harmonic number when you integrate over a whole cycle.

Most of the
side-band products get filtered after the detector anyway, and any DC
that's left is a constant (and small) phase offset, not a frequency
offset (if you do it anything like right).

The bang-bang PLL is pretty good for the price.

It's a can of worms. Any noise on the rails can creep on and shift
the switching point. A product phase detector is a lot more
forgiving.

John has shipping products with 1-ps jitter. I have a digital delay box
of his that has 5 ps of jitter, which is about 35 dB better than the SRS
box I used to have. So rather than preening yourself, you might listen
and learn.

I was doing as well twenty years ago, when it was all a bit more difficult.
It was Gigabit Logic's GaAs parts back then - ECLinPS (which I've used) is easier to use and ECLinPS+ is now a bit faster.

The fact that John can make his stuff work is impressive - lots of people can't - but I did as well quite a while earlier, and so far I'm not hearing anything that anybody ought to take too seriously.

I'm not sure it wouldn't work fine at 80 kHz, if John doesn't nee
the wide control bandwidth

If he went out and bought a decent VXCO, which was an off-the-shelf
item 20 years ago, and ON-Semiconductor now seems to offer as an SMD
component, he could live with a really slow and heavily filtered
phase detector running at 80kHz, but either a DDS or a fractional-N
divider could be made to work at 10MHz and would give much faster
feedback.

John was asking for a smart idea, in order to save money.

He got several, and didn't seem to take any of them seriously.

Money is good. I like money, John likes money, and so do you. I'd much
rather deploy a smart idea than spend extra money. So would you,
provided the idea was yours.

Several people have pointed out that fractional-N would work at 10MHz. I'd be happier using it with a product phase detector, but the jitter from the moving fractional-N edges can get filtered out before it gets anywhere near the VCO drive. DDS is cuter, but DDS chips are expensive - the AD9102 costs $30.

The chemically thinned 155.52MHz crystal for a VCXO wouldn't be all that cheap, but if ON-Semiconductor is putting them into SMD packages the process for making them must be pretty thoroughly automated.

--
Bill Sloman, Sydney

 

[Bill Sloman]

On Friday, 12 September 2014 01:52:01 UTC+10, Phil Hobbs wrote:

On 09/11/2014 11:38 AM, Bill Sloman wrote:
On Friday, 12 September 2014 01:03:22 UTC+10, Phil Hobbs wrote:
On 09/11/2014 08:42 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

Rubbish. The DAC is just producing a tolerable approximation to a
sine wave, and the imperfections should get largely get filtered out
before the DDS output gets into the phase detector.

Quit pontificating and do the math. It's as I said. Phase error due to
additive signals goes as the spur amplitude divided by the maximum phase
slope of the desired signal. 'Tain't rocket science.

I suspect that you've done the math you usually do, which is for random noise at different frequencies.

In this situation, the harmonic content is pretty much deterministic, and the same from one cycle to the next. As I said, it can create a static phase shift, but no noise or drift. In the fractional-N at 10MHz system, successive cycles will have different phase shifts - within a 6.4nsec window - but that will repeat exactly every 12.5usec, and most of it will cancel out a lot more rapidly.

--
Bill Sloman, Sydney

 

[John Larkin]

On Wed, 10 Sep 2014 22:40:12 -0700, josephkk
<joseph_barrett@sbcglobal.net> wrote:

On Wed, 10 Sep 2014 07:21:30 -0700, John Larkin
jlarkin@highlandtechnology.com> wrote:

On Wed, 10 Sep 2014 10:54:45 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:

Am 10.09.2014 um 01:54 schrieb John Larkin:

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.

Dividing EXACTLY with a DDS can be surprisingly hard, one could
find that one is always off by 2e-32 or 2e-48 or whatever
but one is never exactly on the spot, never really synchronous.


Right. One rounding bit out of 48, or even 64, would give me a slow
phase creep.



Once, there was a BCD coded DDS from Stanford IIRC that
could get it exact for easy-to-write decimal numbers.

Yeah, decimal might work.


Today one could put it into an FPGA. A BCD based adder
is easy. I have put a VHDL-only sine table on opencores.org
that should also be easy to modify.

That is interesting. We might look into a decimal DDS.

The DDS concept is an integer divide system, binary or BCD makes no
difference.

No, it's a fractional multiply concept, and some fractions can be
expressed exactly in some radixes but not in others.

Try expressing 1/5 as a binary fractional.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[John Larkin]

On Thu, 11 Sep 2014 00:32:56 -0500, Joe Chisolm
<jchisolm6@earthlink.net> wrote:

On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin wrote:

If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.

You trying to build a OC3 framer but with a 10MHz refclock?

I'm trying to fire the world's biggest laser.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Phil Hobbs]

On 09/11/2014 08:42 AM, Bill Sloman wrote:

On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

The DDS concept is an integer divide system, binary or BCD makes
n difference.

No, it's neither an integer divide system nor does BCD make no
difference.

A counter is an integer divide system.

The frequency resolution of a 48 bit DDS is f_clock/2**48 which is
anything but integer and you can get only multiples of the
resolution out. You may be very close to your intended frequency
but microHz away and that gives you a constant phase creep.

But you can change the frequency by one resolution step from time to
time, and reverse the phase creep - if you need to. Half a microHerz
is rather more precise than John Larkin's 10MHz clock is ever going
to be. With an atomic clock system, you might want to manipulate the
phase creep, but not here.

With a BCD DDS your step size can be f_clock / 10e6 and that that
is an advantage if you need a frequency that can be exactly written
in a few decimal digits.

But you can write exactly the same number in rather fewer hexadecimal
digits, as long as you remember to include the trailing zeros as
digits.

Nope. With binary, the DDS output frequency is an integer multiple of
f_ref/2**N, whereas with BCD it's an integer multiple of f_ref/10**M.
So you can write the same integer, but it won't produce the same output
frequency.

And if you knew your reference clock frequency that precisely.

Or, as is quite likely, other things are locked to that same reference,
and need to interoperate.

The big problem with the DDS idea is the DAC+filter. In order to get
rid of the jitter sidebands down to 1 ps, the analog stuff has to be
accurate and stable to about

1 ps * 2 pi *155.2 MHz ~= 0.1%.

The bang-bang PLL is pretty good for the price.

I'm not sure it wouldn't work fine at 80 kHz, if John doesn't need the
wide control bandwidth.

In a frequency multiplier, the RMS _phase_noise_ goes up by a factor of
N, but that's because the period gets shorter and the _jitter_ stays the
same (provided you get rid of the jitter of the dividers).

So John, how about that 80 kHz bang-bang thing with a picosecond ECL
D-flop following each divider? Your loop bandwidth will be smaller, but
the jitter should be fine.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[John Larkin]

On Thu, 11 Sep 2014 11:03:22 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 09/11/2014 08:42 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

The DDS concept is an integer divide system, binary or BCD makes
n difference.

No, it's neither an integer divide system nor does BCD make no
difference.

A counter is an integer divide system.

The frequency resolution of a 48 bit DDS is f_clock/2**48 which is
anything but integer and you can get only multiples of the
resolution out. You may be very close to your intended frequency
but microHz away and that gives you a constant phase creep.

But you can change the frequency by one resolution step from time to
time, and reverse the phase creep - if you need to. Half a microHerz
is rather more precise than John Larkin's 10MHz clock is ever going
to be. With an atomic clock system, you might want to manipulate the
phase creep, but not here.

With a BCD DDS your step size can be f_clock / 10e6 and that that
is an advantage if you need a frequency that can be exactly written
in a few decimal digits.

But you can write exactly the same number in rather fewer hexadecimal
digits, as long as you remember to include the trailing zeros as
digits.

Nope. With binary, the DDS output frequency is an integer multiple of
f_ref/2**N, whereas with BCD it's an integer multiple of f_ref/10**M.
So you can write the same integer, but it won't produce the same output
frequency.


And if you knew your reference clock frequency that precisely.

Or, as is quite likely, other things are locked to that same reference,
and need to interoperate.

The big problem with the DDS idea is the DAC+filter. In order to get
rid of the jitter sidebands down to 1 ps, the analog stuff has to be
accurate and stable to about

1 ps * 2 pi *155.2 MHz ~= 0.1%.

The bang-bang PLL is pretty good for the price.

I'm not sure it wouldn't work fine at 80 kHz, if John doesn't need the
wide control bandwidth.

In a frequency multiplier, the RMS _phase_noise_ goes up by a factor of
N, but that's because the period gets shorter and the _jitter_ stays the
same (provided you get rid of the jitter of the dividers).

So John, how about that 80 kHz bang-bang thing with a picosecond ECL
D-flop following each divider? Your loop bandwidth will be smaller, but
the jitter should be fine.

Right. The dividers would be in an FPGA, but their outputs would be
resynchronized to the two clocks, with ECL flipflops, to keep the
jitter and drift down. Differential Eclips flops have sub-ps decision
windows that have near zero temperature coefficients.

As far as the loop filter goes, the 155.52 VCXO will have some 1/f
type jitter vs delay curve, which gets better as dollars are added.
That curve doesn't matter at frequencies where the PLL asserts
control. A slow loop filter forces me to buy a bigger, better VCXO
that has less close-in phase noise. And it's hard to find a really
good SC-cut OCXO oscillator at 155.52. The nice LVPECL VCXOs are tiny
surface-mount things.

A really good soup-can sized SC-cut OCXO might have 1 ps of RMS jitter
at 1 second delay. A cheap surface-mount XO might be 10 ns.

I can probably make it work at 80KHz, but I was hoping for some sneaky
trick to get the phase detector frequency up.

The math of this - dividing to 80K, bangbang detector, loop filter,
VCXO - is beyond me, so the best way to do it is to have a lackey
breadboard a few versions. Even then it will be a challenge to test.

Last time I did a bangbang loop, I modeled the phase detector as a
linear slope of voltage vs time error, with the width equal to some
assumed jitter in both clocks, 20 ps or some such. That seemed to
work.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Phil Hobbs]

On 09/11/2014 09:03 AM, Bill Sloman wrote:

On Thursday, 11 September 2014 08:19:33 UTC+10, John Larkin wrote:
On Wed, 10 Sep 2014 22:44:34 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 10.09.2014 um 18:49 schrieb John Larkin:

Thing about a DDS is that it can only output edges aligned with
input edges. In my case, 10MHz and 155.52 MHz edges align once
every 12.5 usec. Changing the DDS radix can let me synthesize
10.000 MHz from 155.52, but it can only do that by jittering
edges around an average value. So, that would put me back to
needing analog precision in the phase detector. Less than
before, but still intimidating.

There is no jitter, the low pass after the DAC is part of the
game.

A DAC, lowpass (or bandpass) filter, and comparator get me back
into the high-precision analog business as regards picosecond
timing accuracy.

The DAC is built into the DDS. The low-pass filter doesn't have to be
high-precision analog - it's just filtering out the spurs at
155.52MHz and its odd multiples.

The DDS will have to have a high speed clock, e.g. 500 MHz or 1 GHz.
The digital spurs have a different phase relationship with the sine wave
output on different cycles, so they need to be filtered out to an
accuracy of about

H ~ delta phi = 1 ps * 2 pi * 155.2 MHz = 0.1%.

That has to happen between 155.2 MHz and f_fast - 155.2 MHz, which for a
500 MHz f_fast is a pretty sharp filter. It can be done, but it doesn't
happen by accident.

If your 10MHz reference oscillator is producing a decent sine wave
(which shouldn't be difficult to arrange) and you use tolerably
linear multiplying detector - my first thought would be an AD834, but
it has been around for a while now - the residual spurs won't produce
much in the way of DC output.

The drift will be horrible. 1 ps is 62 microradians at 10 MHz, so a
drift of 0.006% of full scale eats up the whole timing margin. It's
dramatically harder at 80 kHz, because the resulting jitter goes as N,
unlike the bang-bang loop.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Phil Hobbs]

On 09/11/2014 11:38 AM, Bill Sloman wrote:

On Friday, 12 September 2014 01:03:22 UTC+10, Phil Hobbs wrote:
On 09/11/2014 08:42 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

The DDS concept is an integer divide system, binary or BCD
makes n difference.

No, it's neither an integer divide system nor does BCD make no
difference.

A counter is an integer divide system.

The frequency resolution of a 48 bit DDS is f_clock/2**48 which
is anything but integer and you can get only multiples of the
resolution out. You may be very close to your intended
frequency but microHz away and that gives you a constant phase
creep.

But you can change the frequency by one resolution step from time
to time, and reverse the phase creep - if you need to. Half a
microHerz is rather more precise than John Larkin's 10MHz clock
is ever going to be. With an atomic clock system, you might want
to manipulate the phase creep, but not here.

With a BCD DDS your step size can be f_clock / 10e6 and that
that is an advantage if you need a frequency that can be
exactly written in a few decimal digits.

But you can write exactly the same number in rather fewer
hexadecimal digits, as long as you remember to include the
trailing zeros as digits.

Nope. With binary, the DDS output frequency is an integer multiple
of f_ref/2**N, whereas with BCD it's an integer multiple of
f_ref/10**M.

It's still the same number, even if it won't generate the same
frequency.

Essentially, using decimal numbers is a bad idea. It uses more
silicon area to achieve much the same result.

So you can write the same integer, but it won't produce the same
output frequency.

Obviously.

And if you knew your reference clock frequency that precisely.

Or, as is quite likely, other things are locked to that same
reference, and need to interoperate.

That's a problem of clock distribution - which is interesting in it's
own right, but not what's been being talked about here.

The big problem with the DDS idea is the DAC+filter. In order to
get rid of the jitter sidebands down to 1 ps, the analog stuff has
to be accurate and stable to about 1 ps * 2 pi *155.2 MHz ~= 0.1%.

Rubbish. The DAC is just producing a tolerable approximation to a
sine wave, and the imperfections should get largely get filtered out
before the DDS output gets into the phase detector.

Quit pontificating and do the math. It's as I said. Phase error due to
additive signals goes as the spur amplitude divided by the maximum phase
slope of the desired signal. 'Tain't rocket science.

Most of the
side-band products get filtered after the detector anyway, and any DC
that's left is a constant (and small) phase offset, not a frequency
offset (if you do it anything like right).

The bang-bang PLL is pretty good for the price.

It's a can of worms. Any noise on the rails can creep on and shift
the switching point. A product phase detector is a lot more
forgiving.

John has shipping products with 1-ps jitter. I have a digital delay box
of his that has 5 ps of jitter, which is about 35 dB better than the SRS
box I used to have. So rather than preening yourself, you might listen
and learn.

I'm not sure it wouldn't work fine at 80 kHz, if John doesn't need
the wide control bandwidth.

If he went out and bought a decent VXCO, which was an off-the-shelf
item 20 years ago, and ON-Semiconductor now seems to offer as an SMD
component, he could live with a really slow and heavily filtered
phase detector running at 80kHz, but either a DDS or a fractional-N
divider could be made to work at 10MHz and would give much faster
feedback.

John was asking for a smart idea, in order to save money.

Money is good. I like money, John likes money, and so do you. I'd much
rather deploy a smart idea than spend extra money. So would you,
provided the idea was yours.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[John Larkin]

On Thu, 11 Sep 2014 11:52:01 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 09/11/2014 11:38 AM, Bill Sloman wrote:
On Friday, 12 September 2014 01:03:22 UTC+10, Phil Hobbs wrote:
On 09/11/2014 08:42 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

The DDS concept is an integer divide system, binary or BCD
makes n difference.

No, it's neither an integer divide system nor does BCD make no
difference.

A counter is an integer divide system.

The frequency resolution of a 48 bit DDS is f_clock/2**48 which
is anything but integer and you can get only multiples of the
resolution out. You may be very close to your intended
frequency but microHz away and that gives you a constant phase
creep.

But you can change the frequency by one resolution step from time
to time, and reverse the phase creep - if you need to. Half a
microHerz is rather more precise than John Larkin's 10MHz clock
is ever going to be. With an atomic clock system, you might want
to manipulate the phase creep, but not here.

With a BCD DDS your step size can be f_clock / 10e6 and that
that is an advantage if you need a frequency that can be
exactly written in a few decimal digits.

But you can write exactly the same number in rather fewer
hexadecimal digits, as long as you remember to include the
trailing zeros as digits.

Nope. With binary, the DDS output frequency is an integer multiple
of f_ref/2**N, whereas with BCD it's an integer multiple of
f_ref/10**M.

It's still the same number, even if it won't generate the same
frequency.

Essentially, using decimal numbers is a bad idea. It uses more
silicon area to achieve much the same result.

So you can write the same integer, but it won't produce the same
output frequency.

Obviously.

And if you knew your reference clock frequency that precisely.

Or, as is quite likely, other things are locked to that same
reference, and need to interoperate.

That's a problem of clock distribution - which is interesting in it's
own right, but not what's been being talked about here.

The big problem with the DDS idea is the DAC+filter. In order to
get rid of the jitter sidebands down to 1 ps, the analog stuff has
to be accurate and stable to about 1 ps * 2 pi *155.2 MHz ~= 0.1%.

Rubbish. The DAC is just producing a tolerable approximation to a
sine wave, and the imperfections should get largely get filtered out
before the DDS output gets into the phase detector.

Quit pontificating and do the math. It's as I said. Phase error due to
additive signals goes as the spur amplitude divided by the maximum phase
slope of the desired signal. 'Tain't rocket science.

Most of the
side-band products get filtered after the detector anyway, and any DC
that's left is a constant (and small) phase offset, not a frequency
offset (if you do it anything like right).

The bang-bang PLL is pretty good for the price.

It's a can of worms. Any noise on the rails can creep on and shift
the switching point. A product phase detector is a lot more
forgiving.

John has shipping products with 1-ps jitter. I have a digital delay box
of his that has 5 ps of jitter, which is about 35 dB better than the SRS
box I used to have. So rather than preening yourself, you might listen
and learn.


I'm not sure it wouldn't work fine at 80 kHz, if John doesn't need
the wide control bandwidth.

If he went out and bought a decent VXCO, which was an off-the-shelf
item 20 years ago, and ON-Semiconductor now seems to offer as an SMD
component, he could live with a really slow and heavily filtered
phase detector running at 80kHz, but either a DDS or a fractional-N
divider could be made to work at 10MHz and would give much faster
feedback.

John was asking for a smart idea, in order to save money.

I'm only going to build 8 of the boxes in question, so money isn't
really a big deal, except for the Joergian sporting aspects. I thought
the PLL math was interesting, and a discussion group does need stuff
to discuss. Talking about problems with other people helps me to
think, too.

I'm not an RF sort of guy - sine waves are BORING - and some people
here are, so it's interesting to get some fresh ideas.

It occurs to me that there's a lot of similarity between a noiseless
bang-bang PLL and a duty-cycle integrating ADC, and a lot of
similarity between a noisy bangbang and a delta-sigma ADC.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Phil Hobbs]

On 09/11/2014 12:29 PM, John Larkin wrote:

On Thu, 11 Sep 2014 11:52:01 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 09/11/2014 11:38 AM, Bill Sloman wrote:
On Friday, 12 September 2014 01:03:22 UTC+10, Phil Hobbs wrote:
On 09/11/2014 08:42 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

The DDS concept is an integer divide system, binary or BCD
makes n difference.

No, it's neither an integer divide system nor does BCD make no
difference.

A counter is an integer divide system.

The frequency resolution of a 48 bit DDS is f_clock/2**48 which
is anything but integer and you can get only multiples of the
resolution out. You may be very close to your intended
frequency but microHz away and that gives you a constant phase
creep.

But you can change the frequency by one resolution step from time
to time, and reverse the phase creep - if you need to. Half a
microHerz is rather more precise than John Larkin's 10MHz clock
is ever going to be. With an atomic clock system, you might want
to manipulate the phase creep, but not here.

With a BCD DDS your step size can be f_clock / 10e6 and that
that is an advantage if you need a frequency that can be
exactly written in a few decimal digits.

But you can write exactly the same number in rather fewer
hexadecimal digits, as long as you remember to include the
trailing zeros as digits.

Nope. With binary, the DDS output frequency is an integer multiple
of f_ref/2**N, whereas with BCD it's an integer multiple of
f_ref/10**M.

It's still the same number, even if it won't generate the same
frequency.

Essentially, using decimal numbers is a bad idea. It uses more
silicon area to achieve much the same result.

So you can write the same integer, but it won't produce the same
output frequency.

Obviously.

And if you knew your reference clock frequency that precisely.

Or, as is quite likely, other things are locked to that same
reference, and need to interoperate.

That's a problem of clock distribution - which is interesting in it's
own right, but not what's been being talked about here.

The big problem with the DDS idea is the DAC+filter. In order to
get rid of the jitter sidebands down to 1 ps, the analog stuff has
to be accurate and stable to about 1 ps * 2 pi *155.2 MHz ~= 0.1%.

Rubbish. The DAC is just producing a tolerable approximation to a
sine wave, and the imperfections should get largely get filtered out
before the DDS output gets into the phase detector.

Quit pontificating and do the math. It's as I said. Phase error due to
additive signals goes as the spur amplitude divided by the maximum phase
slope of the desired signal. 'Tain't rocket science.

Most of the
side-band products get filtered after the detector anyway, and any DC
that's left is a constant (and small) phase offset, not a frequency
offset (if you do it anything like right).

The bang-bang PLL is pretty good for the price.

It's a can of worms. Any noise on the rails can creep on and shift
the switching point. A product phase detector is a lot more
forgiving.

John has shipping products with 1-ps jitter. I have a digital delay box
of his that has 5 ps of jitter, which is about 35 dB better than the SRS
box I used to have. So rather than preening yourself, you might listen
and learn.


I'm not sure it wouldn't work fine at 80 kHz, if John doesn't need
the wide control bandwidth.

If he went out and bought a decent VXCO, which was an off-the-shelf
item 20 years ago, and ON-Semiconductor now seems to offer as an SMD
component, he could live with a really slow and heavily filtered
phase detector running at 80kHz, but either a DDS or a fractional-N
divider could be made to work at 10MHz and would give much faster
feedback.

John was asking for a smart idea, in order to save money.

I'm only going to build 8 of the boxes in question, so money isn't
really a big deal, except for the Joergian sporting aspects. I thought
the PLL math was interesting, and a discussion group does need stuff
to discuss. Talking about problems with other people helps me to
think, too.

I'm not an RF sort of guy - sine waves are BORING - and some people
here are, so it's interesting to get some fresh ideas.

Sure. Helps in keeping out of ruts. And sine waves are only boring if
you have a short attention span.

If you want to use a bang-bang loop with a single phase detector, and
avoid analogue precision (even filters), ISTM you're pretty much stuck
with 80 kHz, or the equivalent (e.g. synthesizing 1.5552 GHz and
dividing down). Any mixing or frequency-offset scheme is going to
require filtering.

One possibility is to use local feedback: run a quiet-but-perhaps drifty
offset PLL with a nice wide bandwidth to make your 155.52 MHz, and wrap
it in a bang-bang loop at 80 kHz to take out the drift, perhaps by
putting a varactor phase shifter in the 10 MHz going to the analogue loop.

Cheers

Phil Hobbs

It occurs to me that there's a lot of similarity between a noiseless
bang-bang PLL and a duty-cycle integrating ADC, and a lot of
similarity between a noisy bangbang and a delta-sigma ADC.

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[John Miles, KE5FX]

On Thursday, September 11, 2014 8:45:04 AM UTC-7, Bill Sloman wrote:

On Friday, 12 September 2014 00:19:42 UTC+10, John Larkin wrote:

On Wed, 10 Sep 2014 22:40:12 -0700, josephkk



joseph_barrett@sbcglobal.net> wrote:







On Wed, 10 Sep 2014 07:21:30 -0700, John Larkin



jlarkin@highlandtechnology.com> wrote:







On Wed, 10 Sep 2014 10:54:45 +0200, Gerhard Hoffmann



ghf@hoffmann-hochfrequenz.de> wrote:







Am 10.09.2014 um 01:54 schrieb John Larkin:







I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but



that sounds jitterey to me, and it looks like I can't hit the exact



frequency ratio anyhow.







Dividing EXACTLY with a DDS can be surprisingly hard, one could



find that one is always off by 2e-32 or 2e-48 or whatever



but one is never exactly on the spot, never really synchronous.











Right. One rounding bit out of 48, or even 64, would give me a slow



phase creep.















Once, there was a BCD coded DDS from Stanford IIRC that



could get it exact for easy-to-write decimal numbers.







Yeah, decimal might work.



Today one could put it into an FPGA. A BCD based adder

is easy. I have put a VHDL-only sine table on opencores.org

that should also be easy to modify.



That is interesting. We might look into a decimal DDS.



The DDS concept is an integer divide system, binary or BCD makes no

difference.



No, it's a fractional multiply concept, and some fractions can be

expressed exactly in some radixes but not in others.



Try expressing 1/5 as a binary fractional.



1/101 (binary).

This entire thread... wow... just, wow.

Look up variable-modulus DDSes. They are cool.

-- john, KE5FX

 

[Phil Hobbs]

On 09/11/2014 01:19 PM, Bill Sloman wrote:

On Friday, 12 September 2014 01:52:01 UTC+10, Phil Hobbs wrote:
On 09/11/2014 11:38 AM, Bill Sloman wrote:
On Friday, 12 September 2014 01:03:22 UTC+10, Phil Hobbs wrote:
On 09/11/2014 08:42 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

Rubbish. The DAC is just producing a tolerable approximation to a
sine wave, and the imperfections should get largely get filtered out
before the DDS output gets into the phase detector.

Quit pontificating and do the math. It's as I said. Phase error due to
additive signals goes as the spur amplitude divided by the maximum phase
slope of the desired signal. 'Tain't rocket science.

I suspect that you've done the math you usually do, which is for random noise at different frequencies.

In this situation, the harmonic content is pretty much deterministic, and the same from one cycle to the next. As I said, it can create a static phase shift, but no noise or drift. In the fractional-N at 10MHz system, successive cycles will have different phase shifts - within a 6.4nsec window - but that will repeat exactly every 12.5usec, and most of it will cancel out a lot more rapidly.

Wrong. Do the math. If the jitter were the same from cycle to cycle,
you wouldn't need a DDS register any wider than your DAC.


Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Kevin Aylward]

"Bill Sloman" wrote in message
news:eb4f48e3-5bd6-48e0-bc6c-8c3965698b29@googlegroups.com...

On Friday, 12 September 2014 01:52:01 UTC+10, Phil Hobbs wrote:

On 09/11/2014 11:38 AM, Bill Sloman wrote:
On Friday, 12 September 2014 01:03:22 UTC+10, Phil Hobbs wrote:
On 09/11/2014 08:42 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

Rubbish. The DAC is just producing a tolerable approximation to a
sine wave, and the imperfections should get largely get filtered out
before the DDS output gets into the phase detector.

Quit pontificating and do the math. It's as I said. Phase error due to
additive signals goes as the spur amplitude divided by the maximum phase
slope of the desired signal. 'Tain't rocket science.

I suspect that you've done the math you usually do, which is for random
noise at different frequencies.

In this situation, the harmonic content is pretty much deterministic, and
the same from one cycle to the next. As I said, it can create a static
phase shift, but no noise or >drift. In the fractional-N at 10MHz system,
successive cycles will have different phase shifts - within a 6.4nsec
window - but that will repeat exactly every 12.5usec, and >most of it will
cancel out a lot more rapidly.

I don't agree that, in general, that the noise profile of a fractional-n is
repetitive. A fractional-n will realistically, today, pretty much be a
multi-order delta-sigma configuration, probably... delta-sigma systems are
chaotic . i.e. pretty much random. Indeed, the task is to make it as random
as possible. I haven't followed this tread in detail so not sure what noise
to which is being referred to.

Somewhat interestingly, when John Wells of Marconi invented the delta-sigma
approach to synthesisers, it don't seem that the bigger picture of where
that approach sat was known. To wit, recognising the binomial expansion of
(1-z)^n to get the best approximating delay co-efficients and its relation
to ADC.

Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

 

On Thursday, September 11, 2014 12:29:36 PM UTC-4, John Larkin wrote:

On Thu, 11 Sep 2014 11:52:01 -0400, Phil Hobbs wrote:
On 09/11/2014 11:38 AM, Bill Sloman wrote:
On Friday, 12 September 2014 01:03:22 UTC+10, Phil Hobbs wrote:
On 09/11/2014 08:42 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

The DDS concept is an integer divide system, binary or BCD
makes n difference.

No, it's neither an integer divide system nor does BCD make no
difference.

A counter is an integer divide system.

The frequency resolution of a 48 bit DDS is f_clock/2**48 which
is anything but integer and you can get only multiples of the
resolution out. You may be very close to your intended
frequency but microHz away and that gives you a constant phase
creep.

But you can change the frequency by one resolution step from time
to time, and reverse the phase creep - if you need to. Half a
microHerz is rather more precise than John Larkin's 10MHz clock
is ever going to be. With an atomic clock system, you might want
to manipulate the phase creep, but not here.

With a BCD DDS your step size can be f_clock / 10e6 and that
that is an advantage if you need a frequency that can be
exactly written in a few decimal digits.

But you can write exactly the same number in rather fewer
hexadecimal digits, as long as you remember to include the
trailing zeros as digits.

Nope. With binary, the DDS output frequency is an integer multiple
of f_ref/2**N, whereas with BCD it's an integer multiple of
f_ref/10**M.

It's still the same number, even if it won't generate the same
frequency.

Essentially, using decimal numbers is a bad idea. It uses more
silicon area to achieve much the same result.

So you can write the same integer, but it won't produce the same
output frequency.

Obviously.

And if you knew your reference clock frequency that precisely.

Or, as is quite likely, other things are locked to that same
reference, and need to interoperate.

That's a problem of clock distribution - which is interesting in it's
own right, but not what's been being talked about here.

The big problem with the DDS idea is the DAC+filter. In order to
get rid of the jitter sidebands down to 1 ps, the analog stuff has
to be accurate and stable to about 1 ps * 2 pi *155.2 MHz ~= 0.1%.

Rubbish. The DAC is just producing a tolerable approximation to a
sine wave, and the imperfections should get largely get filtered out
before the DDS output gets into the phase detector.

Quit pontificating and do the math. It's as I said. Phase error due to
additive signals goes as the spur amplitude divided by the maximum phase
slope of the desired signal. 'Tain't rocket science.

Most of the
side-band products get filtered after the detector anyway, and any DC
that's left is a constant (and small) phase offset, not a frequency
offset (if you do it anything like right).

The bang-bang PLL is pretty good for the price.

It's a can of worms. Any noise on the rails can creep on and shift
the switching point. A product phase detector is a lot more
forgiving.

John has shipping products with 1-ps jitter. I have a digital delay box
of his that has 5 ps of jitter, which is about 35 dB better than the SRS
box I used to have. So rather than preening yourself, you might listen
and learn.

No Phil, you're mistaken. John's a mechanic / fiddler who only gets things right accidentally. NOOTTTTT!

I'm not sure it wouldn't work fine at 80 kHz, if John doesn't need
the wide control bandwidth.

If he went out and bought a decent VXCO, which was an off-the-shelf
item 20 years ago, and ON-Semiconductor now seems to offer as an SMD
component, he could live with a really slow and heavily filtered
phase detector running at 80kHz, but either a DDS or a fractional-N
divider could be made to work at 10MHz and would give much faster
feedback.

John was asking for a smart idea, in order to save money.

I'm only going to build 8 of the boxes in question, so money isn't
really a big deal, except for the Joergian sporting aspects. I thought
the PLL math was interesting, and a discussion group does need stuff
to discuss. Talking about problems with other people helps me to
think, too.

I'm not an RF sort of guy - sine waves are BORING - and some people
here are, so it's interesting to get some fresh ideas.

It occurs to me that there's a lot of similarity between a noiseless
bang-bang PLL and a duty-cycle integrating ADC, and a lot of
similarity between a noisy bangbang and a delta-sigma ADC.

I'm about to go for a jog, but how about some analog ideas?

e.g., if the PLL error signal is messy, add in a jitter-compensating signal.

e.g., do fractional division with an integer number of clocks plus a varying analog ramp delay. That would let you keep a much higher reference frequency.

Even a ramp with horrible resolution is way less jittery than alternating the divider modulii.

Cheers,
James Arthur