PLL tricks

[Bill Sloman]

On Friday, 12 September 2014 03:55:41 UTC+10, Phil Hobbs wrote:

On 09/11/2014 01:19 PM, Bill Sloman wrote:
On Friday, 12 September 2014 01:52:01 UTC+10, Phil Hobbs wrote:
On 09/11/2014 11:38 AM, Bill Sloman wrote:
On Friday, 12 September 2014 01:03:22 UTC+10, Phil Hobbs wrote:
On 09/11/2014 08:42 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

Rubbish. The DAC is just producing a tolerable approximation to a
sine wave, and the imperfections should get largely get filtered out
before the DDS output gets into the phase detector.

Quit pontificating and do the math. It's as I said. Phase error due to
additive signals goes as the spur amplitude divided by the maximum phase
slope of the desired signal. 'Tain't rocket science.

I suspect that you've done the math you usually do, which is for random noise at different frequencies.

In this situation, the harmonic content is pretty much deterministic, and the same from one cycle to the next. As I said, it can create a static phase shift, but no noise or drift. In the fractional-N at 10MHz system, successive cycles will have different phase shifts - within a 6.4nsec window - but that will repeat exactly every 12.5usec, and most of it will cancel out a lot more rapidly.

Wrong. Do the math. If the jitter were the same from cycle to cycle,
you wouldn't need a DDS register any wider than your DAC.

I didn't think that I was saying it was. I did say it was the same from one cycle to the next, but the cycles I had in mind were the 12.5usec over which the full cycle repeats itself. For the DDS creating 10MHz from 155.52MHz every two periods of the 10MHz look pretty similar, which means that any kind of decent low pass filtering won't have all that much crap to get rid of.

Your "0.1% precision" demand comes from *you* not doing the math.

--
Bill Sloman, Sydney

 

[Bill Sloman]

On Friday, 12 September 2014 05:20:05 UTC+10, Kevin Aylward wrote:

"Bill Sloman" wrote in message
news:eb4f48e3-5bd6-48e0-bc6c-8c3965698b29@googlegroups.com...
On Friday, 12 September 2014 01:52:01 UTC+10, Phil Hobbs wrote:
On 09/11/2014 11:38 AM, Bill Sloman wrote:
On Friday, 12 September 2014 01:03:22 UTC+10, Phil Hobbs wrote:
On 09/11/2014 08:42 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

<snip>

I don't agree that, in general, that the noise profile of a fractional-n is
repetitive. A fractional-n will realistically, today, pretty much be a
multi-order delta-sigma configuration, probably... delta-sigma systems are
chaotic . i.e. pretty much random. Indeed, the task is to make it as random
as possible. I haven't followed this thread in detail so not sure what noise
to which is being referred to.

The thread opened with John Larkin pointing out that his problem could be solved exactly by dividing both clocks down to 80kHz, so here the noise profile is going to be repetitive at 80kHz. A big chunk repeats at 5MHz, and my first cut at a solution suggest that most of the rest repeated at 1MHz.

--
Bill Sloman, Sydney

Somewhat interestingly, when John Wells of Marconi invented the delta-sigma

approach to synthesisers, it don't seem that the bigger picture of where

that approach sat was known. To wit, recognising the binomial expansion of

(1-z)^n to get the best approximating delay co-efficients and its relation

to ADC.



Kevin Aylward

www.kevinaylward.co.uk

www.anasoft.co.uk - SuperSpice

 

On Thursday, September 11, 2014 8:24:15 PM UTC-4, John Larkin wrote:

On Thu, 11 Sep 2014 17:00:06 -0700 (PDT), dagmargoo...@yahoo.com wrote:
On Thursday, September 11, 2014 12:29:36 PM UTC-4, John Larkin wrote:
On Thu, 11 Sep 2014 11:52:01 -0400, Phil Hobbs wrote:
On 09/11/2014 11:38 AM, Bill Sloman wrote:

It's a can of worms. Any noise on the rails can creep on and shift
the switching point. A product phase detector is a lot more
forgiving.

John has shipping products with 1-ps jitter. I have a digital delay box
of his that has 5 ps of jitter, which is about 35 dB better than the SRS
box I used to have. So rather than preening yourself, you might listen
and learn.

No Phil, you're mistaken. John's a mechanic / fiddler who only gets things right accidentally. NOOTTTTT!

There's nothing wrong with mechanics, and nothing wrong with fiddling
or accidental solutions.

I was kidding of course. The best designers I've known have always been great mechanical and otherwise-thinkers and tinkerers too.

Feynman made one of his breakthroughs imagining twirling pie plates. At a diner, IIRC.

Design is, fundamentally, fiddling, namely
exploring an enormous solution space and finding something that works
well. Brains can do that, somehow. Fiddling is an acquired skill.

Yes. And lots of fiddling at an early age helps.

> Equations seldom design stuff.

Yep. Equations usually describe stuff someone already did, help others duplicate, and sometimes refine it.

[...]

I'm only going to build 8 of the boxes in question, so money isn't
really a big deal, except for the Joergian sporting aspects. I thought
the PLL math was interesting, and a discussion group does need stuff
to discuss. Talking about problems with other people helps me to
think, too.

I'm not an RF sort of guy - sine waves are BORING - and some people
here are, so it's interesting to get some fresh ideas.

It occurs to me that there's a lot of similarity between a noiseless
bang-bang PLL and a duty-cycle integrating ADC, and a lot of
similarity between a noisy bangbang and a delta-sigma ADC.

I'm about to go for a jog, but how about some analog ideas?

e.g., if the PLL error signal is messy, add in a jitter-compensating signal.

e.g., do fractional division with an integer number of clocks plus a varying analog ramp delay. That would let you keep a much higher reference frequency.

Even a ramp with horrible resolution is way less jittery than alternating the divider modulii.

One similar textbook technique is to use a dual-modulus divider and,
off to the side, compute a DAC value as a jitter compensation. The DAC
analog output is summed into the phase detector analog output, to
compensate for the small phase jumps inherent in the dual-modulus
math.

Yes, that was my 2nd suggestion.

I think that a DDS thing might work that way too. If we use the MSB
(ie, rollover) of a phase accumulator as a scaled-down clock, it has a
jitter of one input clock p-p. But, at DDS accumulator overflow time,
we know the values of the lower-down bits of the phase accumulator,
and they could be used to compensate for the MSB jitter. Somehow.

Does that make sense?

It does. If you had access to the lower bits you could, in theory, phase-adjust the DDS output by adding a small DAC'd correction. I think that works. (I'm not sure of all the numbers and trade-offs without actually calculating.)

A DDS to generate a reference signal, then a separate generator to cancel the post-phase detector ripple might be clean circuitry-wise. A dual DDS might provide both.

But it still won't allow me to make exactly 10 MHz from a binary DDS
clocked at 155.52.

But the goal's the opposite, to lock the 155.52e6 to the 10e7 reference, right?

I thought about it jogging. The fractional division using analog ramps would take two ramps--a pre- and post-delay--and some logic.

It's easier and less jittery (I think) with digital equivalents.

To wit, divide 155.52e6 by 243 to get 640KHz.
10 MHz divided by 15 5/8 = 640KHz.
So, if you can generate 1/8ths of 10MHz, you're golden.

I mulled a bunch of schemes to generate (n/8)-length pulses for n=0..7, but I think the lowest jitter is to generate 80MHz with a good rock, phase-locked to the 10MHz reference. Then divide by 155 and Bob's yer uncle.

Good VHF rocks are awesome, in my admittedly dim recollection of some old RF Design articles by Matthys(sp?), and 80MHz is well in reasonable range.

The benefit is an 8x increase in reference frequency, and reference pulses that are exact to within the jitter of a very nice rock.

If the 80MHz drifts in phase relative to the 10MHz, the 155.52e6 output drifts too, possibly a problem...

Cheers,
James Arthur

 

[Bill Sloman]

On Friday, 12 September 2014 10:24:15 UTC+10, John Larkin wrote:

On Thu, 11 Sep 2014 17:00:06 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:
On Thursday, September 11, 2014 12:29:36 PM UTC-4, John Larkin wrote:
On Thu, 11 Sep 2014 11:52:01 -0400, Phil Hobbs wrote:
On 09/11/2014 11:38 AM, Bill Sloman wrote:
On Friday, 12 September 2014 01:03:22 UTC+10, Phil Hobbs wrote:
On 09/11/2014 08:42 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

<snip>

No Phil, you're mistaken. John's a mechanic / fiddler who only gets things right accidentally. NOOTTTTT!

There's nothing wrong with mechanics, and nothing wrong with fiddling
or accidental solutions. Design is, fundamentally, fiddling, namely
exploring an enormous solution space and finding something that works
well. Brains can do that, somehow. Fiddling is an acquired skill.

Equations seldom design stuff.

It helps if the brain is well stocked with design solutions.

John's told him that a DDS output would be "jittery". If it had been better stocked, it would have told him that DDS would be pushing out a stair-case approximation to 10MHz sine wave, with the steps on the staircase reflecting 155.52MHz content (plus odd harmonics of 155.52 MHz)which would be easy to low pass filter down to negligible proportions. As the undesired content is mostly at precisely 155.52MHz, a notch filter wouldn't have been out of place.

I'm not sure it wouldn't work fine at 80 kHz, if John doesn't need
the wide control bandwidth.

If he went out and bought a decent VXCO, which was an off-the-shelf
item 20 years ago, and ON-Semiconductor now seems to offer as an SMD
component, he could live with a really slow and heavily filtered
phase detector running at 80kHz, but either a DDS or a fractional-N
divider could be made to work at 10MHz and would give much faster
feedback.



John was asking for a smart idea, in order to save money.

I'm only going to build 8 of the boxes in question, so money isn't
really a big deal, except for the Joergian sporting aspects. I thought
the PLL math was interesting, and a discussion group does need stuff
to discuss. Talking about problems with other people helps me to
think, too.

I'm not an RF sort of guy - sine waves are BORING - and some people
here are, so it's interesting to get some fresh ideas.

It occurs to me that there's a lot of similarity between a noiseless
bang-bang PLL and a duty-cycle integrating ADC, and a lot of
similarity between a noisy bangbang and a delta-sigma ADC.

I'm about to go for a jog, but how about some analog ideas?

e.g., if the PLL error signal is messy, add in a jitter-compensating signal.
e.g., do fractional division with an integer number of clocks plus a varying analog ramp delay. That would let you keep a much higher reference frequency.

Even a ramp with horrible resolution is way less jittery than alternating the divider modulii.

That's in the same ball-park as using a DDS to go from 155.52MHz to a synthesised 10MHz.

The difference between the staircase the DDS gives John and the sine wave he want are a series of short (6.4nsec) ramps.

You've got to low pass filter the synthesised 10MHz to reduce the 155.52MHz content (and the additional odd harmonic content). Four poles would pull that down by 90dB, and it's all a whole lot less messy than a ramp, though DDS chips are expensive.

One similar textbook technique is to use a dual-modulus divider and,
off to the side, compute a DAC value as a jitter compensation.

better would be to use a

http://www.onsemi.com/pub_link/Collateral/MC10EP195-D.PDF

to generate a compensating programmable delay in the range 0 to 6.43nsec - actually 2.5 to 8.93nsec.

It only offers 10psec resolution and the accuracy is rubbish, so the phase-detector output will still have some high frequency noise, but you are only interested in the DC content of that output, and any PLL feedback to a VCO has lots of low-pass filtering.

It's the kind of thing that you could do with a really dumb 1944-entry look-up table. I couldn't buy any ECL RAM from anywhere last time I tried, but the look-up table is only being looked up at 10MHz, and the MC100EP195 data inputs can be driven from any one of " ECL, CMOS, or TTL".

The are programmable logic devices with ECL-compatible outputs - ten might be a drag, but getting the ten bits out serially once every 100nsec wouldn't be a problem. A look-up table is the dumbest possible way of doing the job - an accumulator structure would make much more sense.

The DAC analog output is summed into the phase detector analog output, to
compensate for the small phase jumps inherent in the dual-modulus
math.

Why not stay in the digital domain? It's less messy, and less demanding EMC-wise.

<snip>

But it still won't allow me to make exactly 10 MHz from a binary DDS
clocked at 155.52.

Sure it will. But the "exactly" 10MHz generated has 155.5.2MHz (and odd harmonics of 155.52MHz) components, which you have to low pass filter out. Since 155.52MHz is quite a bit higher than 10MHz a four or six pole low pass filter could do a pretty thorough job.

The MC100EP195 would let you get a lot closer to 10MHz entirely in the digital domain, but with not less than 10psec of jitter. Since there's up to 1.5nsec of temperature-dependent drift (from -40C to 85C) on the longer delays, you'd probably have closer to 1nsec of jitter on the synthesised 10MHz, which would show up as noise on the raw phase detector output.

There wouldn't be any frequency content in that noise below 80kHz, but you can low-pass filter the phase-detector output pretty fiercely before you feed it back to the voltage-controlled 155.52MHz oscillator, so it shouldn't be a problem.

--
Bill Sloman, Sydney

 

[John Larkin]

On Thu, 11 Sep 2014 17:00:06 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

On Thursday, September 11, 2014 12:29:36 PM UTC-4, John Larkin wrote:
On Thu, 11 Sep 2014 11:52:01 -0400, Phil Hobbs wrote:
On 09/11/2014 11:38 AM, Bill Sloman wrote:
On Friday, 12 September 2014 01:03:22 UTC+10, Phil Hobbs wrote:
On 09/11/2014 08:42 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

The DDS concept is an integer divide system, binary or BCD
makes n difference.

No, it's neither an integer divide system nor does BCD make no
difference.

A counter is an integer divide system.

The frequency resolution of a 48 bit DDS is f_clock/2**48 which
is anything but integer and you can get only multiples of the
resolution out. You may be very close to your intended
frequency but microHz away and that gives you a constant phase
creep.

But you can change the frequency by one resolution step from time
to time, and reverse the phase creep - if you need to. Half a
microHerz is rather more precise than John Larkin's 10MHz clock
is ever going to be. With an atomic clock system, you might want
to manipulate the phase creep, but not here.

With a BCD DDS your step size can be f_clock / 10e6 and that
that is an advantage if you need a frequency that can be
exactly written in a few decimal digits.

But you can write exactly the same number in rather fewer
hexadecimal digits, as long as you remember to include the
trailing zeros as digits.

Nope. With binary, the DDS output frequency is an integer multiple
of f_ref/2**N, whereas with BCD it's an integer multiple of
f_ref/10**M.

It's still the same number, even if it won't generate the same
frequency.

Essentially, using decimal numbers is a bad idea. It uses more
silicon area to achieve much the same result.

So you can write the same integer, but it won't produce the same
output frequency.

Obviously.

And if you knew your reference clock frequency that precisely.

Or, as is quite likely, other things are locked to that same
reference, and need to interoperate.

That's a problem of clock distribution - which is interesting in it's
own right, but not what's been being talked about here.

The big problem with the DDS idea is the DAC+filter. In order to
get rid of the jitter sidebands down to 1 ps, the analog stuff has
to be accurate and stable to about 1 ps * 2 pi *155.2 MHz ~= 0.1%.

Rubbish. The DAC is just producing a tolerable approximation to a
sine wave, and the imperfections should get largely get filtered out
before the DDS output gets into the phase detector.

Quit pontificating and do the math. It's as I said. Phase error due to
additive signals goes as the spur amplitude divided by the maximum phase
slope of the desired signal. 'Tain't rocket science.

Most of the
side-band products get filtered after the detector anyway, and any DC
that's left is a constant (and small) phase offset, not a frequency
offset (if you do it anything like right).

The bang-bang PLL is pretty good for the price.

It's a can of worms. Any noise on the rails can creep on and shift
the switching point. A product phase detector is a lot more
forgiving.

John has shipping products with 1-ps jitter. I have a digital delay box
of his that has 5 ps of jitter, which is about 35 dB better than the SRS
box I used to have. So rather than preening yourself, you might listen
and learn.

No Phil, you're mistaken. John's a mechanic / fiddler who only gets things right accidentally. NOOTTTTT!

There's nothing wrong with mechanics, and nothing wrong with fiddling
or accidental solutions. Design is, fundamentally, fiddling, namely
exploring an enormous solution space and finding something that works
well. Brains can do that, somehow. Fiddling is an acquired skill.

Equations seldom design stuff.

I'm not sure it wouldn't work fine at 80 kHz, if John doesn't need
the wide control bandwidth.

If he went out and bought a decent VXCO, which was an off-the-shelf
item 20 years ago, and ON-Semiconductor now seems to offer as an SMD
component, he could live with a really slow and heavily filtered
phase detector running at 80kHz, but either a DDS or a fractional-N
divider could be made to work at 10MHz and would give much faster
feedback.

John was asking for a smart idea, in order to save money.

I'm only going to build 8 of the boxes in question, so money isn't
really a big deal, except for the Joergian sporting aspects. I thought
the PLL math was interesting, and a discussion group does need stuff
to discuss. Talking about problems with other people helps me to
think, too.

I'm not an RF sort of guy - sine waves are BORING - and some people
here are, so it's interesting to get some fresh ideas.

It occurs to me that there's a lot of similarity between a noiseless
bang-bang PLL and a duty-cycle integrating ADC, and a lot of
similarity between a noisy bangbang and a delta-sigma ADC.

I'm about to go for a jog, but how about some analog ideas?

e.g., if the PLL error signal is messy, add in a jitter-compensating signal.

e.g., do fractional division with an integer number of clocks plus a varying analog ramp delay. That would let you keep a much higher reference frequency.

Even a ramp with horrible resolution is way less jittery than alternating the divider modulii.

One similar textbook technique is to use a dual-modulus divider and,
off to the side, compute a DAC value as a jitter compensation. The DAC
analog output is summed into the phase detector analog output, to
compensate for the small phase jumps inherent in the dual-modulus
math.

I think that a DDS thing might work that way too. If we use the MSB
(ie, rollover) of a phase accumulator as a scaled-down clock, it has a
jitter of one input clock p-p. But, at DDS accumulator overflow time,
we know the values of the lower-down bits of the phase accumulator,
and they could be used to compensate for the MSB jitter. Somehow.

Does that make sense?

But it still won't allow me to make exactly 10 MHz from a binary DDS
clocked at 155.52.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Phil Hobbs]

On 9/11/2014 8:24 PM, John Larkin wrote:

On Thu, 11 Sep 2014 17:00:06 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

On Thursday, September 11, 2014 12:29:36 PM UTC-4, John Larkin wrote:
On Thu, 11 Sep 2014 11:52:01 -0400, Phil Hobbs wrote:
On 09/11/2014 11:38 AM, Bill Sloman wrote:
On Friday, 12 September 2014 01:03:22 UTC+10, Phil Hobbs wrote:
On 09/11/2014 08:42 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

The DDS concept is an integer divide system, binary or BCD
makes n difference.

No, it's neither an integer divide system nor does BCD make no
difference.

A counter is an integer divide system.

The frequency resolution of a 48 bit DDS is f_clock/2**48 which
is anything but integer and you can get only multiples of the
resolution out. You may be very close to your intended
frequency but microHz away and that gives you a constant phase
creep.

But you can change the frequency by one resolution step from time
to time, and reverse the phase creep - if you need to. Half a
microHerz is rather more precise than John Larkin's 10MHz clock
is ever going to be. With an atomic clock system, you might want
to manipulate the phase creep, but not here.

With a BCD DDS your step size can be f_clock / 10e6 and that
that is an advantage if you need a frequency that can be
exactly written in a few decimal digits.

But you can write exactly the same number in rather fewer
hexadecimal digits, as long as you remember to include the
trailing zeros as digits.

Nope. With binary, the DDS output frequency is an integer multiple
of f_ref/2**N, whereas with BCD it's an integer multiple of
f_ref/10**M.

It's still the same number, even if it won't generate the same
frequency.

Essentially, using decimal numbers is a bad idea. It uses more
silicon area to achieve much the same result.

So you can write the same integer, but it won't produce the same
output frequency.

Obviously.

And if you knew your reference clock frequency that precisely.

Or, as is quite likely, other things are locked to that same
reference, and need to interoperate.

That's a problem of clock distribution - which is interesting in it's
own right, but not what's been being talked about here.

The big problem with the DDS idea is the DAC+filter. In order to
get rid of the jitter sidebands down to 1 ps, the analog stuff has
to be accurate and stable to about 1 ps * 2 pi *155.2 MHz ~= 0.1%.

Rubbish. The DAC is just producing a tolerable approximation to a
sine wave, and the imperfections should get largely get filtered out
before the DDS output gets into the phase detector.

Quit pontificating and do the math. It's as I said. Phase error due to
additive signals goes as the spur amplitude divided by the maximum phase
slope of the desired signal. 'Tain't rocket science.

Most of the
side-band products get filtered after the detector anyway, and any DC
that's left is a constant (and small) phase offset, not a frequency
offset (if you do it anything like right).

The bang-bang PLL is pretty good for the price.

It's a can of worms. Any noise on the rails can creep on and shift
the switching point. A product phase detector is a lot more
forgiving.

John has shipping products with 1-ps jitter. I have a digital delay box
of his that has 5 ps of jitter, which is about 35 dB better than the SRS
box I used to have. So rather than preening yourself, you might listen
and learn.

No Phil, you're mistaken. John's a mechanic / fiddler who only gets things right accidentally. NOOTTTTT!


There's nothing wrong with mechanics, and nothing wrong with fiddling
or accidental solutions. Design is, fundamentally, fiddling, namely
exploring an enormous solution space and finding something that works
well. Brains can do that, somehow. Fiddling is an acquired skill.

Equations seldom design stuff.




I'm not sure it wouldn't work fine at 80 kHz, if John doesn't need
the wide control bandwidth.

If he went out and bought a decent VXCO, which was an off-the-shelf
item 20 years ago, and ON-Semiconductor now seems to offer as an SMD
component, he could live with a really slow and heavily filtered
phase detector running at 80kHz, but either a DDS or a fractional-N
divider could be made to work at 10MHz and would give much faster
feedback.

John was asking for a smart idea, in order to save money.

I'm only going to build 8 of the boxes in question, so money isn't
really a big deal, except for the Joergian sporting aspects. I thought
the PLL math was interesting, and a discussion group does need stuff
to discuss. Talking about problems with other people helps me to
think, too.

I'm not an RF sort of guy - sine waves are BORING - and some people
here are, so it's interesting to get some fresh ideas.

It occurs to me that there's a lot of similarity between a noiseless
bang-bang PLL and a duty-cycle integrating ADC, and a lot of
similarity between a noisy bangbang and a delta-sigma ADC.

I'm about to go for a jog, but how about some analog ideas?

e.g., if the PLL error signal is messy, add in a jitter-compensating signal.

e.g., do fractional division with an integer number of clocks plus a varying analog ramp delay. That would let you keep a much higher reference frequency.

Even a ramp with horrible resolution is way less jittery than alternating the divider modulii.


One similar textbook technique is to use a dual-modulus divider and,
off to the side, compute a DAC value as a jitter compensation. The DAC
analog output is summed into the phase detector analog output, to
compensate for the small phase jumps inherent in the dual-modulus
math.

I think that a DDS thing might work that way too. If we use the MSB
(ie, rollover) of a phase accumulator as a scaled-down clock, it has a
jitter of one input clock p-p. But, at DDS accumulator overflow time,
we know the values of the lower-down bits of the phase accumulator,
and they could be used to compensate for the MSB jitter. Somehow.

Does that make sense?

Sure. You can compute what the filtered DAC output ought to produce,
and use that. With your DDG chops, you could do that standing on your head.

I still think the local feedback approach (offset analogue loop
disciplined by 80 kHz bang-bang loop to control drift) would be a cool
thing to build.

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Mike Perkins]

On 11/09/2014 11:20, Mike Perkins wrote:

On 10/09/2014 00:54, John Larkin wrote:


If I hypothetically had a 10 MHz reference and wanted to lock a
155.52 MHz VCXO to it, the obvious way would be to divide both down
to 80 KHz (the GCD) and drive a phase detector back into the VCXO.
But that's a pretty low frequency to run the PD at; to get
picosecond stability, an ordinary analog phase detector would need
better than 1 PPM analog accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work,
but 80K is still pretty low.

There must be tricks to run the phase detector at a higher
frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz,
but that sounds jitterey to me, and it looks like I can't hit the
exact frequency ratio anyhow.

An idea came to me that may or may not be of interest.

You can get multi-bit DACs at several hundred MSPS and higher but I
presume there is an upper limit to your project inventory.

The use of a DDS has been mentioned and of course most DDS's would
use a binary 32 bit counter.

Have you considered using a non-binary count, one that is a multiple
of 125? Your lookup phase table would also need to be modified and 3
* 2>>n would need to be subtracted when the counter wraps round.

Then use a phase comparator at 10MHz with very simple filtering to
drive your VXCO.

You could use a multiple of 155.52MHz to drive the DDS though most
FPGA would only play ball at fundamental. If a FPGA has a DDR
interface is used then certainly it is possible to double up on
samples even with a slow FPGA and indeed is something I have done.

This would maintain a perfect phase relationship between the 10MHz
and the 155.52MHz.

Perhaps I haven't explained myself very well.

What we require is to equate 155.52MHz with 10MHz, such that after
15.552 clock cycles we can produce exactly a single cycle of a sine wave.

Lets suppose we have a sine table that is comprises of 1,944 points with
an amplitude of say 255 for use with an 8 bit DAC.

V = 255 * sin( 360 * n / 1,944)

We can load this into block memory of a FPGA.

For every clock at 155.52MHz we advance the phase by adding 125 to the
accumulator that counts modulo 1,944.

After 15.52 clocks (or 100ns) we would on average have moved along the
whole of the phase table and so output a complete cycle of sine-wave.

The DAC would be driven by the amplitude corresponding to the
accumulator/position in the phase table. We can filter to remove higher
harmonics to leave a healthy 10MHz sine wave.

We can compare with this single cycle (with a 100ns period) with the
cycle we have from the reference 10MHz using a phase comparator.

We have all come across DDS's that use a binary count, but there is no
reason why the count can't be modulo an alternative number. Of course
the phase table length must suit.


--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk

 

[rickman]

On 9/11/2014 10:31 PM, Mike Perkins wrote:

On 11/09/2014 11:20, Mike Perkins wrote:
On 10/09/2014 00:54, John Larkin wrote:


If I hypothetically had a 10 MHz reference and wanted to lock a
155.52 MHz VCXO to it, the obvious way would be to divide both down
to 80 KHz (the GCD) and drive a phase detector back into the VCXO.
But that's a pretty low frequency to run the PD at; to get
picosecond stability, an ordinary analog phase detector would need
better than 1 PPM analog accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work,
but 80K is still pretty low.

There must be tricks to run the phase detector at a higher
frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz,
but that sounds jitterey to me, and it looks like I can't hit the
exact frequency ratio anyhow.

An idea came to me that may or may not be of interest.

You can get multi-bit DACs at several hundred MSPS and higher but I
presume there is an upper limit to your project inventory.

The use of a DDS has been mentioned and of course most DDS's would
use a binary 32 bit counter.

Have you considered using a non-binary count, one that is a multiple
of 125? Your lookup phase table would also need to be modified and 3
* 2>>n would need to be subtracted when the counter wraps round.

Then use a phase comparator at 10MHz with very simple filtering to
drive your VXCO.

You could use a multiple of 155.52MHz to drive the DDS though most
FPGA would only play ball at fundamental. If a FPGA has a DDR
interface is used then certainly it is possible to double up on
samples even with a slow FPGA and indeed is something I have done.

I'm not sure what "though most FPGA would only play ball at fundamental"
means. 155 MHz is not anywhere near the upper speed limit for signals
in a modern FPGA including I/O. Signals feeding a DAC at these speeds
are often LVDS anyway and can easily handle two or three times this rate.

Once your design approaches the upper speed range of the FPGA
internally, it is quite easy to improve performance by doing multiple
calculations in parallel such as the DDR interface you mention would
typically use.

This would maintain a perfect phase relationship between the 10MHz
and the 155.52MHz.

Perhaps I haven't explained myself very well.

What we require is to equate 155.52MHz with 10MHz, such that after
15.552 clock cycles we can produce exactly a single cycle of a sine wave.

Lets suppose we have a sine table that is comprises of 1,944 points with
an amplitude of say 255 for use with an 8 bit DAC.

V = 255 * sin( 360 * n / 1,944)

We can load this into block memory of a FPGA.

For every clock at 155.52MHz we advance the phase by adding 125 to the
accumulator that counts modulo 1,944.

Since this is a fixed rate design which does not need programmability of
the step size, it would be simpler to use an incrementer (or
decrementer) which is loaded with a non-zero start count and is reloaded
on reaching zero. The stored data in the table can be permuted to
account for this.

The result would be a faster circuit and a simpler circuit.

Another optimization is to separate the upper two bits of the counter to
be a divide by four and the lower bits a counter with 486 states. The
lower counter creates a ramp and the upper counter bits are used to
invert the lower counter as well as the sign bit of the data from the
table giving more resolution without using a larger table.

After 15.52 clocks (or 100ns) we would on average have moved along the
whole of the phase table and so output a complete cycle of sine-wave.

The DAC would be driven by the amplitude corresponding to the
accumulator/position in the phase table. We can filter to remove higher
harmonics to leave a healthy 10MHz sine wave.

We can compare with this single cycle (with a 100ns period) with the
cycle we have from the reference 10MHz using a phase comparator.

We have all come across DDS's that use a binary count, but there is no
reason why the count can't be modulo an alternative number. Of course
the phase table length must suit.

In fact non-binary DDS circuits are not at all uncommon. My test
fixture uses one to generate the sine wave while testing our production
boards. It tests a 24 bit CODEC so I wanted to get as much resolution
as I could and the FPGA is rather small with very limited block RAM.

--

Rick

 

[josephkk]

On Thu, 11 Sep 2014 11:03:22 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 09/11/2014 08:42 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

The DDS concept is an integer divide system, binary or BCD makes
n difference.

No, it's neither an integer divide system nor does BCD make no
difference.

A counter is an integer divide system.

The frequency resolution of a 48 bit DDS is f_clock/2**48 which is
anything but integer and you can get only multiples of the
resolution out. You may be very close to your intended frequency
but microHz away and that gives you a constant phase creep.

But you can change the frequency by one resolution step from time to
time, and reverse the phase creep - if you need to. Half a microHerz
is rather more precise than John Larkin's 10MHz clock is ever going
to be. With an atomic clock system, you might want to manipulate the
phase creep, but not here.

With a BCD DDS your step size can be f_clock / 10e6 and that that
is an advantage if you need a frequency that can be exactly written
in a few decimal digits.

But you can write exactly the same number in rather fewer hexadecimal
digits, as long as you remember to include the trailing zeros as
digits.

Nope. With binary, the DDS output frequency is an integer multiple of
f_ref/2**N, whereas with BCD it's an integer multiple of f_ref/10**M.
So you can write the same integer, but it won't produce the same output
frequency.

And in either case the phase step per clock step is an integer. If the
quanta of frequency/phase step is the same for 1 LSB the frequencies will
be the same. That is what i was talking about.
You can keep changing that integer a little bit and introduce a new phase
noise at a much higher frequency than the reference phase clock phase
noise. Maybe some noise shaping can be done to bury the true reference
jitter in another phase noise that gets removed. If Phill H. did the math
for it, i might not be able to follow it.

And if you knew your reference clock frequency that precisely.

Or, as is quite likely, other things are locked to that same reference,
and need to interoperate.

The big problem with the DDS idea is the DAC+filter. In order to get
rid of the jitter sidebands down to 1 ps, the analog stuff has to be
accurate and stable to about

1 ps * 2 pi *155.2 MHz ~= 0.1%.

The bang-bang PLL is pretty good for the price.

I'm not sure it wouldn't work fine at 80 kHz, if John doesn't need the
wide control bandwidth.

In a frequency multiplier, the RMS _phase_noise_ goes up by a factor of
N, but that's because the period gets shorter and the _jitter_ stays the
same (provided you get rid of the jitter of the dividers).

So John, how about that 80 kHz bang-bang thing with a picosecond ECL
D-flop following each divider? Your loop bandwidth will be smaller, but
the jitter should be fine.

Cheers

Phil Hobbs

 

[josephkk]

On Thu, 11 Sep 2014 19:59:16 -0700 (PDT), dagmargoodboat@yahoo.com wrote:

I think that a DDS thing might work that way too. If we use the MSB
(ie, rollover) of a phase accumulator as a scaled-down clock, it has a
jitter of one input clock p-p. But, at DDS accumulator overflow time,
we know the values of the lower-down bits of the phase accumulator,
and they could be used to compensate for the MSB jitter. Somehow.

Does that make sense?

It does. If you had access to the lower bits you could, in theory, phase-adjust the DDS output by adding a small DAC'd correction. I think that works. (I'm not sure of all the numbers and trade-offs without actually calculating.)

A DDS to generate a reference signal, then a separate generator to cancel the post-phase detector ripple might be clean circuitry-wise. A dual DDS might provide both.

I really like the possibilities in a dual DDS system. DDS synth 80 kHz or
800 kHz for more prelock bandwidth. (probably not needed or wanted) It
looks real straight forward and clean with good opportunities to minimize
phase noise.

?-)

 

On Friday, September 12, 2014 12:14:57 AM UTC-4, Bill Sloman wrote:

On Friday, 12 September 2014 10:24:15 UTC+10, John Larkin wrote:
On Thu, 11 Sep 2014 17:00:06 -0700 (PDT), dagmargoo...@yahoo.com wrote:
On Thursday, September 11, 2014 12:29:36 PM UTC-4, John Larkin wrote:

snip

There's nothing wrong with mechanics, and nothing wrong with fiddling
or accidental solutions. Design is, fundamentally, fiddling, namely
exploring an enormous solution space and finding something that works
well. Brains can do that, somehow. Fiddling is an acquired skill.

Equations seldom design stuff.

It helps if the brain is well stocked with design solutions.

John's told him that a DDS output would be "jittery".

It is. The DDS outputs a quantized waveform that can be pretty rough. The output is not an exact integer multiple of the DDS' clock, which means the DDS cycles through its DAC codes (as opposed to repeatedly using the same set over and over), creating a much-lower error frequency and phase error waveform related to the DAC's imperfections.

The DAC might be very good to where its inaccuracies are acceptable. We haven't examined that yet.

> If it had been better stocked, it would have told him that DDS would be pushing out a stair-case approximation to 10MHz sine wave, with the steps on the staircase reflecting 155.52MHz content (plus odd harmonics of 155.52 MHz

The 10MHz is the master reference; we're trying to generate 155.52e6 from it.

I'm talking about using the DDS to synthesize a PLL reference signal from the 10MHz standard, not using the DDS to output 155.52MHz.

> which would be easy to low pass filter down to negligible proportions.

John asked to synthesize 155.52 from 10MHz originally but did comment later about doing the reverse, which made room for confusion.

If the DDS is synthesizing 10MHz from a 155.52MHz reference, the DDS is outputting a 15.52 step 10MHz "sinewave." 15.52 steps is a pretty rough waveform.

[...]

e.g., if the PLL error signal is messy, add in a jitter-compensating signal.
e.g., do fractional division with an integer number of clocks plus a varying analog ramp delay. That would let you keep a much higher reference frequency.

Even a ramp with horrible resolution is way less jittery than alternating the divider modulii.

That's in the same ball-park as using a DDS to go from 155.52MHz to a synthesised 10MHz.

We're solving different problems.

I'm talking about synthesizing a low-jitter reference frequency from the 10MHz master, at a higher-than-GCD frequency (640KHz instead of 80KHz in this example).
.------------------------------.
.------. | ___ ___ |
| ref. | | / \ .---. / \ |
10 MHz >---|synth.|-----|->| X |-->|LPF|-->| ~ |-+-|-> 155.52MHz
'------' 640 | \___/ '---' \___/ | |
KHz | ^ VCXO | |
| '----------------------' |
'------------------------------'

Raising the reference by "n" means we can push the VCXO back towards correct phase n-times more frequently, lowering its phase wander/jitter w.r.t. the 10MHz master reference.

Before jogging, I was suggesting an *exact* non-integer divider with consistent (if imperfect) intermediate timing edges could be produced using
- integer numbers of 10MHz clock-cycles,
- stretched to the desired pulsewidth with analog digital delay generators..

The edge-timing imperfections could be small, and would be attenuated by the loop LPF.

After jogging I suggested as simpler: locking an 80MHz rock to the 10MHz master, then digitally dividing by 125, yielding a solid 640KHz reference for the 155.52MHz loop.

.---------------------------------.
| .---. .---. .----. .----. |
10MHz >---| x |-->|LPF|-->|VCXO|-+-|/125|---> 640KHz
| '---' '---' '----' | '----' |
| ^ 80 MHz | |
| '--------------------' |
'---------------------------------'

The reference edges are then perfectly-timed (i.e., not quantized or approximated), and stable as the (excellent) 80MHz rock.

All of that's old-school, meant to be solid and simple. '57 Chevy.

Today, a DDS PLL-reference generator might be simpler. Clocked at a non-integer multiple of the output frequency, say, 250MHz, a DDS could produce a stair-stepped 960KHz (=155.52e6/162) approximation to a sinewave (for the 155.52MHz PLL) reference, with ~260 steps in it.

There'd be a lot of easily-filtered 250MHz in the output, and a not-so-easily-filtered DAC-error beat frequency component that might be small enough not to matter.

Cheers,
James Arthur

 

[Bill Sloman]

On Friday, 12 September 2014 23:37:43 UTC+10, dagmarg...@yahoo.com wrote:

On Friday, September 12, 2014 12:14:57 AM UTC-4, Bill Sloman wrote:
On Friday, 12 September 2014 10:24:15 UTC+10, John Larkin wrote
On Thu, 11 Sep 2014 17:00:06 -0700 (PDT), dagmargoo...@yahoo.com wrote:
On Thursday, September 11, 2014 12:29:36 PM UTC-4, John Larkin wrote:

snip

There's nothing wrong with mechanics, and nothing wrong with fiddling
or accidental solutions. Design is, fundamentally, fiddling, namely
exploring an enormous solution space and finding something that works
well. Brains can do that, somehow. Fiddling is an acquired skill.

Equations seldom design stuff.

It helps if the brain is well stocked with design solutions.

John's told him that a DDS output would be "jittery".

It is. The DDS outputs a quantized waveform that can be pretty rough.

Technically speaking, it isn't "jittering". The artifacts are deterministic, rather than random.

> The output is not an exact integer multiple of the DDS' clock, which means the DDS cycles through its DAC codes (as opposed to repeatedly using the same set over and over), creating a much-lower error frequency and phase error waveform related to the DAC's imperfections.

Considered as an error signal on the perfect sine wave desired, it's a series of ramps which can be low-pass filtered out. 15.52 of them per cycle is actually fairly high frequency noise, and a couple of poles of low pass-filtering would clean it up considerably.

It won't create any kind of frequency error. I can imagine that there might be a small residual amplitude error that could translate into a periodic phase shift error which could repeat at 80kHz, which could be problem if you used an edge-based phase detector.

With a product-based phase detector, this would average out a lot faster.

The DAC might be very good to where its inaccuracies are acceptable. We haven't examined that yet.

If his brain had been better stocked, it would have told him that DDS would be pushing out a stair-case approximation to 10MHz sine wave, with the steps on the staircase reflecting 155.52MHz content (plus odd harmonics of 155.52 MHz which would be easy to low pass filter down to negligible proportions).

The 10MHz is the master reference; we're trying to generate 155.52e6 from it.

Not exactly. You are trying to lock a 155.52MHz output to a 10MHz reference..

Trying to generate 155.52MHz from it produces images of frequency multipliers, which won't work, since 155.52MHz isn't a harmonic of 10MHz.

I'm talking about using the DDS to synthesize a PLL reference signal from the 10MHz standard, not using the DDS to output 155.52MHz.

The only way you can do that is by buying a DDS with a built-in VCO which can be locked to an external reference.

http://www.analog.com/static/imported-files/data_sheets/AD9915.pdf

offers a 2.4 to 2.5GHz VCO which you could set at precisely 2.44GHz by choosing a 244 divide ratio (anything even from 20 to 510 seems to be on offer) and let it lock the divided output to the 10MHz reference.

You can then program any output frequency you want - page 17/18 of the data sheet tells you how - and with the AD9915 you really can get any rational number ratio you want.

Sadly, the AD9915 is expensive - $143.10 each for 5 to 9 from Newark - and Newark don't have any in stock, though there seem to be three in the UK workshop.

> John asked to synthesize 155.52 from 10MHz originally but did comment later about doing the reverse, which made room for confusion.

It's quite a bit cheaper.

> If the DDS is synthesizing 10MHz from a 155.52MHz reference, the DDS is outputting a 15.52 step 10MHz "sinewave." 15.52 steps is a pretty rough waveform.

But a low pass filter would clean it up a lot.

e.g., if the PLL error signal is messy, add in a jitter-compensating signal.

e.g., do fractional division with an integer number of clocks plus a varying analog ramp delay. That would let you keep a much higher reference frequency.

Even a ramp with horrible resolution is way less jittery than alternating the divider modulii.

That's in the same ball-park as using a DDS to go from 155.52MHz to a synthesised 10MHz.

We're solving different problems.

Depends how high you get above the playing field. John wants a 155.52MHz clock with at least the sort of stability you can get from a good quality 10MHz quartz crystal reference oscillator. There are quite a few ways to get from A to B.

http://www.freqelec.com/pdf/rfs_12pg.pdf

offers even better frequency stability and - with option 008 "1 Hz to 10 MHz sq. wave, TTL Comp., 5 MHz to 20 MHz sine wave." an output which could be an exact integer sub-multiple of 155.52MHz. An output at 9.7200MHz might be handy.

Sadly, the rubidium reference frequency at 6.835GHz isn't an integral multiple of 155.52MHz. Caesium - at 9.193 GHz - isn't any better.

<snipped pedestrian stuff>

> All of that's old-school, meant to be solid and simple. '57 Chevy.

And clumsy. The MC100EP195 could do the same kind of job in a smaller package. The temperature sensitivity of the delay it generates is nasty, and the 10psec resolution means that it's never going to be good for direct synthesis, but it would probably be good enough for a good-enough-for-long-term-stability scheme for generating a monitoring 10MHz output from the 155.52MHz source to be compared with the 10MHz reference crystal by a product detector feeding back through low-pass filter into a nice slow integrator to keep the VCO at the right frequency in the long term.

Today, a DDS PLL-reference generator might be simpler. Clocked at a non-integer multiple of the output frequency, say, 250MHz, a DDS could produce a stair-stepped 960KHz (=155.52e6/162) approximation to a sinewave (for the 155.52MHz PLL) reference, with ~260 steps in it.

There'd be a lot of easily-filtered 250MHz in the output, and a not-so-easily-filtered DAC-error beat frequency component that might be small enough not to matter.

The AD9915 is off the shelf and pretty much complete. $143.10 isn't cheap, but for eight units, what you pay for the off-the-shelf solution is recovered in reduced design time. $1,144.80 doesn't buy a lot of design time.

It's faster than the number you had in mind - at 2.44GHz versus 250MHz - and the non-binary modulus it offers seems to get rid of the DAC-error beat frequency component.

--
Bill Sloman, Sydney

 

On Friday, September 12, 2014 1:23:35 PM UTC-4, John Larkin wrote:

On Thu, 11 Sep 2014 19:59:16 -0700 (PDT), dagmargoo...@yahoo.com wrote:

A DDS to generate a reference signal, then a separate generator to cancel the post-phase detector ripple might be clean circuitry-wise. A dual DDS might provide both.

But it still won't allow me to make exactly 10 MHz from a binary DDS
clocked at 155.52.

But the goal's the opposite, to lock the 155.52e6 to the 10e7 reference, right?

Yes. But if I could make 10 MHz from the 155.52, I could run my phase
detector at 10M instead of 80K.

Yes, understood. Offhand I don't see a simple way to make clean 10MHz from
the 155.52MHz. I showed a clean, simple way to get the phase detector up
from 80K to 640K instead. It's only 8x, but 8x is 8x.

Mike Perkin's method makes 10MHz with 15.552 quantized sine-steps per
cycle, as you asked for.

That might be fine after filtering--I haven't done the math. My gut reaction
to getting from 15.552 steps to ppb jitter just four octaves down is -- yowsa!

Cheers,
James Arthur

 

On Friday, September 12, 2014 2:48:49 PM UTC-4, Mike Perkins wrote:

On 12/09/2014 19:26, dagmargoo...@yahoo.com wrote:
On Friday, September 12, 2014 1:23:35 PM UTC-4, John Larkin wrote:
On Thu, 11 Sep 2014 19:59:16 -0700 (PDT), dagmargoo...@yahoo.com wrote:

A DDS to generate a reference signal, then a separate generator to cancel the post-phase detector ripple might be clean circuitry-wise. A dual DDS might provide both.

But it still won't allow me to make exactly 10 MHz from a binary DDS
clocked at 155.52.

But the goal's the opposite, to lock the 155.52e6 to the 10e7 reference, right?

Yes. But if I could make 10 MHz from the 155.52, I could run my phase
detector at 10M instead of 80K.

Yes, understood. Offhand I don't see a simple way to make clean 10MHz from
the 155.52MHz. I showed a clean, simple way to get the phase detector up
from 80K to 640K instead. It's only 8x, but 8x is 8x.

Mike Perkin's method makes 10MHz with 15.552 quantized sine-steps per
cycle, as you asked for.

That might be fine after filtering--I haven't done the math. My gut reaction
to getting from 15.552 steps to ppb jitter just four octaves down is -- yowsa!

I've seen less steps used in generating RF waveforms with very good
performance using the right filtering to remove the harmonics.

I have too, and I've even done it, but turning stepped waves into perfect
sines doesn't 'feel' right. We all know it works, I'm not arguing that,
but I've got to calculate stuff to be convinced.

I also mistrust having that filter response in the control loop. It might
be fine, I just haven't scratched it out.

As an extreme example, a 10MHz crystal filter would clean things up nicely,
but add tens of mS feedback delays if it's really good (Q ~= 1e5).

You won't even be too far along the sin(x)/x curve.

If the OP prefers more samples per cycle, then phase compare at 5MHz
with over 31 sine-steps or start with 311.04MHz with over 31 sine-steps
and divide by 2 to get 50% duty 155.52MHz clock. The variations are
endless, each with its own advantage.

The principle is that you have more choice rather than being a slave to
80kHz and instead can choose the frequency you do the phase comparison
at, and more choice over the pre and post phase comparator filters.

Understood.

It's a solid topology idea, I just haven't done all the homework.

Cheers,
James Arthur

 

On Friday, September 12, 2014 2:11:10 PM UTC-4, Phil Hobbs wrote:

On 09/11/2014 10:59 PM, dagmargoo...@yahoo.com wrote:
On Thursday, September 11, 2014 8:24:15 PM UTC-4, John Larkin wrote:
On Thu, 11 Sep 2014 17:00:06 -0700 (PDT), dagmargoo...@yahoo.com
wrote:
On Thursday, September 11, 2014 12:29:36 PM UTC-4, John Larkin
wrote:

There's nothing wrong with mechanics, and nothing wrong with
fiddling or accidental solutions.

I was kidding of course. The best designers I've known have always
been great mechanical and otherwise-thinkers and tinkerers too.

Feynman made one of his breakthroughs imagining twirling pie plates.
At a diner, IIRC.

Design is, fundamentally, fiddling, namely exploring an enormous
solution space and finding something that works well. Brains can do
that, somehow. Fiddling is an acquired skill.

Yes. And lots of fiddling at an early age helps.

Equations seldom design stuff.

Yep. Equations usually describe stuff someone already did, help
others duplicate, and sometimes refine it.

That's unduly pessimistic. Before designing an instrument, I always
calculate how good it _could_ be, from first principles where possible.

That way I can (a) select the best possible approach, and (b) know when
it isn't there yet. I couldn't do my job without crunching a fair bit
of math. My rule of thumb is that the final result gets within 1 dB of
the theory most of the time, and within 3 dB almost always (i.e. unless
I've made a math blunder or failed to think of some physical effect that
turns out to be important).

Granted, in your situation.

More often I'm trying to solve novel problems. A long time ago, it was
making clean BPSK SS UHF cheaply from a cheap crystal, at micropower,
fast-settling, with a lot of other constraints. There simply isn't an
equation that outputs a novel topology.

More recently I was tasked loading a device with a ~500A max inrush onto
a supply made to trip-out around a tenth of that, with everything COTS
and "untouchable," lest the certifications be spoiled. That too was
solved with a novel external topology, custom for the application.

For me it's usually topology(/ies) first, then equations to compare
performance, then trade-offs / selection between the choices.

Cheers,
James Arthur

 

[John Larkin]

On Thu, 11 Sep 2014 20:59:19 -0400, Phil Hobbs
<hobbs@electrooptical.net> wrote:

On 9/11/2014 8:24 PM, John Larkin wrote:
On Thu, 11 Sep 2014 17:00:06 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

On Thursday, September 11, 2014 12:29:36 PM UTC-4, John Larkin wrote:
On Thu, 11 Sep 2014 11:52:01 -0400, Phil Hobbs wrote:
On 09/11/2014 11:38 AM, Bill Sloman wrote:
On Friday, 12 September 2014 01:03:22 UTC+10, Phil Hobbs wrote:
On 09/11/2014 08:42 AM, Bill Sloman wrote:
On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann
wrote:
Am 11.09.2014 um 07:40 schrieb josephkk:

The DDS concept is an integer divide system, binary or BCD
makes n difference.

No, it's neither an integer divide system nor does BCD make no
difference.

A counter is an integer divide system.

The frequency resolution of a 48 bit DDS is f_clock/2**48 which
is anything but integer and you can get only multiples of the
resolution out. You may be very close to your intended
frequency but microHz away and that gives you a constant phase
creep.

But you can change the frequency by one resolution step from time
to time, and reverse the phase creep - if you need to. Half a
microHerz is rather more precise than John Larkin's 10MHz clock
is ever going to be. With an atomic clock system, you might want
to manipulate the phase creep, but not here.

With a BCD DDS your step size can be f_clock / 10e6 and that
that is an advantage if you need a frequency that can be
exactly written in a few decimal digits.

But you can write exactly the same number in rather fewer
hexadecimal digits, as long as you remember to include the
trailing zeros as digits.

Nope. With binary, the DDS output frequency is an integer multiple
of f_ref/2**N, whereas with BCD it's an integer multiple of
f_ref/10**M.

It's still the same number, even if it won't generate the same
frequency.

Essentially, using decimal numbers is a bad idea. It uses more
silicon area to achieve much the same result.

So you can write the same integer, but it won't produce the same
output frequency.

Obviously.

And if you knew your reference clock frequency that precisely.

Or, as is quite likely, other things are locked to that same
reference, and need to interoperate.

That's a problem of clock distribution - which is interesting in it's
own right, but not what's been being talked about here.

The big problem with the DDS idea is the DAC+filter. In order to
get rid of the jitter sidebands down to 1 ps, the analog stuff has
to be accurate and stable to about 1 ps * 2 pi *155.2 MHz ~= 0.1%.

Rubbish. The DAC is just producing a tolerable approximation to a
sine wave, and the imperfections should get largely get filtered out
before the DDS output gets into the phase detector.

Quit pontificating and do the math. It's as I said. Phase error due to
additive signals goes as the spur amplitude divided by the maximum phase
slope of the desired signal. 'Tain't rocket science.

Most of the
side-band products get filtered after the detector anyway, and any DC
that's left is a constant (and small) phase offset, not a frequency
offset (if you do it anything like right).

The bang-bang PLL is pretty good for the price.

It's a can of worms. Any noise on the rails can creep on and shift
the switching point. A product phase detector is a lot more
forgiving.

John has shipping products with 1-ps jitter. I have a digital delay box
of his that has 5 ps of jitter, which is about 35 dB better than the SRS
box I used to have. So rather than preening yourself, you might listen
and learn.

No Phil, you're mistaken. John's a mechanic / fiddler who only gets things right accidentally. NOOTTTTT!


There's nothing wrong with mechanics, and nothing wrong with fiddling
or accidental solutions. Design is, fundamentally, fiddling, namely
exploring an enormous solution space and finding something that works
well. Brains can do that, somehow. Fiddling is an acquired skill.

Equations seldom design stuff.




I'm not sure it wouldn't work fine at 80 kHz, if John doesn't need
the wide control bandwidth.

If he went out and bought a decent VXCO, which was an off-the-shelf
item 20 years ago, and ON-Semiconductor now seems to offer as an SMD
component, he could live with a really slow and heavily filtered
phase detector running at 80kHz, but either a DDS or a fractional-N
divider could be made to work at 10MHz and would give much faster
feedback.

John was asking for a smart idea, in order to save money.

I'm only going to build 8 of the boxes in question, so money isn't
really a big deal, except for the Joergian sporting aspects. I thought
the PLL math was interesting, and a discussion group does need stuff
to discuss. Talking about problems with other people helps me to
think, too.

I'm not an RF sort of guy - sine waves are BORING - and some people
here are, so it's interesting to get some fresh ideas.

It occurs to me that there's a lot of similarity between a noiseless
bang-bang PLL and a duty-cycle integrating ADC, and a lot of
similarity between a noisy bangbang and a delta-sigma ADC.

I'm about to go for a jog, but how about some analog ideas?

e.g., if the PLL error signal is messy, add in a jitter-compensating signal.

e.g., do fractional division with an integer number of clocks plus a varying analog ramp delay. That would let you keep a much higher reference frequency.

Even a ramp with horrible resolution is way less jittery than alternating the divider modulii.


One similar textbook technique is to use a dual-modulus divider and,
off to the side, compute a DAC value as a jitter compensation. The DAC
analog output is summed into the phase detector analog output, to
compensate for the small phase jumps inherent in the dual-modulus
math.

I think that a DDS thing might work that way too. If we use the MSB
(ie, rollover) of a phase accumulator as a scaled-down clock, it has a
jitter of one input clock p-p. But, at DDS accumulator overflow time,
we know the values of the lower-down bits of the phase accumulator,
and they could be used to compensate for the MSB jitter. Somehow.

Does that make sense?

Sure. You can compute what the filtered DAC output ought to produce,
and use that. With your DDG chops, you could do that standing on your head.

I still think the local feedback approach (offset analogue loop
disciplined by 80 kHz bang-bang loop to control drift) would be a cool
thing to build.

That does sound nice, some fast RFish loop with the bangbang to servo
the picosecond precision. We might have to do that if the brute-force
80K bangbang gets into trouble.

A cheapish XO will have the jitter that I need out to, say, 1
millisecond. So the 80K bangbang will have to take over there, without
adding a lot of noise. With a better XO, the crossover time increases
and the tradeoff is better.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[John Larkin]

On Thu, 11 Sep 2014 19:59:16 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

On Thursday, September 11, 2014 8:24:15 PM UTC-4, John Larkin wrote:
On Thu, 11 Sep 2014 17:00:06 -0700 (PDT), dagmargoo...@yahoo.com wrote:
On Thursday, September 11, 2014 12:29:36 PM UTC-4, John Larkin wrote:
On Thu, 11 Sep 2014 11:52:01 -0400, Phil Hobbs wrote:
On 09/11/2014 11:38 AM, Bill Sloman wrote:

It's a can of worms. Any noise on the rails can creep on and shift
the switching point. A product phase detector is a lot more
forgiving.

John has shipping products with 1-ps jitter. I have a digital delay box
of his that has 5 ps of jitter, which is about 35 dB better than the SRS
box I used to have. So rather than preening yourself, you might listen
and learn.

No Phil, you're mistaken. John's a mechanic / fiddler who only gets things right accidentally. NOOTTTTT!

There's nothing wrong with mechanics, and nothing wrong with fiddling
or accidental solutions.

I was kidding of course. The best designers I've known have always been great mechanical and otherwise-thinkers and tinkerers too.

Feynman made one of his breakthroughs imagining twirling pie plates. At a diner, IIRC.

Design is, fundamentally, fiddling, namely
exploring an enormous solution space and finding something that works
well. Brains can do that, somehow. Fiddling is an acquired skill.

Yes. And lots of fiddling at an early age helps.

Equations seldom design stuff.

Yep. Equations usually describe stuff someone already did, help others duplicate, and sometimes refine it.

[...]

I'm only going to build 8 of the boxes in question, so money isn't
really a big deal, except for the Joergian sporting aspects. I thought
the PLL math was interesting, and a discussion group does need stuff
to discuss. Talking about problems with other people helps me to
think, too.

I'm not an RF sort of guy - sine waves are BORING - and some people
here are, so it's interesting to get some fresh ideas.

It occurs to me that there's a lot of similarity between a noiseless
bang-bang PLL and a duty-cycle integrating ADC, and a lot of
similarity between a noisy bangbang and a delta-sigma ADC.

I'm about to go for a jog, but how about some analog ideas?

e.g., if the PLL error signal is messy, add in a jitter-compensating signal.

e.g., do fractional division with an integer number of clocks plus a varying analog ramp delay. That would let you keep a much higher reference frequency.

Even a ramp with horrible resolution is way less jittery than alternating the divider modulii.

One similar textbook technique is to use a dual-modulus divider and,
off to the side, compute a DAC value as a jitter compensation. The DAC
analog output is summed into the phase detector analog output, to
compensate for the small phase jumps inherent in the dual-modulus
math.

Yes, that was my 2nd suggestion.

I think that a DDS thing might work that way too. If we use the MSB
(ie, rollover) of a phase accumulator as a scaled-down clock, it has a
jitter of one input clock p-p. But, at DDS accumulator overflow time,
we know the values of the lower-down bits of the phase accumulator,
and they could be used to compensate for the MSB jitter. Somehow.

Does that make sense?

It does. If you had access to the lower bits you could, in theory, phase-adjust the DDS output by adding a small DAC'd correction. I think that works. (I'm not sure of all the numbers and trade-offs without actually calculating.)

A DDS to generate a reference signal, then a separate generator to cancel the post-phase detector ripple might be clean circuitry-wise. A dual DDS might provide both.

But it still won't allow me to make exactly 10 MHz from a binary DDS
clocked at 155.52.

But the goal's the opposite, to lock the 155.52e6 to the 10e7 reference, right?

Yes. But if I could make 10 MHz from the 155.52, I could run my phase
detector at 10M instead of 80K.



--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[John Larkin]

On Fri, 12 Sep 2014 03:31:49 +0100, Mike Perkins <spam@spam.com>
wrote:

On 11/09/2014 11:20, Mike Perkins wrote:
On 10/09/2014 00:54, John Larkin wrote:


If I hypothetically had a 10 MHz reference and wanted to lock a
155.52 MHz VCXO to it, the obvious way would be to divide both down
to 80 KHz (the GCD) and drive a phase detector back into the VCXO.
But that's a pretty low frequency to run the PD at; to get
picosecond stability, an ordinary analog phase detector would need
better than 1 PPM analog accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work,
but 80K is still pretty low.

There must be tricks to run the phase detector at a higher
frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz,
but that sounds jitterey to me, and it looks like I can't hit the
exact frequency ratio anyhow.

An idea came to me that may or may not be of interest.

You can get multi-bit DACs at several hundred MSPS and higher but I
presume there is an upper limit to your project inventory.

The use of a DDS has been mentioned and of course most DDS's would
use a binary 32 bit counter.

Have you considered using a non-binary count, one that is a multiple
of 125? Your lookup phase table would also need to be modified and 3
* 2>>n would need to be subtracted when the counter wraps round.

Then use a phase comparator at 10MHz with very simple filtering to
drive your VXCO.

You could use a multiple of 155.52MHz to drive the DDS though most
FPGA would only play ball at fundamental. If a FPGA has a DDR
interface is used then certainly it is possible to double up on
samples even with a slow FPGA and indeed is something I have done.

This would maintain a perfect phase relationship between the 10MHz
and the 155.52MHz.

Perhaps I haven't explained myself very well.

What we require is to equate 155.52MHz with 10MHz, such that after
15.552 clock cycles we can produce exactly a single cycle of a sine wave.

Lets suppose we have a sine table that is comprises of 1,944 points with
an amplitude of say 255 for use with an 8 bit DAC.

V = 255 * sin( 360 * n / 1,944)

We can load this into block memory of a FPGA.

For every clock at 155.52MHz we advance the phase by adding 125 to the
accumulator that counts modulo 1,944.

After 15.52 clocks (or 100ns) we would on average have moved along the
whole of the phase table and so output a complete cycle of sine-wave.

The DAC would be driven by the amplitude corresponding to the
accumulator/position in the phase table. We can filter to remove higher
harmonics to leave a healthy 10MHz sine wave.

We can compare with this single cycle (with a 100ns period) with the
cycle we have from the reference 10MHz using a phase comparator.

We have all come across DDS's that use a binary count, but there is no
reason why the count can't be modulo an alternative number. Of course
the phase table length must suit.

A scheme like that would work if all I needed was a stable frequency.
But I also want picosecond timing accuracy. Things like DACs, lowpass
filters, and phase detectors will all have drift with time and
temperature, and a picosecond is a cruel unit of measure.

An ECL bangbang phase detector is the only thing I can think of that
has picosecond time stability, and it looks like it must work at 80
KHz. As Phil suggests, it could be the DC part of a compound loop.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Phil Hobbs]

On 09/11/2014 10:59 PM, dagmargoodboat@yahoo.com wrote:

On Thursday, September 11, 2014 8:24:15 PM UTC-4, John Larkin wrote:
On Thu, 11 Sep 2014 17:00:06 -0700 (PDT), dagmargoo...@yahoo.com
wrote:
On Thursday, September 11, 2014 12:29:36 PM UTC-4, John Larkin
wrote:
On Thu, 11 Sep 2014 11:52:01 -0400, Phil Hobbs wrote:
On 09/11/2014 11:38 AM, Bill Sloman wrote:

It's a can of worms. Any noise on the rails can creep on
and shift the switching point. A product phase detector is
a lot more forgiving.

John has shipping products with 1-ps jitter. I have a
digital delay box of his that has 5 ps of jitter, which is
about 35 dB better than the SRS box I used to have. So
rather than preening yourself, you might listen and learn.

No Phil, you're mistaken. John's a mechanic / fiddler who only
gets things right accidentally. NOOTTTTT!

There's nothing wrong with mechanics, and nothing wrong with
fiddling or accidental solutions.

I was kidding of course. The best designers I've known have always
been great mechanical and otherwise-thinkers and tinkerers too.

Feynman made one of his breakthroughs imagining twirling pie plates.
At a diner, IIRC.

Design is, fundamentally, fiddling, namely exploring an enormous
solution space and finding something that works well. Brains can do
that, somehow. Fiddling is an acquired skill.

Yes. And lots of fiddling at an early age helps.

Equations seldom design stuff.

Yep. Equations usually describe stuff someone already did, help
others duplicate, and sometimes refine it.

That's unduly pessimistic. Before designing an instrument, I always
calculate how good it _could_ be, from first principles where possible.

That way I can (a) select the best possible approach, and (b) know when
it isn't there yet. I couldn't do my job without crunching a fair bit
of math. My rule of thumb is that the final result gets within 1 dB of
the theory most of the time, and within 3 dB almost always (i.e. unless
I've made a math blunder or failed to think of some physical effect that
turns out to be important).

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Mike Perkins]

On 12/09/2014 19:26, dagmargoodboat@yahoo.com wrote:

On Friday, September 12, 2014 1:23:35 PM UTC-4, John Larkin wrote:
On Thu, 11 Sep 2014 19:59:16 -0700 (PDT), dagmargoo...@yahoo.com wrote:

A DDS to generate a reference signal, then a separate generator to cancel the post-phase detector ripple might be clean circuitry-wise. A dual DDS might provide both.

But it still won't allow me to make exactly 10 MHz from a binary DDS
clocked at 155.52.

But the goal's the opposite, to lock the 155.52e6 to the 10e7 reference, right?

Yes. But if I could make 10 MHz from the 155.52, I could run my phase
detector at 10M instead of 80K.

Yes, understood. Offhand I don't see a simple way to make clean 10MHz from
the 155.52MHz. I showed a clean, simple way to get the phase detector up
from 80K to 640K instead. It's only 8x, but 8x is 8x.

Mike Perkin's method makes 10MHz with 15.552 quantized sine-steps per
cycle, as you asked for.

That might be fine after filtering--I haven't done the math. My gut reaction
to getting from 15.552 steps to ppb jitter just four octaves down is -- yowsa!

I've seen less steps used in generating RF waveforms with very good
performance using the right filtering to remove the harmonics.

You won't even be too far along the sin(x)/x curve.

If the OP prefers more samples per cycle, then phase compare at 5MHz
with over 31 sine-steps or start with 311.04MHz with over 31 sine-steps
and divide by 2 to get 50% duty 155.52MHz clock. The variations are
endless, each with its own advantage.

The principle is that you have more choice rather than being a slave to
80kHz and instead can choose the frequency you do the phase comparison
at, and more choice over the pre and post phase comparator filters.

--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk