PLL tricks

[John Larkin]

On Wed, 10 Sep 2014 04:57:02 -0500, ChesterW <iamsnoozin@yahoo.com>
wrote:

On 9/9/14, 6:54 PM, John Larkin wrote:


If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.



It's clunky, but no tricks required:

increase 10 MHz by 3^4 yielding 810 MHz

Divide 810 MHz by 5^3 yielding 6.48 MHz

increase 6.48 MHz by 2^3 * 3 yielding 155.52 MHz

The prime factors for these odd-sounding frequencies are surprisingly small.

ChesterW

The divisor for 80 KHz mixing are 125 and 1944.

125 = 5 * 5 * 5

1944 = 2 * 2 * 2 * 3 * 3 * 3 * 3 * 3

so there are things that can be done.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[whit3rd]

On Wednesday, September 10, 2014 12:49:08 PM UTC-4, John Larkin wrote:

Thing about a DDS is that it can only output edges aligned with input
edges. In my case, 10MHz and 155.52 MHz edges align once every 12.5
usec. ...

The only thing I can think of just now is to run the VCO at some
multiple of 155.52, so I can have a GCD higher than 80K.

Or, use two loops? the multipliers break down

The divisor for 80 KHz mixing are 125 and 1944.
125 = 5 * 5 * 5
1944 = 2 * 2 * 2 * 3 * 3 * 3 * 3 * 3

so first PLL the 10 MHz up by 3*3*3 and down by 5; that's 2 MHz
at the phase comparator, and gives you a 27/5 * 10 MHz intermediate clock.
Second stage, up by 16*9 and down by 5, that's double the frequency
you want (so a final divide-by-two flipflop gives a clean signal). The second
PLL has its comparator at about 10 MHz.

 

[John Larkin]

On Wed, 10 Sep 2014 10:54:45 +0200, Gerhard Hoffmann
<ghf@hoffmann-hochfrequenz.de> wrote:

Am 10.09.2014 um 01:54 schrieb John Larkin:

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.

Dividing EXACTLY with a DDS can be surprisingly hard, one could
find that one is always off by 2e-32 or 2e-48 or whatever
but one is never exactly on the spot, never really synchronous.

Once, there was a BCD coded DDS from Stanford IIRC that
could get it exact for easy-to-write decimal numbers.

Today one could put it into an FPGA. A BCD based adder
is easy. I have put a VHDL-only sine table on opencores.org
that should also be easy to modify.

regards, Gerhard

Thing about a DDS is that it can only output edges aligned with input
edges. In my case, 10MHz and 155.52 MHz edges align once every 12.5
usec. Changing the DDS radix can let me synthesize 10.000 MHz from
155.52, but it can only do that by jittering edges around an average
value. So, that would put me back to needing analog precision in the
phase detector. Less than before, but still intimidating.

The only thing I can think of just now is to run the VCO at some
multiple of 155.52, so I can have a GCD higher than 80K. So it becomes
a search for a super-low-phase-noise VCO in the low GHz ballpark. SAW
or ceramic resonator maybe?


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[ChesterW]

On 9/10/14, 9:25 AM, John Larkin wrote:

On Wed, 10 Sep 2014 04:57:02 -0500, ChesterW <iamsnoozin@yahoo.com
wrote:

On 9/9/14, 6:54 PM, John Larkin wrote:


If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.



It's clunky, but no tricks required:

increase 10 MHz by 3^4 yielding 810 MHz

Divide 810 MHz by 5^3 yielding 6.48 MHz

increase 6.48 MHz by 2^3 * 3 yielding 155.52 MHz

The prime factors for these odd-sounding frequencies are surprisingly small.

ChesterW

The divisor for 80 KHz mixing are 125 and 1944.

125 = 5 * 5 * 5

1944 = 2 * 2 * 2 * 3 * 3 * 3 * 3 * 3

so there are things that can be done.


Hi John,

Using 80 kHz comes with the requirement for high analog precision. You
wanted to trade speed for precision, a good idea, especially since speed
is so cheap. So you don't care about the prime factors of 80 kHz. The
important factors are:

2^10 * 3^5 * 5^4 = 155.52 MHz and

2^7 * 5^7 = 10 MHz.

One solution to your problem is fractional, which has already been
discussed. To keep the solution in the integers (and above 80 kHz and
below about 20 GHz), I think you need two VCOs and a divider.

The advantage of this approach is that you should have a simple system
with easy-to-predict phase noise and no surprises. The disadvantage is
that you need more parts.

There are combinations other that what I showed earlier, for example you
can increase the 10 MHz by 3^3 yielding 270 MHz. Divide 270 MHz by 5^3
yielding 2.16 MHz. Increase 2.16 MHz by 2^3 * 3^2 yielding 155.52 MHz.

Thanks for the chance to play with the prime numbers. I don't get to do
that often.

ChesterW

 

[Bill Sloman]

On Thursday, 11 September 2014 02:49:08 UTC+10, John Larkin wrote:

On Wed, 10 Sep 2014 10:54:45 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 10.09.2014 um 01:54 schrieb John Larkin:

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.

Dividing EXACTLY with a DDS can be surprisingly hard, one could
find that one is always off by 2e-32 or 2e-48 or whatever
but one is never exactly on the spot, never really synchronous.

Only if you choose to divide by an irrational number (like e or pi).

<snip>

Thing about a DDS is that it can only output edges aligned with input
edges. In my case, 10MHz and 155.52 MHz edges align once every 12.5
usec. Changing the DDS radix can let me synthesize 10.000 MHz from
155.52, but it can only do that by jittering edges around an average
value. So, that would put me back to needing analog precision in the
phase detector. Less than before, but still intimidating.

The raw DDS output can only output edges aligned with it's internal clock, but many DDS chips have a built-in frequency multiplier to make the internal clock a lot faster than the external reference.

And you are supposed to filter the DDS output to smear out the edges - the steps on the stair-case approximation to a true sine wave output.

An analog - multiplying - phase detector does produce an output containing high frequency content, but you are supposed to low-pass filter this to the point that it doesn't produce significant phase excursions at the VCO.

<snipped further exhibition of intellectual poverty>

--
Bill Sloman, Sydney

 

[Tauno Voipio]

On 10.9.14 19:49, John Larkin wrote:

Thing about a DDS is that it can only output edges aligned with input
edges. In my case, 10MHz and 155.52 MHz edges align once every 12.5
usec. Changing the DDS radix can let me synthesize 10.000 MHz from
155.52, but it can only do that by jittering edges around an average
value. So, that would put me back to needing analog precision in the
phase detector. Less than before, but still intimidating.

The DDS output is an analog sine wave. You *do* need the reconstruction
low-pass filter after the DAC. The DAC values are correct for the sine
at the incloming clock intervals, so the low-pass interpolates them
for the other times.

How about using a DDS for 10 MHz from 155.52 MHz and phase detecting
the low-pass filtered output using sampling controlled by your
10 MHz reference?

--

Tauno Voipio

 

[John Larkin]

On Wed, 10 Sep 2014 14:30:26 -0500, ChesterW <iamsnoozin@yahoo.com>
wrote:

On 9/10/14, 9:25 AM, John Larkin wrote:
On Wed, 10 Sep 2014 04:57:02 -0500, ChesterW <iamsnoozin@yahoo.com
wrote:

On 9/9/14, 6:54 PM, John Larkin wrote:


If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.



It's clunky, but no tricks required:

increase 10 MHz by 3^4 yielding 810 MHz

Divide 810 MHz by 5^3 yielding 6.48 MHz

increase 6.48 MHz by 2^3 * 3 yielding 155.52 MHz

The prime factors for these odd-sounding frequencies are surprisingly small.

ChesterW

The divisor for 80 KHz mixing are 125 and 1944.

125 = 5 * 5 * 5

1944 = 2 * 2 * 2 * 3 * 3 * 3 * 3 * 3

so there are things that can be done.


Hi John,

Using 80 kHz comes with the requirement for high analog precision. You
wanted to trade speed for precision, a good idea, especially since speed
is so cheap. So you don't care about the prime factors of 80 kHz. The
important factors are:

2^10 * 3^5 * 5^4 = 155.52 MHz and

2^7 * 5^7 = 10 MHz.

One solution to your problem is fractional, which has already been
discussed. To keep the solution in the integers (and above 80 kHz and
below about 20 GHz), I think you need two VCOs and a divider.

The advantage of this approach is that you should have a simple system
with easy-to-predict phase noise and no surprises. The disadvantage is
that you need more parts.

There are combinations other that what I showed earlier, for example you
can increase the 10 MHz by 3^3 yielding 270 MHz. Divide 270 MHz by 5^3
yielding 2.16 MHz. Increase 2.16 MHz by 2^3 * 3^2 yielding 155.52 MHz.

Thanks for the chance to play with the prime numbers. I don't get to do
that often.

ChesterW

Yeah, all sorts of number theory stuff pops up when you do things like
this.


This is sort of interesting: clock a mod-1944 counter from 155.52 MHz.
It ticks every 6.43... ns.

Every 12.5 us, namely every state 0 of the counter, it aligns
perfectly with the 10 MHz ref, whose period is 100 ns.

No other states of the 155 MHz counter align with the 100 ns ref
period, GCD duh, but some come awfully close.

State 902 happens at 5,799.897 ns, which is only 103 ps before a 10
MHz ref edge.

State 1042 is 103 ps late.

State 1244 is 29 ps early.

1493 is 51 ps late.


I wonder if we could work with them somehow.




--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Gerhard Hoffmann]

Am 10.09.2014 um 18:49 schrieb John Larkin:

Thing about a DDS is that it can only output edges aligned with input
edges. In my case, 10MHz and 155.52 MHz edges align once every 12.5
usec. Changing the DDS radix can let me synthesize 10.000 MHz from
155.52, but it can only do that by jittering edges around an average
value. So, that would put me back to needing analog precision in the
phase detector. Less than before, but still intimidating.

There is no jitter, the low pass after the DAC is part of the game.

But now, with plenty 24*24 Multipliers in an FPGA, that are obscenely
cheap and that run at hundreds of MHz, I would do the phase comparision
in the digital domain. Then you get a near-DC control voltage that
is oversampled at 10 or even 155 MSPS, easy to filter.

When the 10 MHz ref is only 0/1, even a multiplier might be a
luxury. And the DAC also, a PWM output might do.

Ooohps, I'm getting Joergish!

Gerhard

 

[Gerhard Hoffmann]

Am 10.09.2014 um 22:44 schrieb Gerhard Hoffmann:

I'll play the Ingrid:

But now, with plenty 24*24 Multipliers in an FPGA, that are obscenely
cheap and that run at hundreds of MHz, I would do the phase comparision
in the digital domain. Then you get a near-DC control voltage that
is oversampled at 10 or even 155 MSPS, easy to filter.

When the 10 MHz ref is only 0/1, even a multiplier might be a
luxury. And the DAC also, a PWM output might do.

With 1/0 10MHz one would probably divide to 5MHz for the comparision
to be independent of duty cycle. And for the sampling rate, 155
makes more sense.

Gerhard

ps In German newsgroups, there was a woman called Ingrid who used to
follow-up her own posts excessively. Therefore now:
"Ich mache mal die Ingrid."

 

[John Larkin]

On Wed, 10 Sep 2014 22:44:34 +0200, Gerhard Hoffmann
<ghf@hoffmann-hochfrequenz.de> wrote:

Am 10.09.2014 um 18:49 schrieb John Larkin:


Thing about a DDS is that it can only output edges aligned with input
edges. In my case, 10MHz and 155.52 MHz edges align once every 12.5
usec. Changing the DDS radix can let me synthesize 10.000 MHz from
155.52, but it can only do that by jittering edges around an average
value. So, that would put me back to needing analog precision in the
phase detector. Less than before, but still intimidating.

There is no jitter, the low pass after the DAC is part of the game.

A DAC, lowpass (or bandpass) filter, and comparator get me back into
the high-precision analog business as regards picosecond timing
accuracy.

But now, with plenty 24*24 Multipliers in an FPGA, that are obscenely
cheap and that run at hundreds of MHz, I would do the phase comparision
in the digital domain. Then you get a near-DC control voltage that
is oversampled at 10 or even 155 MSPS, easy to filter.

When the 10 MHz ref is only 0/1, even a multiplier might be a
luxury. And the DAC also, a PWM output might do.

Ooohps, I'm getting Joergish!

Yikes! You'll be chopping firewood next.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[ChesterW]

On 9/10/14, 3:29 PM, John Larkin wrote:
<snip>

Yeah, all sorts of number theory stuff pops up when you do things like
this.

I was a mathematician before I became an engineer. Number theory was one
of my favorite areas.

This is sort of interesting: clock a mod-1944 counter from 155.52 MHz.
It ticks every 6.43... ns.

Every 12.5 us, namely every state 0 of the counter, it aligns
perfectly with the 10 MHz ref, whose period is 100 ns.

No other states of the 155 MHz counter align with the 100 ns ref
period, GCD duh, but some come awfully close.

State 902 happens at 5,799.897 ns, which is only 103 ps before a 10
MHz ref edge.

State 1042 is 103 ps late.

State 1244 is 29 ps early.

1493 is 51 ps late.


I wonder if we could work with them somehow.

I just pictured a circuit with 2 * 1944 comparators

ChesterW

 

[Bill Sloman]

On Thursday, 11 September 2014 14:03:17 UTC+10, John Larkin wrote:

On Wed, 10 Sep 2014 21:02:35 -0500, tim <tim@seemywebsite.com> wrote:
On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin wrote:

If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

But if you the 155.52MHz as the reference input to a DDS generating a 10MHz sine wave clock and compare that with a 10MHz sine wave clock generated by your high quality reference crystal, the analog output from a multiplying phase detector would contain a large 20MHz component which you'd have to filter out, and cross products with any high frequency ripple on the DDS output that you hadn't filtered out.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

Much lower than it needs to be. And building an edge-sensitve phase detector when you could buy an Analog Devices AD834 - back in 1989 I used something more specialised, but ti doesn't seem to be available any more - probably wouldn't be wise.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.

Think again.

What do you mean by "picosecond stability?"

My 155.52 clock shouldn't drift in time more than, say, 10 ps relative
to the 10 MHz reference. If I use an analog phase detector (multiplier
or charge pump) at 80 KHz, it will need to have roughly 1 PPM analog
stability.

But with a DDS you can run it at 10MHz, as you could with a fractional-N scheme, though with more noise on the raw phase-detector output (which would be easy to filter out).

I can use a edge-sensitive phase detector, namely an ECL d-flop, as a
bang-bang early/late sensor, which would have esentially infinite gain
and single-digit-picosecond long-term stability. But the loop
filtering will be ugly. The bang-bang detector output would be
essentially random 1s and 0s at 80 KHz, which will contain a bunch of
low frequency noise.

Which makes it a really silly - as well as a quite unnecessary - idea.

If you mean jitter, and the VXCO is good enough, then it should smooth
over noise in the PD.

An 80KHz phase detector will need to be filtered hard to keep from
wobbling the VCXO. That means the XO has to have very low open-loop
jitter at frequencies where the loop doesn't discipline it. It can be
done, it's just tough.

But you can buy it - pre-done - from ON Semiconductor, so it just needs spending enough money in the right place. Nothing tough about that.

http://www.onsemi.com/pub_link/Collateral/NBVSPXXXX-D.PDF

If you wanted a small batch, you might have to go to a crystal specialist who could thin a couple of special crystal for you for 155.52MHz. They've been available for a couple of decades now.

--
Bill Sloman, Sydney

 

[Bill Sloman]

On Thursday, 11 September 2014 15:03:01 UTC+10, rickman wrote:

On 9/9/2014 7:54 PM, John Larkin wrote:

If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a

pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.

I'm sure you know a lot more about 1 ps phase detectors than I do, but
when you say "exact"... when does a frequency ever need to be "exact"?

Won't the input be within some accuracy spec? Or is this a case where
the two frequencies have to be in lock step for some digital stuff to
work correctly? It just seems like some odd frequencies to require
exact frequency ratios.

BTW, a DDS *would* be very jittery at those numbers.

The raw DDS output would be a 15.5 step staircase-approximation to a sine wave.
That's 23 degree steps, and 20% of full-scale steps in amplitude for the biggest steps.

You'd use a low pass filter to get rid of the 155.52MHz content and its higher harmonics. A handful of poles of low-pass filter would clean it up no end, and a notch could do even better.

PLL loop stability has to cope with the phase delay (and frequency dependent excursions) through the filter, but that's cookbook stuff.

Nobody sane uses a DDS without an output filter, though with a big gap between the reference frequency and the synthesised frequency, you don't need much filtering.

--
Bill Sloman, Sydney

 

[John Larkin]

On Wed, 10 Sep 2014 21:02:35 -0500, tim <tim@seemywebsite.com> wrote:

On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin wrote:

If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.

What do you mean by "picosecond stability?"

My 155.52 clock shouldn't drift in time more than, say, 10 ps relative
to the 10 MHz reference. If I use an analog phase detector (multiplier
or charge pump) at 80 KHz, it will need to have roughly 1 PPM analog
stability.

I can use a edge-sensitive phase detector, namely an ECL d-flop, as a
bang-bang early/late sensor, which would have esentially infinite gain
and single-digit-picosecond long-term stability. But the loop
filtering will be ugly. The bang-bang detector output would be
essentially random 1s and 0s at 80 KHz, which will contain a bunch of
low frequency noise.

If you mean jitter, and the VXCO is good enough, then it should smooth
over noise in the PD.

An 80KHz phase detector will need to be filtered hard to keep from
wobbling the VCXO. That means the XO has to have very low open-loop
jitter at frequencies where the loop doesn't discipline it. It can be
done, it's just tough.




--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[rickman]

On 9/9/2014 7:54 PM, John Larkin wrote:

If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.

I'm sure you know a lot more about 1 ps phase detectors than I do, but
when you say "exact"... when does a frequency ever need to be "exact"?
Won't the input be within some accuracy spec? Or is this a case where
the two frequencies have to be in lock step for some digital stuff to
work correctly? It just seems like some odd frequencies to require
exact frequency ratios.

BTW, a DDS *would* be very jittery at those numbers.

--

Rick

 

[Joe Chisolm]

On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin wrote:

If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.

You trying to build a OC3 framer but with a 10MHz refclock?


--
Chisolm
Republic of Texas

 

[tim]

On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin wrote:

If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.

What do you mean by "picosecond stability?"

If you mean jitter, and the VXCO is good enough, then it should smooth
over noise in the PD.

--
www.wescottdesign.com

 

[josephkk]

On Wed, 10 Sep 2014 07:21:30 -0700, John Larkin
<jlarkin@highlandtechnology.com> wrote:

On Wed, 10 Sep 2014 10:54:45 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:

Am 10.09.2014 um 01:54 schrieb John Larkin:

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.

Dividing EXACTLY with a DDS can be surprisingly hard, one could
find that one is always off by 2e-32 or 2e-48 or whatever
but one is never exactly on the spot, never really synchronous.


Right. One rounding bit out of 48, or even 64, would give me a slow
phase creep.



Once, there was a BCD coded DDS from Stanford IIRC that
could get it exact for easy-to-write decimal numbers.

Yeah, decimal might work.


Today one could put it into an FPGA. A BCD based adder
is easy. I have put a VHDL-only sine table on opencores.org
that should also be easy to modify.

That is interesting. We might look into a decimal DDS.

The DDS concept is an integer divide system, binary or BCD makes no
difference.

?-)

 

[josephkk]

On Wed, 10 Sep 2014 21:03:17 -0700, John Larkin
<jlarkin@highlandtechnology.com> wrote:

On Wed, 10 Sep 2014 21:02:35 -0500, tim <tim@seemywebsite.com> wrote:

On Tue, 09 Sep 2014 16:54:53 -0700, John Larkin wrote:

If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.

What do you mean by "picosecond stability?"

My 155.52 clock shouldn't drift in time more than, say, 10 ps relative
to the 10 MHz reference. If I use an analog phase detector (multiplier
or charge pump) at 80 KHz, it will need to have roughly 1 PPM analog
stability.

I can use a edge-sensitive phase detector, namely an ECL d-flop, as a
bang-bang early/late sensor, which would have esentially infinite gain
and single-digit-picosecond long-term stability. But the loop
filtering will be ugly. The bang-bang detector output would be
essentially random 1s and 0s at 80 KHz, which will contain a bunch of
low frequency noise.


If you mean jitter, and the VXCO is good enough, then it should smooth
over noise in the PD.

An 80KHz phase detector will need to be filtered hard to keep from
wobbling the VCXO. That means the XO has to have very low open-loop
jitter at frequencies where the loop doesn't discipline it. It can be
done, it's just tough.

Nor is it all as simple as you expect. The SONET system is designed to be
able to eat amazing amounts of clock drift and not lose data or effective
synchronization.

Lemme see if i can work this out:

DS1 is 1.544 Mb/s
DS2 is 4 DS1 + Overhead 6.312 Mb/s
DS3 is 28 DS1 (6 DS2)+ Overhead 44.736 Mb/s
1 DS3 plus SONET overhead is STS-1 51.84 Mb/s
The STS-1 is 9 rows of 90 Bytes
Of this the first 3 bytes are high level overhead including
Section over head
Pointer
Line overhead
and SPE
SPE is one byte POH and 86 bytes payload per row
That makes for 774 bytes of payload and 36 bytes of overhead per STS-1
frame.

The system allows for continuous positive and negative byte slip for each
DS1 (VT 1.7) tributary.

Please see:

<http://www.cisco.com/c/en/us/support/docs/optical/synchronous-optical-network-sonet/28081-sonet-28081.html#c>
<http://en.wikipedia.org/wiki/Synchronous_optical_networking>
<http://www.exar.com/uploadedfiles/home/sonet-sdh-essentials_022508.pdf>

 

[Bill Sloman]

On Thursday, 11 September 2014 19:11:58 UTC+10, Gerhard Hoffmann wrote:

Am 11.09.2014 um 07:40 schrieb josephkk:

The DDS concept is an integer divide system, binary or BCD makes n
difference.

No, it's neither an integer divide system nor does BCD make no difference..

A counter is an integer divide system.

The frequency resolution of a 48 bit DDS is f_clock/2**48 which is
anything but integer and you can get only multiples of the
resolution out. You may be very close to your intended frequency
but microHz away and that gives you a constant phase creep.

But you can change the frequency by one resolution step from time to time, and reverse the phase creep - if you need to. Half a microHerz is rather more precise than John Larkin's 10MHz clock is ever going to be. With an atomic clock system, you might want to manipulate the phase creep, but not here..

With a BCD DDS your step size can be f_clock / 10e6 and that
that is an advantage if you need a frequency that can be
exactly written in a few decimal digits.

But you can write exactly the same number in rather fewer hexadecimal digits, as long as you remember to include the trailing zeros as digits.

And if you knew your reference clock frequency that precisely.

And also, you need the lowpass after the dds only if you
cross the boundary from a sampled to a continuous system.

For example in a software defined radio it is perfectly
legal to multiply the data from the antenna ADC with the
output from the sin&cos table to convert them to an IF
or to baseband. There is no low pass involved.

No quite the same problem. John's desired output is a low jitter 155.52MHz clock, not an audio signal to be heard by a human being.

That makes it attractive to do the phase comparison in the
sampled domain and to d/a convert only the tune voltage to
the VCXO which is just nervous DC.

So John divides his 10MHz reference clock to 80kHz, counts transitions of his nominally 155.52MHz clock and compares the sum with 1944. If the sum is 1945 the nominally 155.52MHz clock was running at 155.6MHz, and if 1943 at 155.44MHz and in either case some 6.4nsec of jitter have built up.

The problem with the digital domain is that it is slow and coarse.

The loop integrator would be digital, too; it's just an adder
and a register. Sorry, no precision op amp and foil capacitors.

The your VXCO had better have very good medium term stability, because you are going to have to integrate a lot of clock edges before you know enough to start twiddling the control voltage.

There is not much need to maximize loop bandwidth to
correct the 1/f noise, the telecom people ignore the first
few KHz altogether, where it's hard.

In other words, forget the 1psec jitter specification.

Those ps numbers carry a completely different meaning in
normal time distribution and navigation.

Really. One picosecond is a very well-defined interval. You seem to have decided that having an edge creep a few psec away from it's nominal position doesn't matter if it a) happens slowly enough and b) will eventually creep back where it belongs.

You may be right, but that's not obvious from the way the problem has been stated.

--
Bill Sloman, Sydney