Clock Edge notation

[HT-Lab]

"Pinhas" <bknpk@hotmail.com> wrote in message
news:cd9b126f-6f99-4776-9542-6057050951bd@e67g2000hsa.googlegroups.com...

On Apr 14, 8:43 pm, Sue <sudha...@gmail.com> wrote:
Does anyone know how can I get started on making a DOS script file to
synthesize a VHDL design. I tried understanding something
from:http://toolbox.xilinx.com/docsan/xilinx5/pdf/docs/xst/xst.pdf

But I still need more help.
Can someone please tell me the sequence which I should follow.

Thanks

I would suggest to install cygwin and use bash or perl script. Later
you'll be able to migrate to linux/unix machines.
http://bknpk.no-ip.biz/

I believe the OP is asking how to run XST from DOS.

However, IMHO, for something quick and dirty a DOS bat file is hard to beat.
If you want something more elaborate I would suggest Tcl which runs on all
platforms, is very powerful and easy to learn. In addition most if not all
EDA tools support it.

Hans
www.ht-lab.com

 

[HT-Lab]

"Niv" <kev.parsons@mbda.co.uk> wrote in message
news:24b1ea6c-6194-49c8-94eb-2746fd2c25e3@t54g2000hsg.googlegroups.com...

Hi all, we currently use VHDL for all our design & verification via
testbenches.
I have been asked to look at alternative verification methodologies,
particularly SystemVerilog.

SystemVerilog is a language, not a verification methodology. Perhaps you
should focus on the required methodology first and then look at the
available languages and tools?

(I've been on a PSL course a few years ago, but until now never had
the tool(s) to exploit it's use,

Yes unfortunately the tools for PSL/SVA are quite expensive, lets hope
VHDL2007/8 will introduce more people to the power of assertions and as such
bring the price down.

but
people seem to think SysVerilog may be a better approach anyway.

Better approach for what, Assertion Based Verification(ABV), Testbench
Development, Constrained Random(CR), Transaction Level Modelling(TLM),
fixed/floating point modelling?

So, what is the best book(s) to learn SV for a VHDL conversant
audience, and possibly more important,
whare can we quickly learn what SV can do for us above and beyond VHDl
testbenches.

Probably less than what you would expect. As posted some time ago VHDL can
be used for TLM, CR, ABV (using PSL) but probably not as easy as with a
modern language like SystemVerilog/SystemC.

Another option as suggested by Darrin is to look at SystemC. The advantage
of SystemC is that you can add it to a "lowcost" simulator like Modelsim PE
(no need to go to SE/Questa) and it will give you access to TLM, CR, OO and
a very easy C/C++ interface to your PE VHDL.

Hans
www.ht-lab.com

(Cross posted to Verilog group)

Regards, Niv.

 

[HT-Lab]

"Niv" <kev.parsons@mbda.co.uk> wrote in message
news:4b4679c3-efc2-4d48-8edf-a0674bec2ae7@c65g2000hsa.googlegroups.com...

On 16 Apr, 12:47, "HT-Lab" <han...@ht-lab.com> wrote:
"Niv" <kev.pars...@mbda.co.uk> wrote in message

...

Regards, Niv.- Hide quoted text -

- Show quoted text -

We do have ModelSim SE & Questa, so that's not an issue.
However, no-one is really using Questa at the moment due to lack of
understanding of what we can do with it.

In that case I would suggest studying the AVM/OVM which is quite a
comprehensive verification environment and supported by Questa. You can
download a free copy from the Mentor website

http://www.mentor.com/products/fv/_3b715c/

We currently do large FPGA designs and test using VHDL testbenches
(quite a lot of VHDL ASSERT statements are used).
I've been led to believe (possibly erroneously) that with
SystemVeilog, the assertions are more comprehensive & simpler to
apply.

I am not sure about more comprehensive but given that they are part of the
language you might be right with respect to applying them. However, as you
probably agree, adding PSL statements in comments (or link in a vunit) is
not such a big issue. In VHDL2007/8 comments are no longer required for PSL
and if I understand the P1076 reference manual correctly vunits can be used
as packages.

I realise that SV is a language & not a methodology; and there seems a
general consensus here that SV will "win" over SystemC;
although that could be rubbish.

I think that is indeed rubbish since we are not talking about HD-DVD versus
Blu-Ray, SV and SC have non-overlapping capabilities. SV is closer to the
hardware has build in assertions and is more capable in functional
verification (functional coverage is much easier in SV than SC) to name a
few. SystemC on the other hand is more capable in terms of high-level
modelling (better OO support), so if you want to model a complete SoC
including say an Operating System you would pick SystemC over SystemVerilog.

We want to address our verification methodology to make it more
thorough & hopefully simpler, albeit having to learn SV on top of
VHDL. (Why no SystemVHDL?)

It is always good to learn another language so your effort on SV will not be
wasted, just make sure you don't throw out the baby with the bathwater

Hans
www.ht-lab.com

Niv.

 

[KJ]

"Mike Treseler" <mike_treseler@comcast.net> wrote in message
news:66mpo7F2ka8d1U1@mid.individual.net...

Tricky wrote:


the DC fifo is a very reliable way of
passing data across clock domains, and is a lot safer than double
registering.

I don't agree.

The LPM_FIFO_DC (dual-clock)
has asynchronous priority resolution.
WRCLOCK has 'priority' only as long as the two
rising edges stay away from each other.

Meaning that lpm_fifo_dc will (or could) misfunction in what way? Ignore a
write? Something else?

Kevin Jennings

 

[KJ]

"Mike Treseler" <mike_treseler@comcast.net> wrote in message
news:66mpo7F2ka8d1U1@mid.individual.net...

Tricky wrote:


the DC fifo is a very reliable way of
passing data across clock domains, and is a lot safer than double
registering.

I don't agree.

The LPM_FIFO_DC (dual-clock)
has asynchronous priority resolution.
WRCLOCK has 'priority' only as long as the two
rising edges stay away from each other.

Meaning that lpm_fifo_dc will (or could) misfunction in what way? Ignore a
write? Something else?

Kevin Jennings

 

[HT-Lab]

"Peter Glar" <Peter@yahoo.com> wrote in message
news:fusklp$o1q$1@aioe.org...

Hi

I am currently looking for a basic MIPS implementation in VHDL.
I have found some in Verilog on opencores.com but not really in VHDL.

Anyone has a good source for that?

Cheers,
Peter

mmmm, first hit in google using mips+vhdl gives me:

http://www.ewh.ieee.org/soc/es/Nov1997/01/INDEX.HTM

and there seem to be many more....

Hans
www.ht-lab.com

 

[Symon]

KJ wrote:

On Apr 25, 8:10 am, vhdl_danne <dan...@reidal.com> wrote:
Hi! I need to implement this in VHDL:

result=2.2*(time/timeTot-0.5)

time/timeTot is a duty cycle of a pwm signal and will always be less
than zero

Is there any simple solution for this?

Cheers! DR

What is the problem that you would like a simple solution for?

KJ

He says less than zero, so maybe negative time is his problem?

Syms.

 

[Symon]

Mike Treseler wrote:

beky4kr@gmail.com wrote:


http://bknpk.no-ip.biz/divide_by_constnat/divide_by_constant.html


Nice verilog sim example.
Thanks.

-- Mike Treseler

vlog db7.v db7_tb.v
vsim -c db7_tb -do "run -all;exit"

# Loading work.db7_tb
# Loading work.db7
# run -all
# 7 1 00000000111 00000000001 1
# 14 2 00000001110 00000000010 1
# 21 3 00000010101 00000000011 1
# 28 4 00000011100 00000000100 1
# 35 5 00000100011 00000000101 1
# 42 6 00000101010 00000000110 1
# 49 7 00000110001 00000000111 1

Is it 18?

Syms.

 

[Symon]

Daniel Reidal wrote:

calculate the sense current. My problem is I don't know how to handle
decimal numbers in an easy way. I have only used integers (signed and
unsigned) in my designs.
Thanks Daniel

http://en.wikipedia.org/wiki/Binary_point
....and just in case...
http://en.wikipedia.org/wiki/Twos_complement

 

[Symon]

Daniel Reidal wrote:

calculate the sense current. My problem is I don't know how to handle
decimal numbers in an easy way. I have only used integers (signed and
unsigned) in my designs.
Thanks Daniel

http://en.wikipedia.org/wiki/Binary_point
....and just in case...
http://en.wikipedia.org/wiki/Twos_complement

 

[KJ]

"Daniel Reidal" <info@omnisys.se> wrote in message
news:fv3qnb$ep7$1@aioe.org...

Mike Treseler wrote:
vhdl_danne wrote:
I need to implement this in VHDL:
result=2.2*(time/timeTot-0.5)
time/timeTot is a duty cycle of a pwm signal and will always be less
than zero
Maybe you mean less than one.
Is there any simple solution for this?

Any numeric solution for synthesis
starts with binary math.
1. Read this
http://www.emu8086.com/assembly_language_tutorial_assembler_reference/numbering_systems_tutorial.html
or this
http://deadsmall.com/3J3
2. Get python
http://www.python.org/download/
3. Do the math:

Let's say we have an 8 bit pwm.
57 /evtfs/home/tres> python
2**8
256
hex(256)
'0x100'
__________
Since our pwm is only 8 bits,
that '1' msb represents the counter carry out
for the FF to 00 rollover.
Now to 'fractions'.

A 25% pulse width would correspond to a count of
0.25 * 128
32.0
hex(32)
'0x20'

A pulse, wider by a factor of 2.2
would correspond to a count of
2.2 * 32
70.4
int(70.4)
70
int(70.4 + 0.5)
70
hex(70)
'0x46'

and so it goes.

-- Mike Treseler


Thanks. My problem is like this. I have a Current sense circuit that will
generate a PWM signal that I have to monitor. The frequency of the pwm
waveform will not be constant (because of temperature variations). So my
idea is to count BOTH pulse width and frequency of the signal to determine
the duty cycle. I'm using the formula to calculate the sense current. My
problem is I don't know how to handle decimal numbers in an easy way. I
have only used integers (signed and unsigned) in my designs.

Daniel,

You're still leaving much to the imagination by not describing what you're
really after, but at least now you've added some detail. You can simply
count high time and low time of the PWM signal and you'll have all the
information you'll need about the signal, so why do you think you need to
know duty cycle?

If you have a microprocessor in your system anywhere it could easily take
the easily measurable high time and low time numbers and from that compute
the duty cycle. If not and you have an actual need for duty cycle then it
will be of the form:

DC = High time / (High time + Low time)

This 'can' be implemented in VHDL if you want, you'll likely want to scale
the numbers by some factor so that DC is in some integer range instead of 0
to 1.

Kevin Jennings

 

[KJ]

"Daniel Reidal" <info@omnisys.se> wrote in message
news:fv3qnb$ep7$1@aioe.org...

Mike Treseler wrote:
vhdl_danne wrote:
I need to implement this in VHDL:
result=2.2*(time/timeTot-0.5)
time/timeTot is a duty cycle of a pwm signal and will always be less
than zero
Maybe you mean less than one.
Is there any simple solution for this?

Any numeric solution for synthesis
starts with binary math.
1. Read this
http://www.emu8086.com/assembly_language_tutorial_assembler_reference/numbering_systems_tutorial.html
or this
http://deadsmall.com/3J3
2. Get python
http://www.python.org/download/
3. Do the math:

Let's say we have an 8 bit pwm.
57 /evtfs/home/tres> python
2**8
256
hex(256)
'0x100'
__________
Since our pwm is only 8 bits,
that '1' msb represents the counter carry out
for the FF to 00 rollover.
Now to 'fractions'.

A 25% pulse width would correspond to a count of
0.25 * 128
32.0
hex(32)
'0x20'

A pulse, wider by a factor of 2.2
would correspond to a count of
2.2 * 32
70.4
int(70.4)
70
int(70.4 + 0.5)
70
hex(70)
'0x46'

and so it goes.

-- Mike Treseler


Thanks. My problem is like this. I have a Current sense circuit that will
generate a PWM signal that I have to monitor. The frequency of the pwm
waveform will not be constant (because of temperature variations). So my
idea is to count BOTH pulse width and frequency of the signal to determine
the duty cycle. I'm using the formula to calculate the sense current. My
problem is I don't know how to handle decimal numbers in an easy way. I
have only used integers (signed and unsigned) in my designs.

Daniel,

You're still leaving much to the imagination by not describing what you're
really after, but at least now you've added some detail. You can simply
count high time and low time of the PWM signal and you'll have all the
information you'll need about the signal, so why do you think you need to
know duty cycle?

If you have a microprocessor in your system anywhere it could easily take
the easily measurable high time and low time numbers and from that compute
the duty cycle. If not and you have an actual need for duty cycle then it
will be of the form:

DC = High time / (High time + Low time)

This 'can' be implemented in VHDL if you want, you'll likely want to scale
the numbers by some factor so that DC is in some integer range instead of 0
to 1.

Kevin Jennings

 

[jtw]

I'm sure he is talking about the digital portion, as in ... there are many
codecs available for Windows. Reference http://en.wikipedia.org/wiki/Codec.

JTW

<ghelbig@lycos.com> wrote in message
news:48f49310-844a-4101-954a-a4a4c3d2ad77@u36g2000prf.googlegroups.com...
On Apr 29, 12:43 pm, HansWernerMarsc...@web.de wrote:

The Subject says it all. I´m looking for learning examples mainly
signal processing. Voice or audio is also a good thing for
demonstrations. Maybe it is not so hard to proof. If something is
going wrong you hear it.

While there are advances in "analog" VHDL, I don't know of any D/A
implementations in VHDL.

If what you're really looking for is VHDL for the interface to a
CODEC, then Google for whatever interface your CODEC has (I2S is a
common one).

G.

 

[KJ]

"pallav" <pallavgupta@gmail.com> wrote in message
news:689c3a86-d13c-4f42-be48-47c8f2b7bb13@26g2000hsk.googlegroups.com...

Hi,

I'm writing a small tutorial for functional simulation/testbench in
VHDL. My code is show below. I instantiate the UUT as follows:

UUT: NAND2 port map(a_t => a, b_t => b, y_t => y);

I use GHDL (a free VHDL compiler) to compile by saying "ghdl -a
nand2.vhd". I get the following error message:
nand2.vhd:88:32: no declaration for "a"
nand2.vhd:88:42: no declaration for "b"
nand2.vhd:88:52: no declaration for "y"

However, if I change the above line to
UUT: NAND2 port map(a_t, b_t, y_t);

it compiles fine. Is this a synthesizer issue or has the VHDL standard
changed?

Neither. The port names are 'a', 'b, and 'y' and it appears your signals
have the '_t' suffix, which means that you should've instantiated it as

UUT: NAND2 port map(a=> a_t , b=> b_t , y=> y_t);

Since named association is optional (but generally recommended, you can not
include the port names in which case the assignments are by position which
is why the following worked for you.

UUT: NAND2 port map(a_t, b_t, y_t);

Kevin Jennings

 

[David Spencer]

"Thomas" <thomas.b36@gmail.com> wrote in message
news:5bde9bf2-ff64-4ca3-9d23-0fb2d85724e0@z72g2000hsb.googlegroups.com...

Hi all,

I need to design (VHDL) a I2C bus multiplexer to control 4 clock I2C
slave devices that have the same slave address. My CPLD receives an on-
board I2C bus and needs to route it to 4 I2C devices thru an I2C mux
depending on the slave that i need to configure. No matter what I've
tryed, it doesn't work....

Any help/idea?

Thank you.

My design looklike:

entity I2c_Bus_Mux is
port( onboard_i2c_SCL : inout std_logic;
onboard_i2c_SDA : inout std_logic;
control_vector : in std_logic_vector(1 downto 0);
Slave0_SCL : inout std_logic;
Slave0_SDA : inout std_logic;
Slave1_SCL : inout std_logic;
Slave2_SDA : inout std_logic
---------------------etc-------------------);
end I2c_Bus_Mux;


process (----sensitivity list containing all involved signals)
begin
case control_vector is
when "00" =
Slave0_SCL <= onboard_i2c_SCL ;
Slave0_SDA <= onboard_i2c_SDA;
onboard_i2c_SCL <= Slave0_SCL;
onboard_i2c_SDA <= Slave0_SDA;
when "01" =
.......etc.....

The problem is that I2C signals (SCL and SDA) are bidirectional, which makes
any form of I2C repeater/switch within an FPGA very hard to implement.
Assuming that you only have a single I2C master then you don't need to worry
about arbitration and you may be able to make it work with some careful
thinking, but it is non-trivial.

An easier solution is to implement an I2C device within your FPGA to act as
a control register for an external analog mux (Quickswitch type thing).
Alternative, just buy an I2C mux from NXP (Philips as was), which will do
the job for you.

 

[David Spencer]

"Thomas" <thomas.b36@gmail.com> wrote in message
news:5bde9bf2-ff64-4ca3-9d23-0fb2d85724e0@z72g2000hsb.googlegroups.com...

Hi all,

I need to design (VHDL) a I2C bus multiplexer to control 4 clock I2C
slave devices that have the same slave address. My CPLD receives an on-
board I2C bus and needs to route it to 4 I2C devices thru an I2C mux
depending on the slave that i need to configure. No matter what I've
tryed, it doesn't work....

Any help/idea?

Thank you.

My design looklike:

entity I2c_Bus_Mux is
port( onboard_i2c_SCL : inout std_logic;
onboard_i2c_SDA : inout std_logic;
control_vector : in std_logic_vector(1 downto 0);
Slave0_SCL : inout std_logic;
Slave0_SDA : inout std_logic;
Slave1_SCL : inout std_logic;
Slave2_SDA : inout std_logic
---------------------etc-------------------);
end I2c_Bus_Mux;


process (----sensitivity list containing all involved signals)
begin
case control_vector is
when "00" =
Slave0_SCL <= onboard_i2c_SCL ;
Slave0_SDA <= onboard_i2c_SDA;
onboard_i2c_SCL <= Slave0_SCL;
onboard_i2c_SDA <= Slave0_SDA;
when "01" =
.......etc.....

The problem is that I2C signals (SCL and SDA) are bidirectional, which makes
any form of I2C repeater/switch within an FPGA very hard to implement.
Assuming that you only have a single I2C master then you don't need to worry
about arbitration and you may be able to make it work with some careful
thinking, but it is non-trivial.

An easier solution is to implement an I2C device within your FPGA to act as
a control register for an external analog mux (Quickswitch type thing).
Alternative, just buy an I2C mux from NXP (Philips as was), which will do
the job for you.

 

[Brad Smallridge]

You should be able switch your signals, if you can
get at the IOs before they are combined into inouts.
Can you do that? Or is there some sort of proprietary
code problem?

What tools are you using and what is your target CPLD?

Brad Smallridge
AiVision

 

[Brad Smallridge]

You should be able switch your signals, if you can
get at the IOs before they are combined into inouts.
Can you do that? Or is there some sort of proprietary
code problem?

What tools are you using and what is your target CPLD?

Brad Smallridge
AiVision

 

[David Spencer]

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:JPGTj.9447$sd4.8499@fe109.usenetserver.com...

You should be able switch your signals, if you can
get at the IOs before they are combined into inouts.
Can you do that? Or is there some sort of proprietary
code problem?

What tools are you using and what is your target CPLD?

Brad Smallridge
AiVision

The problem is that I2C signals are open-drain and inherently bidirectional.
Any sort of I2C buffering or switching requires a low-level on either side
to be propagated to the other side. This is virtually impossible to do in a
100% digital device since either or both sides can pull the signal low at
any time.

 

[David Spencer]

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:JPGTj.9447$sd4.8499@fe109.usenetserver.com...

You should be able switch your signals, if you can
get at the IOs before they are combined into inouts.
Can you do that? Or is there some sort of proprietary
code problem?

What tools are you using and what is your target CPLD?

Brad Smallridge
AiVision

The problem is that I2C signals are open-drain and inherently bidirectional.
Any sort of I2C buffering or switching requires a low-level on either side
to be propagated to the other side. This is virtually impossible to do in a
100% digital device since either or both sides can pull the signal low at
any time.