Clock Edge notation

[Thomas Stanka]

nfirtaps schrieb:

I am a little unclear that clk2 could have the problem here since it
only starts the clk1 process. The clk1 process then stops itself after
writing 1024 bytes. Could you please explain a little more what you
mean? It seems to me as clk2 can start the clk1 process anytime an no
synchronizing problems would occur, because the clk1 process stops
itself.

The sendbit changes its value depending on the rising edge of clk2.
Inside your fpga, you need more than one FF to build your counter.
Delay differences between the clk2 and all FF in Clk1 will lead to
situations, where some FF of your counter see your statbit from clk2 is
'0' and other see it is '1'.

bye Thomas

 

[nfirtaps]

Just realized I posted my vhdl code twice, and forgot to put my
testbench. Here it is:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
USE ieee.numeric_std.ALL;
use std.textio.all;

ENTITY usbbackend_testbench IS
END usbbackend_testbench;

ARCHITECTURE behavior OF usbbackend_testbench IS

-- Component Declaration
COMPONENT usb_backend
Port (
-- Inputs/Outputs for FX2
usb_ifclk : in STD_LOGIC;
usb_slwr : out STD_LOGIC;
usb_fd : out STD_LOGIC_VECTOR(15 downto 0);
usb_ep6ff : in STD_LOGIC;
usb_ep6ef : in std_logic;
-- Inputs from Down Converter Logic
ddc_clk : in std_logic;
ddc_data : in std_logic_vector(15 downto 0);
reset : in std_logic
);
end component;

signal usb_ifclk_w : std_logic;
signal usb_ep6ff_w : std_logic := '0';
signal usb_ep6ef_w : std_logic := '1';
signal ddc_clk_w : std_logic;
signal ddc_data_w : std_logic_vector(15 downto 0) :=
"0000000000000000";
signal usb_slwr_w : std_logic := '0';
signal usb_fd_w : std_logic_vector(15 downto 0);
signal reset_w : std_logic := '1';

file InFile : TEXT is in "simdatain.txt";
file OutFile : TEXT is out "simdataout.txt";
BEGIN

uut: usb_backend PORT MAP(
usb_ifclk => usb_ifclk_w,
usb_slwr => usb_slwr_w,
usb_fd => usb_fd_w,
usb_ep6ff => usb_ep6ff_w,
usb_ep6ef => usb_ep6ef_w,
ddc_clk => ddc_clk_w,
ddc_data => ddc_data_w,
reset => reset_w
);

process
begin
usb_ifclk_w <= '1';
wait for 10.5 ns;
usb_ifclk_w <= '0';
wait for 10.5 ns;
end process;

process
begin
ddc_clk_w <= '1';
wait for 50 ns;
ddc_clk_w <= '0';
wait for 50 ns;
end process;

process(usb_slwr_w)
begin
if (usb_slwr_w'event and usb_slwr_w = '1') then
usb_ep6ef_w <= '0' after 23 ns;
end if;
if (usb_slwr_w'event and usb_slwr_w = '0') then
usb_ep6ef_w <= '1' after 100ns;
end if;
end process;

-- Test Bench Statements
tb : PROCESS
BEGIN

wait for 100 ns; -- wait until global set/reset completes

reset_w <= '1';

wait for 100 ns;
reset_w <= '0';

wait; -- will wait forever
END PROCESS tb;
-- End Test Bench

END;

 

[Paul Uiterlinden]

Ted wrote:

I have a test bench in which the input stimulus file length is
unknown.
I would like to read the file in to my test bench and loop through
each element of the stimulus every clock. The only problem is the
the
upper limit of the loop is unknown. I created the following to find
the file length (number of elements) and use that length as the
upper limit of a loop used to read the file into an array which is
based off of that length.

You cannot do that. The upper and lower limits in an array (type)
declaration must be static. The value of a signal is not static.

If you absolutely must store the contents of the file and have that
accessible in your testbench, you must create a linked list. It
consist of dynamically allocated objects, by using access types and
the NEW operator. See for example:
http://www.emba.uvm.edu/~jswift/uvm_class/notes/access.html

Another way would just to create an array that is large enough to hold
the largest expected file. But that is rightout ugly.

But why reading in the file first and then use the contents? If you
just need a new vector each clock, why not read a line each clock and
use that vector?

Yet another approach: don't use a file at all. Declare a constant
array with your vectors.

--
Paul.
www.aimcom.nl
email address: switch x and s

 

[Mark McDougall]

Ben Jones wrote:

Duh, I see. Has anyone ever, ever put the MSB on the right?

Yes!

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[Ben Jones]

"Mark McDougall" <markm@vl.com.au> wrote in message
news:457756be$0$28967$5a62ac22@per-qv1-newsreader-01.iinet.net.au...

Ben Jones wrote:

Duh, I see. Has anyone ever, ever put the MSB on the right?
Yes!

Anyone else? So far that is 1000000000 people I know of.

-Ben-

 

[Dave Pollum]

Matt Clement wrote:

Thanks Ben for your response

You are correct the ADD was supposed to be Reset but even then, the process
is only started on a clock cycle or a change on reset. I dont have a way of
changing the reset value. I was using the reset as an INOUT so that I
could change it within the system rather than externally. I just tried
making a seperate process that uses a wait statement like below to try and
set the LED1 outputs and it gives an error that it creates constant drivers
for net LED1.

process
begin
wait until reset = '0';
led1<="11111111111111111111111111111111";
reset<='1';
end process;



"Ben Jones" <ben.jones@xilinx.com> wrote in message
news:el6h9c$dbt3@cnn.xsj.xilinx.com...
Hi Matt,

"Matt Clement" <clement@nanotechsys.com> wrote in message
news:Iwzdh.1053$4p2.521@trndny07...
Hey Guys/Gals,

I have a design that needs 32 outputs to be started or asynchronously set
to high right after power up. I also have two clocked state machine
processes which run and act on those 32 outputs. I have tried just about
everything I can think of to get it to work. The closest I got was going
to a dummy state initially and setting them to high, but this of course
requires a clock prior to setting them high. I would like to set them
high without having to wait for a clock pulse.

PROCESS (clk, ADD)
VARIABLE DATA : STD_LOGIC_VECTOR(32 DOWNTO 0); --was 35
BEGIN
IF (RESET = '0') THEN --also tried IF (STATE = S37) THEN
LED1<="11111111111111111111111111111111";
--STATE<=IDLE;

Ugh, too loud.

Your main problem is that the process isn't sensitive to the reset signal,
so it doesn't see its value until ADD or CLK changes. What you probably
meant was

process(clk, reset)
variable data : std_logic_vector(32 downto 0);
begin
if reset = '0' then
led1 <= (others => '1');
elsif rising_edge(clock) then
case state is
when idle =
...
end case;
end if;
end process;

I don't see why it should need to be sensitive to ADD either.

Cheers,

-Ben-

Matt;

Where does the reset signal come from? I've used reset chips (i.e.TI's
TLC7705) to reset CPLD logic. The '7705 generates a reset output on
power-up and also has an input for a reset push button switch. Also,
do you have code that forces your state machine into an initial state?
-Dave Pollum

 

[homoalteraiensis]

I remember a hint in mento's spec, that more than one waveform windows
is not available for the budget versions of modelsim

 

[Kai Harrekilde-Petersen]

moogyd@yahoo.co.uk writes:

Hi,

(Off-topic, Cross-posted to comp.lang.vhdl and comp.lang.verilog)

I'd say this is at least semi-on-topic.

I am looking to put an open-source bug/issue tracking system in place
for our current project (eventually expanded for all projects), and
would appreciate any experiences/comments/suggestions.

Consider carefully whether you expect to develop IP cores that are
going to be used in multiple chips. If you do, consider using a tool
where you can have a hierarchy of issue groups, so that you can
submit, track, and close independently an issue with IP block <foo> in
multiple chips at the same time.

I have used Gnats in a previous job, and we had to break our own and
gnats' back to get this to "work" (much manual work in selection,
copying, and tracking of the original issue was needed).

Now imagine that you have ~5 basic IP blocks and 3 different chip
architectures, which were reused across 15-20 tapeouts within 5-6
years and you are starting to get a LOT manual checking and
crosschecking between issues in different chips to figure out whether
a particular issue really applies to what you're taping out.


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>

 

[Kai Harrekilde-Petersen]

moogyd@yahoo.co.uk writes:

Kai Harrekilde-Petersen wrote:
moogyd@yahoo.co.uk writes:
I am looking to put an open-source bug/issue tracking system in place
for our current project (eventually expanded for all projects), and
would appreciate any experiences/comments/suggestions.

Consider carefully whether you expect to develop IP cores that are
going to be used in multiple chips. If you do, consider using a tool
where you can have a hierarchy of issue groups, so that you can
submit, track, and close independently an issue with IP block <foo> in
multiple chips at the same time.

We do have IP's that are used in multiple chips, and so this will be in
issue.
It sounds llike it is not easy to do with Gnats. Are you aware of a
tool that handles it better?

Alas, I am not aware of a tool that does this (but I haven't looked
for it either). However, it should be relatively straight-forward to
design and implement.


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>

 

[Thomas Stanka]

Mike Treseler schrieb:

ec wrote:

What if after Place and Route the timing constarint are lower then needed ,
what should be done ?

First you should analyse the longest paths to have an idea why your
design miss your contraints. This could help you a lot in deceiding
what to do next.

Your choices are
1. Reduce the clock frequency.
2. Pipeline the design.
3. Use a faster device.

2a) instead of real pipelining it is often possible to gain speed by
simple changes of your HW structure (eg. change state encoding, use
resource doubbling to improve timing, use downto-0 counter or lfsr
instead of up-to-constant counter,...). For complex fsm you _could_
gain a lot with major reworking if your first fsm design leads to high
fanout nets.

4. for slight violations you could
a) change the P&R until it fits (preplacing by hand can help a lot,
but don't expect miracles)
b) change the environmetal parameters if applicabel (e.g if your
voltage is in every case much better than worst case, you could
increase voltage for worst case timing analyses (if your tool allows to
do so))

5. rerun synthesis with other timing constraints (can help in _some_
cases, sometimes you can gain even with loose contraints)

6. Flatten Netlist, if it is still hierachically and your tool has some
weaknesses on module bounds.

4 -6 can do for up to ~30% depending on your design. If you want 100Mhz
and even miss 50 Mhz you typically need to use choices 1-3.

bye Thomas

 

[ec]

Thanks
ec

"Mike Treseler" <mike_treseler@comcast.net> ???
??????:4vvp1vF1e5ja0U1@mid.individual.net...

ec wrote:

What if after Place and Route the timing constarint are lower then needed
,
what should be done ?

Your choices are
1. Reduce the clock frequency.
2. Pipeline the design.
3. Use a faster device.

-- Mike Treseler

 

[Jonathan Bromley]

On 4 Jan 2007 07:14:21 -0800, "Tim Verstraete"
<tim.verstraete@barco.com> wrote:

[Also posted to comp.lang.vhdl]

ok, your right, now i know why it works on this code and not mine, in
the template i used the following libraries:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

and in mine i used

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

And that is PRECISELY why I keep banging on about why
STD_LOGIC_(UN)SIGNED is such a very, very bad thing.

If you had used only STD_LOGIC_ARITH or (better)
NUMERIC_STD, then you would have been forced into
declaring the objects as SIGNED or UNSIGNED, and you
would know what you were doing. Having an arbitrary
numeric representation imposed on std_logic_vector
by a use clause is IMO certifiably insane.

Thanks for providing more ammunition for my rant
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Mike Treseler]

Jonathan Bromley wrote:

On 4 Jan 2007 07:14:21 -0800, "Tim Verstraete"
tim.verstraete@barco.com> wrote:

[Also posted to comp.lang.vhdl]

ok, your right, now i know why it works on this code and not mine, in
the template i used the following libraries:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

and in mine i used

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

And that is PRECISELY why I keep banging on about why
STD_LOGIC_(UN)SIGNED is such a very, very bad thing.

If you had used only STD_LOGIC_ARITH or (better)
NUMERIC_STD, then you would have been forced into
declaring the objects as SIGNED or UNSIGNED, and you
would know what you were doing. Having an arbitrary
numeric representation imposed on std_logic_vector
by a use clause is IMO certifiably insane.

Thanks for providing more ammunition for my rant

These newsgroups provide plenty
of this sort of ammunition.
The source, it seems to me,
is the training examples and
editor templates from brand X and brand S.

The result is that most designers of
VHDL synthesis code are convinced that
using signed and unsigned types is a waste of time,
and that only "purists" think otherwise.

This state of affairs is only a problem
for me when I use or supply entities to
other designers. My workaround in this case
is to declare [un]signed variables for use
in my entity and implicit type conversion
for port input and output assignments
from the omnipresent std_logic_vector type.

-- Mike Treseler

 

[Brian Drummond]

On Fri, 05 Jan 2007 12:22:29 -0800, Mike Treseler
<mike_treseler@comcast.net> wrote:

Jonathan Bromley wrote:
On 4 Jan 2007 07:14:21 -0800, "Tim Verstraete"
tim.verstraete@barco.com> wrote:

[Also posted to comp.lang.vhdl]

ok, your right, now i know why it works on this code and not mine, in
the template i used the following libraries:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

Thanks for providing more ammunition for my rant

These newsgroups provide plenty
of this sort of ammunition.
The source, it seems to me,
is the training examples and
editor templates from brand X and brand S.

Indeed. Furthermore, at least half the time, having included the
std_logic_arith type libraries, the code doesn't ever use them!

It is normal practice for me to comment out these "use" clauses;
normally the code just compiles without them, and I have one less thing
to worry about. (In the rare examples that actually use them, it's not
usually difficult to make them numeric_std clean, though I don't always
bother)

- Brian

 

[yttrium]

i have to admit at first i was not really convinced but by writing more
and more DSP related VHDL where i need signed/unsigned values i am
learning a lot of the inefficiency of certain libraries and packages ...

Mike Treseler wrote:

Jonathan Bromley wrote:
On 4 Jan 2007 07:14:21 -0800, "Tim Verstraete"
tim.verstraete@barco.com> wrote:

[Also posted to comp.lang.vhdl]

ok, your right, now i know why it works on this code and not mine, in
the template i used the following libraries:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

and in mine i used

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
And that is PRECISELY why I keep banging on about why
STD_LOGIC_(UN)SIGNED is such a very, very bad thing.

If you had used only STD_LOGIC_ARITH or (better)
NUMERIC_STD, then you would have been forced into
declaring the objects as SIGNED or UNSIGNED, and you
would know what you were doing. Having an arbitrary
numeric representation imposed on std_logic_vector
by a use clause is IMO certifiably insane.

Thanks for providing more ammunition for my rant

These newsgroups provide plenty
of this sort of ammunition.
The source, it seems to me,
is the training examples and
editor templates from brand X and brand S.

The result is that most designers of
VHDL synthesis code are convinced that
using signed and unsigned types is a waste of time,
and that only "purists" think otherwise.

This state of affairs is only a problem
for me when I use or supply entities to
other designers. My workaround in this case
is to declare [un]signed variables for use
in my entity and implicit type conversion
for port input and output assignments
from the omnipresent std_logic_vector type.

-- Mike Treseler

 

[Ray Andraka]

yttrium wrote:

i have to admit at first i was not really convinced but by writing more
and more DSP related VHDL where i need signed/unsigned values i am
learning a lot of the inefficiency of certain libraries and packages ...

By the same token, if you do a lot of DSP, you'll soon learn to
appreciate the strong typing in VHDL as compared to verilog, and may
even grow to despise the permissiveness (and ambiguity) of verilog.

FWIW, I code my VHDL components with std_logic and std_logic_vector on
the I/O in order to be consistent with existing libraries. I convert
the signals to signed/unsigned inside the architecture as needed. Some
of my components have a boolean generic, "is_signed" to specify the
behavior as an option.

 

[Andy Peters]

Ivangray wrote:

Hi,
I'm a new user for work with a fpga components, I use ACTEL Fusion
Starter KIT.
I dont understand why this code dont work in SynaptiCAD when compile
follow code :

What do you mean by "dont (sic) work"?

-- mytimer.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
^^^^^^^^^^^^^^^^

This might be your problem. maybe. But "dont work" isn't a reasonable
description of what's going on.
- a

 

[Mike Treseler]

chibiks@googlemail.com wrote:

Can anyone give me some pseudocode or VHDL code on how to implement
dataforwarding using a 2:1 multiplexer for an ALU in a simple 32-bit
microprocessor.

If you have the ALU code,
adding a mux is a one-liner.

-- Mike Treseler

 

[Al]

ALuPin wrote:

If I write the following command in my macro I do not get a wave of
this signal
"add wave sim:/tb_packetfile_ctrl/u1/last_block"

try:

add wave sim:/tb_packetfile_ctrl/u1/*

or from the gui:

view,structure,right-click on u1, add, add to wave

If that doesn't do it, the signal is not there.

MACRO:
cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim
vlib modelsim_work
vmap work modelsim_work
vsim -sdftyp /U1=packetfile_ctrl_vhd.sdo work.TB_PACKETFILE_CTRL

Wait a minute. You are siming a netlist, not source code.
This may be the reason last_block is gone.
Compile the source files and try
vsim TB_PACKETFILE_CTRL

-- Mike Treseler

In old archives I found this thread, started from ALuPin.
I think I have the same problem when trying to "add wave" internal
signals with ModelSim. Going through several trials it looks like is not
possible to add wave of a netlist, unless is a port of the hierarchy.
But then I realized there is a -internal option I assumed was for this
purpose, but it didn't work at all, or at least I didn't manage to make
it work.

Then if I go to the Workspace and look for the signals, I find some of
them are shown in one way some others in another:

\mysignal1\
mysignal2

When I type:

add wave /mytest/dut/mysignal2

nothing happens. But if I do write

add wave /mytest/dut/mysignal2/q

the q of the flip-flop is shown on the wave. This is based (i think) on
the fact that can be shown only component's port of a netlist (is that
right?).
The same approach doesn't work for mysignal1, because of these backslash
that i do not understand. It looks like the backslash are inserted on
vectors, but I'm not pretty sure, then if I browse for the vector in the
workspace I find something like this:

\vector[0]\
\vector[1]\
\vector[2]\
\vector[3]\
..
..
..

but how can I add them to the wave from command line? using wildcards do
not help. This is my trials log, where count1_in is a std_logic_vector
(7 downto 0):


add wave -internal /test_counter/dut/count1_in/q
# (vish-4014) No objects found matching '/test_counter/dut/count1_in/q'.
add wave -internal /test_counter/dut/count1_in*/q
# (vish-4014) No objects found matching '/test_counter/dut/count1_in*/q'.
add wave -internal /test_counter/dut/\count1_in*\/q
# (vish-4014) No objects found matching '/test_counter/dut/count1_in*/q'.
add wave -internal /test_counter/dut/\count1_in[0]\/q
# invalid command name "0"

Moreover the option -internal looks to seem useless.
Any suggestions?

Thanks a lot

Al


--
Alessandro Basili
CERN, PH/UGC
Hardware Designer

 

[Mike Treseler]

Al wrote:

In old archives I found this thread, started from ALuPin.
I think I have the same problem when trying to "add wave" internal
signals with ModelSim.
Any suggestions?

Maybe you didn't try this.
add wave -r /*

-- Mike Treseler