Clock Edge notation

[Mike Treseler]

paddy3118@netscape.net wrote:

Does anyone write 'generatable IP' e.g. n-bit UARTS then verify the
UART for small values of n; but more thoroughly, then instantiate a
version of the IP with a much larger version of n?

The reference design here:
http://home.comcast.net/~mike_treseler/
just happens to be uart with character length
set by the generic constant char_len_c.

See also the procedural component RETIME in the same file.

-- Mike Treseler

 

[Mike Treseler]

paddy3118@netscape.net wrote:

Mike,
To verify your block using my methodology, I would change your
testbench test_uart.vhd to bring the generic char_len_c to its top,

The testbench generics are defaulted,
but you could easily map them per
the design generic map.

I would then define functional coverage
points and try and achieve a very high functional coverage but with say
a char_len_c of 2 or 1. The big question would then be if high
functional coverage of the smaller design would equate to high
'quality' of any generatable variant, or not.

Have at it. Let us know what you find.

-- Mike Treseler

 

Try not to cross post. This isnt anything to do with VHDL

 

[jens]

Use a clock and a counter. Then the accuracy of the delay is based on
clock accuracy and not analog component tolerances.

 

[Ashu]

Hi,
Firstly whatever your design is you need to make you want it to go high
and detected by logic when it increases above voltage say 'v' else it
will go high when it reaches VIH of the IC(cpld or Xorr IC whichever u
use).
If these two devices are using diff technologies their VIH values will
differ.

If this is not a problem then to create a delay u can use a multiple
flipflop stages and provide them appropriate clock.
A simple shift register will also do.



Sarah wrote:

I want to use the output of a R-C integrator as a delayed input to CPLD

(inside there is a XOR gate and counter logic). It worked OK when I use

discrete XOR IC 4070. But for same R-C values it doesn't works with
CPLD.
Is is due to the fact that analog input (sawtooth from integrator) has
given to CPLD?
Is comparator after integrator is one of the solution?
Suggest other methods for creating delays inside CPLD. That will
elliminate need of integrator. Here delay required is 1.1us.

 

[Klaus Falser]

In article <du42f3$1o81@cliff.xsj.xilinx.com>, ben.jones@xilinx.com
says...

....

You should be able to write this as follows and get the behaviour you want:

process(clk,reset)
begin
if rising_edge(clk) then
addr <= tmp;
end if;

if reset = '0' then
tmp <= (others => '0');
elsif falling_edge(clk) then
tmp <= "0000" & data;
end if;
end process;

This is a single process, describing what I think you mean by "an
interconnect with two FFs". It is not unusual for a VHDL process to
represent many, many interconnected registers. If one had to write a
separate process for every flip-flop in a design, it would get very verbose
indeed! It's just unusual to have both rising- and falling-edge registers in
the same process.

....

-Ben-

Is it not better to split this up into 2 processes?
For simulation this is certainly ok, but does it fit the pattern a
compiler for synthesis needs to understand (accordingly to the IEEE
standard) ?

Klaus

 

[Mike Treseler]

Allan Herriman wrote:

So compile your RTL source then compile (*) and elaborate your
testbench. It will pick up the RTL version in the library.
Then compile your gate level source then compile and elaborate your
testbench. It will pick up the gate level version in the library.
Crude, but effective as long as you don't want to simulate your RTL
and gate level designs simultaneously.

After writing a generic rtl/gate testbench example, I must agree
that Allan's method is preferable.

The generic switch works ok, but it really makes
a mess of the testbench and causes annoying warnings about
the generated instances driving the same ports.
And flipping the switch requires either a command line
-G option or an edit of the constant assignment.

For me, a gate level sim is an exception rather than
the rule and it is not worth the impact to my standard
design flow to try and support it directly in the
testbench source. A little script using Allan's method
is probably the best way to go.

-- Mike Treseler

 

[Mike Treseler]

H aka N wrote:

I cannot use the vhdl-200x floating point and fixed point packages as I
am using XST and it (at least version 6.3) complains about negative
indexes, and there isn't much that can be done about it.

All the source code is there.
It is probably easier to rewrite the function with
natural indexes than it is to start from scratch.

Or try Quartus. It sticks to the standards better than XST.

Or start a case with Xilinx. Are you using the latest XST version?

-- Mike Treseler

 

[Dave Pollum]

Jan Behrend wrote:

Hello list,

the CY7C460A is an 8k deep, asynchronous FIFO :

ftp://ftp.mpifr-bonn.mpg.de:/outgoing/jbehrend/cy7c460a.pdf

What I want to do is to precisely keep track of the fill level. So I
need a counter which reacts to falling edges of two asynchronous signals
(/WR /RD).
This design is to be put into a Xilnix Coolrunner CPLD (Xpla3).

Has anyone done this before or can help how to go about this?

Cheers Jan Behrend

--
Jan Behrend
Max-Planck-Institut für Radioastronomie
Abteilung für Infrarot-Interferometrie Tel: (+49) 228 525 319
Auf dem Hügel 69 Fax: (+49) 228 525 411
D-53121 Bonn (Germany) jbehrend@mpifr-bonn.mpg.de
http://www.mpifr-bonn.mpg.de
PGP public key:
ftp://ftp.mpifr-bonn.mpg.de:/outgoing/jbehrend/jbehrend-gpg.asc

I've worked with a smaller async FIFO (Cypress CY7C425), and have found
the Full and Empty flags to be adequate for my needs. By counting the
/WR and /RD signals aren't you duplicating some of the FIFO's internal
logic? Perhaps doing the whole thing in an FPGA would fit your needs
better. I haven't graduated out of CPLDs yet, so I can't help you, but
there have been discussions of doing FIFOs in FPGAs in comp.arch.fpga
or comp.lang.vhdl.

-Dave Pollum

 

[Rafal Pietrak]

On Thu, 02 Mar 2006 04:35:25 -0800, Mike Treseler wrote:

I would start by describing the logic you really want.
I doubt that synthesis needs the hints.
Here's some related examples.

http://groups.google.com/groups?q=vhdl+treseler+resize+result_len

-- Mike Treseler

Thx, Not that all this is entirely obvious to me, now. But at least I have
something to focus on.

Thenx again,

-R

 

[Isaac Bosompem]

patrick.melet@dmradiocom.fr wrote:

hi everybody,

I would like to do a clock multiplcation.

My idea was to count how many samples I have in one period of the
original clock. Latch the last value of this counter : so I've got the
number of sample into one period of the clock.

Then I create a second counter which count toward the number of sample
compute last and now with this counter I can create a second clock.

CLK1 : 111111000000111111000000
counter 1 : 012345012345012345
Max counter : 5 5 5
counter 2 : 012345012345012345
CLK2: 111000111000111000

My VHDL is :

if top_baud='1' then
compteur_baud_max <= count_1;
count_1 <= 0;
else
count_1 <= count_1 + 1;
end if;

if count_2<compteur_bit_max then
count_2<= count_2+ 1;
else
count_2<= 0;
compteur_bit_max <= compteur_baud_max;
end if;


if (count_2 <= compteur_bit_max/4) or (count_2 > compteur_bit_max/2 and
count_2 <= 3*compteur_bit_max/4) then
clock_bit <= '1';
else
clock_bit <= '0';
end if;

My original clock1 has non constant period and the period varies....
So I've got problem in this clock generation

thanks if you have ideas

Why not use a clock manager in the FPGA to take care of the job? Or are
making one to be simulated not synthesized?

 

[Jan Behrend]

Dave Pollum wrote:

Jan Behrend wrote:

Hello list,

the CY7C460A is an 8k deep, asynchronous FIFO :

ftp://ftp.mpifr-bonn.mpg.de:/outgoing/jbehrend/cy7c460a.pdf

What I want to do is to precisely keep track of the fill level. So I
need a counter which reacts to falling edges of two asynchronous signals
(/WR /RD).
This design is to be put into a Xilnix Coolrunner CPLD (Xpla3).

Has anyone done this before or can help how to go about this?

Cheers Jan Behrend


I've worked with a smaller async FIFO (Cypress CY7C425), and have found
the Full and Empty flags to be adequate for my needs. By counting the
/WR and /RD signals aren't you duplicating some of the FIFO's internal
logic?
This is certainly true, so somebody HAS done it.

I need the exact fill level because I am sending packets over an
IEEE-1394 bus, and I want to adjust the packet size according to the
amount of available data. Another requirement is to completely empty
the FIFO once no more new data arrive. That's why the fill flags are to
coarse for my needs.

Perhaps doing the whole thing in an FPGA would fit your needs
better.
The hardware choice is already fixed.

I haven't graduated out of CPLDs yet, so I can't help you, but
there have been discussions of doing FIFOs in FPGAs in comp.arch.fpga
or comp.lang.vhdl.
Thanks for the pointer.

-Dave Pollum

--
Jan Behrend
Max-Planck-Institut für Radioastronomie
Abteilung für Infrarot-Interferometrie Tel: (+49) 228 525 319
Auf dem Hügel 69 Fax: (+49) 228 525 411
D-53121 Bonn (Germany) jbehrend@mpifr-bonn.mpg.de
http://www.mpifr-bonn.mpg.de
PGP public key:
ftp://ftp.mpifr-bonn.mpg.de:/outgoing/jbehrend/jbehrend-gpg.asc

 

[David R Brooks]

kulkarku@math.net wrote:

Hi i am new VLSI technology.
can anybody suggest me the criteria for choosing FPGA/CPLD for design.
which parameters play imp role in distingwishing them?
any guidline for that.

Most CPLDs have one flipflop per package signal pin.

So if your design needs more flipflops than there are signal pins in the
package, it's a done deal: FPGA.

 

[Thomas Stanka]

Hello,

Matt North schrieb:

They way i distinguish between the two is:

CPLD
-Instant On
-Non-volatile

Also valid for some FPGA famillies.

-Reconfigurable*

? Same as FPGA ?

-Fixed Path Delays
-Low/Medium size.

Also true for small FPGAs *g*

FPGA
-Setup Time
-Volatile

Only true for some FPGAs

-Reconfigurable
-Good for large designs.

With these points in mind CPLD is normally good for control applications and
logic soaking, FPGA is good for complex designs rich in register
utilisation.

Nowadays its hard to distinguish between CPLD and FPGA because naming a
device CPLD or FPGA is more marketing than anything else.

Traditional CPLDs have siginifcant less registers and are very limited
in routing pathes, but provide a good timing for each path. FPGAs
provide more registers and are totaly flexible in interconnecting logic
and registers while having longer routing delays [1].

bye Thomas

[1] for compareable technology. Don't expect a 0.5um CPLD to reach the
timing of a Virtex4.

 

hello,

what do you mean by clock manager... I would like to use a PLL but on
Stratix Altera FPGA, there is a minimum input clock frequency of about
15 MHz, and my clocks are under 4 MHz

 

[Mike Treseler]

Abs wrote:

so how do i give the inputs, i have a test vector, for which i want to
test wheather all teh statements are executed well, i get 99%, how do i
provide the input vector. should i use TCL Script or Testbenches.

I prefer to use a procedural vhdl testbench to
provide stimulus and verification, like the one here:
http://home.comcast.net/~mike_treseler/

There
are commands actually used to do code/state/branch coverage, are those
TCL commands. should i write a TCL Script to do all that.

Coverage is icing on the cake.
You need cake first.
Modelsim SE has an automatic interface to do coverage
testing for you, once you have working uut and testbench code.

-- Mike Treseler

 

Thanks. You guys are bith right. I see it now. Thank you for the help.

-Tony

 

[radarman]

What part are you targetting. Most modern parts no longer support true
*internal* tri-state drivers (and by extension, busses). In these
parts, you will get more mileage by creating an "or" structure, where
the modules output zero's when not selected, and you just OR all the
bus bits together. (ie. bus_0(0) or bus_1(0) or bus_2(0)...) The
downside is that now you can get some serious combinational latencies -
limiting the number of drivers on the bus.

Either way, I would suggest creating two busses - one for writes and
one for reads. The write bus is generally very simple, while the read
bus requires some effort - but the total effort is less than trying to
combine them.

 

[Mark McDougall]

Mike Treseler wrote:

Yes, you can. Write a testbench and run a simulation. Edit code,
repeat.

You forgot one last step...

Submit for assessment.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[Mark McDougall]

Mark McDougall wrote:

Actually, I think it's pretty obvious this guy didn't even write the
code in question.

Why steal code you don't know works?

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266