Clock Edge notation

[Tim Hubberstey]

Andy Peters wrote:

charles.el...@wpafb.af.mil wrote:

Below is my version of your code. I don't use IEEE.STD_LOGIC_ARITH
because it is not really an ieee standard. Instead I have used
ieee.numeric_std and used the type unsigned for count_up.


Ya know, it's funny. I just installed Xilinx' ISE 7.1 and I was
"thumbing" through the XST manual looking to see how certain things are
inferred.

The example code to infer an "Unsigned 8-bit Adder" (page 105) uses the
old Synopsys std_logic_arith and std_logic_unsigned libraries. In
fact, all of the examples use these libraries!

Maybe these libraries would shrivel up and die if the tools vendors
stopped using them in examples.

They won't do anything unless they hear the complaints. After all, the
code *is* correct, just outdated.

You should forward your post to Xilinx; maybe something will happen.

I don't know if we'll ever get rid of std_logic_unsigned and
std_logic_signed. There are too many designers around that prefer the
convenience of not having to deal with type conversions (BTW: I'm not
one of them).

What _might_ speed the demise of these libraries would be a utility to
automatically convert std_logic_arith, std_logic_unsigned, or
std_logic_signed code into numeric_std code. Without having done an in
depth analysis, I think it should be fairly simple. Then all that legacy
code using the old libraries could be (relatively) painlessly recovered.

Then again, the examples still use
VHDL'87 syntax (hello! rising_edge(clk), anyone?) in a document
copyrighted 2005.

This is a different issue. rising_edge(clk) is _not_ the same as
(clk'event and clk=1) for non-synthesized code. Changing over without
careful checking could result in "interesting" behavior in test benches.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

[Duane Clark]

ALuPin@web.de wrote:

...
t_Bidir_data <= t_tx_data when t_drive_tx_data='1' else (others =
'Z');
t_rx_data <= t_Bidir_data when t_drive_tx_data='0' else (others =
'0');
...

My question :
In the port map
Bidir_data => t_Bidir_data

an INOUT port of the unit under test is connected to a signal within
the testbench.

Will the Tristate Description shown work ? (Which "direction does
"t_Bidir_data" have ?)
The testbench "t_tx_data" generation takes over the tristate bus master
role.

Did you just try it? That would be the easy thing to do. Sure, it will
work. There is normally no reason to tristate the receive data. Just do

t_rx_data <= t_Bidir_data;

 

[Mike Treseler]

Neil wrote:

I've written a hdl design, and simulate it now. But I can't find the
way to write a hdl testbench to test the design.

Step one is to install a vhdl simulator
and run some tutorial examples.

A testbench is a text file.
It includes a null entity and
architecture processes
to wiggle and watch the design instance.

Besides the UUT instance, I normally
use a clock/reset generation process
and a main process to wiggle and watch.

Here's an example
http://tinyurl.com/cv43m

-- Mike Treseler

 

[Ben Twijnstra]

Hi Neil,

I use Modelsim as my simulator, and now use waveform to simulate. but
it seems not a good way when the design needs a long simulating time
and the input signals are changed both regular and irregular.

Let me read the sample first to get a general idea. thank you again.

The attached three files might also be of interest. They follow roughly the
same pattern but give you something to chew on. I wrote these on a Linux
box, so you may not be able to open them properly with Notepad, but most
other editors won't have any trouble with them.

I find the use of the txt_util package most useful because you don't need to
rely on ASSERT all the time.

Best regards,


Ben

 

[Ralf Hildebrandt]

Neil wrote:

I've written a hdl design, and simulate it now. But I can't find the
way to write a hdl testbench to test the design.

A testbench is nothing obscure. It is something you use to test your
design. It depends on you how a test should be designed.

Typically a testbench is a VHDL component that instantiates your design
inside plus some additional components you need (e.g. a clock generator).

Inside the testbench component you should generate some signals for your
design. You are free how to do this (components, functions, procedures,
synthesizable or not...). You may use the complete set of VHDL.

I've googled, But I
can't find much material on net.

This is because a testbench is always specialized for one design and
everybody writes testbenches a little bit different.



Ralf

 

[Ralf Hildebrandt]

Divyang M wrote:

In two of the states of my state machine I need to transition (or stay
in the same state) depending on internal signals (and not the inputs).
These signals are essentially counters. Is this OK to do and
synthesize?

Sounds good.
And this has two additional advantages:
* Your state-variable is "freezed" for a while (until the counter has
reached it's final value) and therefore all combinational logic, that
depends on the state variable will not change. This saves power,
because unnessecary transitionas are avoided. I call this counter "a
substatemachine inside a masterstatemachine".
* You can re-use the counter in many master-states. This may save
flipflops.

Or should I make a separate state for each of the counter values?

If such an counter is used only in one or two master-states and the
bitwidth of your master-state variable is wide enough, you would need
more flipflops using the masterstatemachine plus the counter than only
using a normal state machine.
Otherwise if the counter is reused extensively, you will save power and
may save flipflops.

process(clk)
begin
if (clk = '1' and clk'event) then

Just a hint: No reset?

when WAIT_16 =
if (newline = '1') then
mydelay <= mydelay + 1;
end if;
if mydelay = 16 then
next_state <= PROCESS;
else
next_state <= WAIT_16;
end if;

Looks good.


Ralf

 

[Jerzy Gbur]

Divyang M wrote:

Hi,

I am coding a state machine and have the transition from one state to
the next (or back to the same state) conditional on an internal signal.
The internal signal is essentially a counter. Is this OK to do and is
it synthesizable? Any forseen problems with it?

Here is a snippet of the state machine (one process type).
process(clk, rst) -- sensitivity list
"newline" is an INPUT port
"mydelay", "vert", and "horiz" are SIGNALs

when WAIT_16 =
if newline = '1' then
mydelay <= mydelay + 1;
end if;

if mydelay < 16 then
next_state <= WAIT_16;
else
next_state <= DO_PROCESSING;
end if;

when DO_PROCESSING =
if horiz < 640 then
horiz <= horiz + 1;
next_state <= DO_PROCESSING;
else
next_state <= WAIT_FOR_NEWLINE;
end if;

when WAIT_FOR_NEWLINE =
if newline = '1' then
if vert < 240 then
vert <= vert + 1;
else
vert <= 0;
end if;
horiz <= 0;
next_state <= DO_PROCESSING;
else
next_state <= WAIT_FOR_NEWLINE;
end if;

end case;

On the first glance it should work.

regards

Jerzy Gbur

 

[james]

On 15 May 2005 12:41:59 -0700, jo.spreutels@gmail.com (jo) wrote:

I need to make a vga controller but I have a problem.
The clock is 48 Mhz,so i have to divide it by two to have 24 Mhz for
640 by 480 pixels.
but the clock input should be the real clock 48 Mhz en there's also an
enable input and by this input we can get the correct(needed)
frequency of 24 MHz.
I don't know how to do this and how this exactly works,but it has to
be done this way,maybe somebody can write a little bit code for me?
Are explain howthis thing works.
thanks a lot!!
*****

A simple JK flip flop will divide by 2 nicely. That can be made from
two D flip flops.

james

 

[Mike Treseler]

Divyang M wrote:

I was going through some older posts in the forum and saw that the
WAIT_16 state can be interpreted as a 'Moore' state machine whithin a
'Mealy' state machine. And from a Mentor Graphics white paper on FSMs,
Moore machines have output glitches.

All your code is inside a clocked
process, so all outputs are registered.
No glitches.

-- Mike Treseler

 

[Mike Treseler]

Divyang M wrote:

Also, for a one process state machine do the internal signals need to
be on the process sensitivity list or just clk and reset signals?

just clk and reset

-- Mike Treseler

 

[Stefcio Z.]

On 15 May 2005 12:41:59 -0700, jo.spreutels@gmail.com (jo) wrote:

I need to make a vga controller but I have a problem.
The clock is 48 Mhz,so i have to divide it by two to have 24 Mhz for
640 by 480 pixels.
but the clock input should be the real clock 48 Mhz en there's also an
enable input and by this input we can get the correct(needed)
frequency of 24 MHz.
I don't know how to do this and how this exactly works,but it has to
be done this way,maybe somebody can write a little bit code for me?
Are explain howthis thing works.
thanks a lot!!

Should it be something like this?

architecture PreScaler of PreScaler is
signal Qint: STD_LOGIC_VECTOR(26 downto 0);
begin

process (CLK, RESET)
begin
if RESET = '1' then
Qint <= (others => '0');
elsif Clk'event and Clk='1' then
if CEI = '1' then
if Qint = 1 then
Qint <= (others => '0');
else
Qint <= Qint + 1;
end if;
end if;
end if;
end process;

CEO <= '1' when Qint = 1 else '0';

end PreScaler;

Next, you should map port CEO to CE in your design.

--
Lukasz Z.

 

[Jim Lewis]

Taras,

constant B4 : unsigned := "010";
constant CONST : unsigned := B4 + "001"; --is NOT locally static

constant B4 : integer := 2;
constant CONST : integer := B4 + 1; -- is locally static

From the LRM:
7.4.1 Locally static primaries
An expression is said to be locally static if and only if every
operator in the expression denotes an implicitly dened operator
whose operands and result are scalar and if every primary in the
expression is a locally static primary, where a locally static
primary is dened to be one of the following: ...

Integers are scalar, arrays are not.


The VHDL-200X effort has proposals that modify this.
Two important changes:
1) Strike the requirement for the operand and result to be scalar. (FT22)
2) Include operators defined in std_logic_1164 and numeric_std along
with implicitly defined operators in consideration for being
locally static. (FT23)


The VHDL-200X working group is looking for corporate support
to fund the LRM editing effort. Funding will determine the
question as to when the features will be available.
If your company can help sponsor this effort, please contact
myself (VASG vice-chair) or Stephen Bailey (VASG chair).


Best Regards,
Jim Lewis

Taras

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Mike Treseler]

Andy Peters wrote:

Divyang M wrote:
Thanks Mike, state machines have now started to make more sense now


And they'll make even more sense once you forget the following two
words:

Moore
Mealy

Amen to that!
Time to recycle those books.

I expect D-flops were more trouble
to wire up in 1954.


-- Mike Treseler

 

[james]

On 16 May 2005 00:33:58 -0700, jo.spreutels@gmail.com wrote:

I know how to divide a clock buth how does this works in combination
with the enable input?
****

A simple method though not always the best way is to gate the clock
with an "AND" gate.

james

 

[Jim Lewis]

Abilash,
Seeing simlar observations to yours, for the VHDL-200X effort
I proposed that VHDL accept Verilog gate level description as
a valid VHDL format. The response I received from at least
one EDA vendor was that VHDL gate level descriptions could
be as fast as Verilog gate level descriptions if the vendors
spent more time optimizing them.

If you want VHDL gate level designs to be faster, it is a
matter of making sure your vendors know that they need to
spend the time making them faster.

Best Regards,
Jim Lewis

Hi Group,
I am relatively new to VHDL and am tring to understand why
VHDL gate level descriptions simulate slower than verilog models.I was
told that it was because how the VHDL model gets evaluated (delay
models) that makes it slower.I didnt quite follow this and if somebody
in the group could point me towards a more detailed explanation ,it
would be great.I would also like to know why do we see better VHDL
performace at behavioural descriptions(as compared to verilog
behavioural descriptions.).I am sorry if this has been discussed
previously.

Thanks,
Abilash.

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Jim Lewis]

Pasacco,
Perhaps you want to consider using functions to implement
this rather than an entity.

Cheers,
Jim

Hi

I want to make the following two simple 4-to-1 and 2-to-1 mux, into one
entity with parameterized ports.
I am trying generic statement, yet with no success --:
Could someone give some idea?
Thankyou


--------------------------------------------------------------
-- 4-to-1 Mux
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity mux_gate is
port ( SEL: in STD_LOGIC_VECTOR (1 downto 0);
A,B,C,D: in STD_LOGIC;
SIG: out STD_LOGIC);
end mux_gate;

architecture RTL of mux_gate is
begin
SEL_PROCESS: process (SEL,A,B,C,D)
begin
case SEL is
when "00" => SIG <= A;
when "01" => SIG <= B;
when "10" => SIG <= C;
when others => SIG <= D;
end case;
end process SEL_PROCESS;
end RTL;
---------------------------------------------------
-- 2-to-1 Mux
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity mux_gate is
port ( SEL: in STD_LOGIC;
A,B: in STD_LOGIC;
SIG: out STD_LOGIC);
end mux_gate;

architecture RTL of mux_gate is
begin
SEL_PROCESS: process (SEL,A,B)
begin
case SEL is
when "0" => SIG <= A;
when others => SIG <= B;
end case;
end process SEL_PROCESS;
end RTL;
-------------------------------------------------------

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Amit Dua]

The Vital library provides "VitalMux" function.
You can take a look at it as the vital src code is shipped with standard
simulators. For e.g. ncvhdl/ncsim simulator ships it in
<installation_dir>/tools/inca/files/IEEE.src/prmtvs_b.vhd. It should
also be faster as vital library is accelerated in simulators.

VitalMux calls VInterMux that does the real work.
Look at VInterMux function if you dont want to use vital library.

rgds
-Amit.


Jim Lewis wrote:

Pasacco,
Perhaps you want to consider using functions to implement
this rather than an entity.

Cheers,
Jim


Hi

I want to make the following two simple 4-to-1 and 2-to-1 mux, into one
entity with parameterized ports.
I am trying generic statement, yet with no success --:
Could someone give some idea?
Thankyou


--------------------------------------------------------------
-- 4-to-1 Mux
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity mux_gate is
port ( SEL: in STD_LOGIC_VECTOR (1 downto 0);
A,B,C,D: in STD_LOGIC;
SIG: out STD_LOGIC);
end mux_gate;

architecture RTL of mux_gate is
begin
SEL_PROCESS: process (SEL,A,B,C,D)
begin
case SEL is
when "00" => SIG <= A;
when "01" => SIG <= B;
when "10" => SIG <= C;
when others => SIG <= D;
end case;
end process SEL_PROCESS;
end RTL;
---------------------------------------------------
-- 2-to-1 Mux
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity mux_gate is
port ( SEL: in STD_LOGIC;
A,B: in STD_LOGIC;
SIG: out STD_LOGIC);
end mux_gate;

architecture RTL of mux_gate is
begin
SEL_PROCESS: process (SEL,A,B)
begin
case SEL is
when "0" => SIG <= A;
when others => SIG <= B;
end case;
end process SEL_PROCESS;
end RTL; -------------------------------------------------------

 

[Martin Thompson]

jo.spreutels@gmail.com writes:

for a project I need to make a vga controller.
The purpose is that their will appear 3 rectangles at the screen.
Is it possible to have a look maybe at the code,since nothing is
appearing at the screen and I have a really hard time to find the
error.

Have you simulated it? I see you have some timings down there, where
did they come from?
Is the monitor syncing, or is it confused by your sync signals and
staying in power save.

this is the timing

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Don't do that - use ieee.numeric_std.all instead. See the vhdl FAQ
for all the reasons.

Then use unsigned types for your counter signals. Or just use integers!

<snip>

klokdeling: process (clock48)
--variabelen klokdelers
variable tel_klok24 : integer range 0 to 2**2-1;

--einde variabelen klokdelers

begin

if (clock48'event and clock48 = '1') then
tel_klok24 := tel_klok24 + 1;
if (tel_klok24 = 2) then
tel_klok24 := 0;
clock24 <= '1';


else
clock24 <= '0';
end if;
end if;

end process klokdeling;

timing: process (clock24)
begin



if (clock24'EVENT) and (clock24='1')then

You are generating a 'gated clock' here (in conjunction with the
process above). Better to generate a clock enable and do
if rising_edge(clock48) then
if enable_24 then
-- veeryting else
etc.
Snipped the rest, which doesn't look too unreasonable.

Can you get a white screen by setting RGB = "111"?

What are you driving the RGB lines with? Direct from the FPGA pin?
That's probably a bad idea as VGA signals are 75ohm source terminated
1Vpp (IIRC), not untermitaed 3.3V (or whatever you have set) signals.

Have you read this:
http://www.stanford.edu/class/ee108a/documentation/vga.pdf

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

 

[Egbert Molenkamp]

Maybe the quiet attribute?
Here an example. Since p is changed after a delta delay. De process resumes
after a delta. Then p1 is assigned at the second delta the process resumes
after the second delta and wait forever.

Egbert Molenkamp

entity demo is
port (a : in integer := 0);
end demo;

architecture bhv of demo is
signal p, p1 : integer := 0;
begin
process
begin
p <= a;
wait until not p'quiet;
report "test" severity note;
p1 <= p;
wait until not p1'quiet;
wait;
end process;
end bhv;


"Andy Peters" <Bassman59a@yahoo.com> schreef in bericht
news:1116351201.114042.248890@z14g2000cwz.googlegroups.com...

I think I should be able to do this, but I can't figure out what signal
attribute or other magic incantation is necessary. The following is
for a test bench.

Given a signal:

signal InData : std_logic_vector(7 downto 0); -- or whatever

assigned in some process somewhere:

InDataDrive : process is
begin
InData <= foo;
wait until FooIsHappy;
InData <= bar;
wait until BarIsHappy;
end process InDataDrive;

I'd like to have a process somewhere detect that InData changes and
then do something with the new value:

DealWithIt : process is
begin
... do some stuff
wait until InData'event;
... do more stuff
end process DealWithIt;

This all works wonderfully except when foo and bar are the same. In
that case, the wait until InData'event triggers on the initial change
(imagine that some other process changes both foo and bar during the
time BarIsHappy is false) but when InData is assigned bar (same as
foo), DealWithIt doesn't trigger.

I also tried

wait until InData'active;

which also didn't work.

Seems to me that even though the values assigned to InData are the
same, there are still transactions on InData.

I'm using ModelSim XE 6.0a. Perhaps there's an optimization happening?

I tried

wait until (InData'transaction = '1');

but that was even more evil -- my entire simulation suspended here.

Any ideas? I was trying to be clever and avoid adding a "New Data
Available" signal to this test bench logic.

Thanks,
-a

 

[Eyck Jentzsch]

praveen.kantharajapura@gmail.com wrote:

Hi ,

I am using NCSIM simulator to simulate my VHDL code, what i wanted to
know is how to generate a Value Change dump(VCD) file using NCSIM, to
load the wave forms offline in simvision.For ex in verilog we have
"$dumpvars" , how to do it for VHDL.


Thanks in advance ,
Praveen

RTFM, on TCL commandline: 'probe -create -vcd ...'

To get all options try: 'help probe' or the online docu cdsdoc)

-Eyck