Clock Edge notation

[m]

On 6 May 2005 14:26:11 -0700, "Praveen" <sams235@gmail.com> wrote:

Hi,

Could someone suggest me a circuit to get the below ouput from the
input?

__________________________________
| |
____| |______________________ Input


_____
| |
____| |______________________ Output


Thanks.

module pulse(..., in, out);
....
input in;
output out;

wire indlyd = DELAY(in);
wire out = !indlyd & in;
endmodule

now of course the interesting part inside DELAY and the missing ports.
One very crude way is to instantiate some delays between in and
indlyd. Or declare indyd as register and clock in through some number
of cycles. This depends on whether you have a clock to which in is
synchronous or how wide you want the pulse to be etc.

 

[Ralf Hildebrandt]

Praveen wrote:

Could someone suggest me a circuit to get the below ouput from the
input?

__________________________________
| |
____| |______________________ Input


_____
| |
____| |______________________ Output

_ _ _
| | | | | ...
____| |_| |_| clock


Sample Input with the rising_edge of clock. If Input is high, set output
high. With the next rising_edge of clock, if output is high, set it low
/and/ store the information, that Input was already high. Do not set
Output high, if the stored information says, that Input was already
high. Reset this information with the rising_edge of clock, if Input is low.
Hint: In the 2nd. sentence is an "error", because I did not want to
mention the stored information so early there.

Note: The rising_edge of Output will have a delay respective to Input.

Finally: This is a "pulse compressor", not a "pulse stretcher"

Ralf

 

[info_]

Taras_96 wrote:

Hi everyone,

I've got some simple code, shown below:
entity hello_world is -- test bench (top level like "main")
end entity hello_world;

library IEEE; -- but may need other libraries
use IEEE.std_logic_1164.all; -- basic logic types
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library STD;
use STD.textio.all; -- basic I/O

architecture test of hello_world is -- where declarations are placed
begin
my_print : process is -- a process is parallel
variable my_line : line; -- type 'line' comes from
textio
begin

wait;
end process my_print;
end architecture test;

Xilinx complains that

"ERROR:HDLParsers:3312 - C:/Xilinx/projects/test/test_io.vhd Line 21.
Undefined symbol 'line'."

I had a look at the Xilinx XST User Guide, and page 284 clearly shows
that 'line' is a supported type! I read a couple of other posts, and
they suggested that I enclose the code with -- pragma translate_off /
-- pragma translate_on, but Xilinx complained that:

"ERROR:HDLParsers:164 - C:/Xilinx/projects/test/test_io.vhd Line 27.
parse error, unexpected $"

What's going on??

Do you want to _synthesize_ writeline and access types (line) ?
Where do you expect the text to go to in the silicon ?

Files are for simulation (ModelSim), not for silicon (XST).

you may find useful to use file output in synthesizable code
for debug purpose, in which case you should embed this code within
the correct pragmas (in doubt, use synopsys' which are usually recognized).

Bert Cuzeau

 

[Ziggy]

robboll wrote:

I've got a few really large files on a laptop that I inherited that are
really large. Have no idea what they are for:

2733_4A-en-server.vhd 7/19/2004 4,130,321.408 bytes

Any idea or suggestion?

Thanks,

RBollinger

Have you tried opening them to see if its got comments?

 

[info_]

Ziggy wrote:

robboll wrote:

I've got a few really large files on a laptop that I inherited that are
really large. Have no idea what they are for:

2733_4A-en-server.vhd 7/19/2004 4,130,321.408 bytes

Any idea or suggestion?
Thanks,

RBollinger


Have you tried opening them to see if its got comments?

1. if it's 4 Gigabytes, just suggest using MSWord to inspect it LOL

2. If it 4+ megabytes and 0.408 byte, then I wonder what this
less than half a character might be

3. If it's VHDL RTL code from a human, then this guy deserves
an entry in the Guiness Book of Records ;-)
(maybe fell asleep on the Control V keys ?)

Might be a VHDL netlist, much less glorious, likely very useless.


Bert

 

[Mike Treseler]

Taras_96 wrote:

Is there
someway of declaring a unsigned variable's length in the body of a
function?

reference the length of the actual
argument right in the variable declaration
-- ...
)
return unsigned is
variable reg_v : unsigned(vec_arg'range);
begin
-- ...

So far I haven't had any success because you need to declare
the variable and its length before the body of the function, and you
can't declare an unconstrained variable.

No, but you can use an unconstrained parameter.

-- Mike Treseler

 

[Ben Twijnstra]

Hi Joey,

It seems that posting here (or the fpga group) clears my head (I think
I've answerd myself 3 times now within 24hrs of posting)... figured out
that my state machine setup was essentially correct, but I was not
clocking my registers, sort of assumed they would be updated (and
'saved') in the output process when I said stuff like:

my_ff <= my_ff and other_signal;

but since this process was combinational, my_ff wasn't ever going to
become a real FF. I guess these are the growing pains of transforming
from a programmer to a HW designer.

Is it possible for you to send me a snippet of the failing and the working
code? I'm currently writing a one-day training called "VHDL design for
software engineers" and would like to see if this is a thinko I haven't
covered yet.

Don't send code to the address specified in the header. Send it to
[myfirstname].[mylastname] at gmail dot com. Oh, and don't try to pronounce
my last name. It may hurt your tongue.

Best regards,


Ben Twijnstra

 

[Egbert Molenkamp]

library ieee;
use ieee.std_logic_1164.all;
entity mux is
generic (w : natural:= 2); -- sel_width
port (sel : in std_logic_vector(w-1 downto 0);
d : in std_logic_vector(2**w-1 downto 0);
o : out std_logic);
end mux;

library ieee;
use ieee.numeric_std.all;
architecture bhv of mux is
begin
o <= d (to_integer(unsigned(sel)));
end bhv;

Egbert Molenkamp



"Pasacco" <pasacco@gmail.com> wrote in message
news:1115579890.432800.109580@z14g2000cwz.googlegroups.com...

Hi

I want to make the following two simple 4-to-1 and 2-to-1 mux, into one
entity with parameterized ports.
I am trying generic statement, yet with no success --:
Could someone give some idea?
Thankyou


--------------------------------------------------------------
-- 4-to-1 Mux
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity mux_gate is
port ( SEL: in STD_LOGIC_VECTOR (1 downto 0);
A,B,C,D: in STD_LOGIC;
SIG: out STD_LOGIC);
end mux_gate;

architecture RTL of mux_gate is
begin
SEL_PROCESS: process (SEL,A,B,C,D)
begin
case SEL is
when "00" => SIG <= A;
when "01" => SIG <= B;
when "10" => SIG <= C;
when others => SIG <= D;
end case;
end process SEL_PROCESS;
end RTL;
---------------------------------------------------
-- 2-to-1 Mux
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity mux_gate is
port ( SEL: in STD_LOGIC;
A,B: in STD_LOGIC;
SIG: out STD_LOGIC);
end mux_gate;

architecture RTL of mux_gate is
begin
SEL_PROCESS: process (SEL,A,B)
begin
case SEL is
when "0" => SIG <= A;
when others => SIG <= B;
end case;
end process SEL_PROCESS;
end RTL;
-------------------------------------------------------

 

[Giuseppeł]

Bernasconi Sacha ha scritto:

Sto creando un sito sul vhdl in italiano, contenente una guida di
base, collegamenti a guide avanzate e un forum di discussione.
Se a qualcuno puň interessare e avesse voglia di iniziare a far vivere
il forum questo č l'indirizzo: http://vhdl.onlinedreams.ch
Saluti

Ciao,
Sulla pagina dei link, a mio parere, manca il link al programma ISE
della Xilinx.
La versione web e' liberamente scaricabile ed utilizzabile in ambiente
windows.
Quella a pagamento ha in piu' solo il coregen per generare
automaticamente degli oggetti del programma come sommatori, divisori,
funzioni complesse etc (intelletual proprerty per intenderci) e la
possibilita' di utilizzare piattaforme diverse come Linux e Sun.

--
---
Ciao
Giuseppe
-----------------------------------
http://digilander.libero.it/nokappa

 

[Giuseppeł]

Bernasconi Sacha ha scritto:

Ciao, sotto programmi->windows, nei link c'era giŕ il sito della
xilinx.
Se mi dici che c'č anche per linux e unix lo sposto sotto
multipiattaforma.
Dici che il link cosě alla xilinx č sufficiente o dovrei mettere
direttamente il link al programma?
grazie

sacha

Sinceramente metterei tutti i link in ordine alfabetico, ed
eventualmente a lato aggiungerei tra parentesi se e' multipiattaforma o no.

E' difficile capire cosa si intende con multipiattaforma o windows anche
perche' e' un continuo aggiornamento di versioni da parte delle case.

Vedi il messaggio di Matteo, dice che ISE web 7 e' anche per Linux,
mentre io ero fermo alla 6 che era solo per win.

Per il secondo quesito, metterei il link alla pagina di download. E' piu
veloce.

--
---
Ciao
Giuseppe
-----------------------------------
http://digilander.libero.it/nokappa

 

[Niv]

-- Instead of writing t_wraddress <= ("00010" & "0000100010");
-- or t_wraddress <= "000100000100010";
-- I want
-- some shorter expressions like

t_wraddress(14 downto 10) <= to_stdlogicvector(x"02");
t_wraddress(9 downto 0) <= to_stdlogicvector(x"22");

X"AB03" is a legal 16 bit std_logic_vector.
You're trying to assign X"22", an 8 bit vector to a 10 bit vector.
You shouldn't need the conversion function.

Try something like t_wradress(9 downto 0) <= "00" & X"22"; -- If you want
10 bit assignment

Regards, Niv.

 

[Duane Clark]

Andy Peters wrote:

A funny thing is happening in my test bench.

Given an entity with a vector in the list of ports:

entity foo is
port (
in bar : std_logic_vector(7 downto 0);
... );
end entity foo;

and a greatly-simplified architecture

architecture bletch of foo is
begin
proc : process is
begin
wait on bar; -- wait for change
doSomething;
end process proc;
end architecture bletch;

The problem is that the wait is triggered when the vector bar changes
from all undriven ('UUUUUUUU') to some reasonable value. Then
doSomething is called, and then it goes back to waiting for bar to
change. The higher-level module that uses foo definitely changes bar
again, and I can see it change in foo, but the process proc is hung and
apparently doesn't see bar changing.

You don't appear to have included enough code. Either you need a
sensitivity list, or you need an inifinite wait in the process.
Otherwise, Modelsim should give you an error when you attempt to compile
that. Do you have a sensitivity list that includes bar?

 

[Duane Clark]

Duane Clark wrote:

You don't appear to have included enough code. Either you need a
sensitivity list, or you need an inifinite wait in the process.
Otherwise, Modelsim should give you an error when you attempt to compile
that. Do you have a sensitivity list that includes bar?

Hmm.. my bad. Any wait is okay, so ignore that, sorry.

 

[Mike Treseler]

Andy Peters wrote:

The problem is that the wait is triggered when the vector bar changes
from all undriven ('UUUUUUUU') to some reasonable value. Then
doSomething is called, and then it goes back to waiting for bar to
change.

Maybe bar changes during doSomething;
instead of during the wait. You only
have half of a handshake here.

-- Mike Treseler

 

[NEWS-T-ONLINE]

jluisky schrieb:

hi everybody, I`m looking for some interface betwwen Microblaze and
SDRAM.

THANKS IN ADVANCE.

JLUIS
MEXICO

Hello JLUIS,

the EDK includes such an IPCore. The name of the interface for
microblaze to a SDRAM is "opb_sdram".

Helmut

 

[Ralf Hildebrandt]

Zenock wrote:

I'm new to VHDL and am running into some trouble. I know the code
listed below doesn't work. I don't understand exactly why it doesn't
work.

process (Pulse_in)
begin
if Rising_edge(Pulse_in) Then
....
elsif Falling_edge(Pulse_in) Then
....
end process;

Do not use both edges - use only one. Only very few synthesis tools and
libraries are capable of dual-edge flipflops.

Rule for the thumb: Don't use an else / elsif branch after an 'event
(rising_edge() / faling_edge()).


If you really need dual-edge behavior, there are ways to model it, but
in general: Try to avoid it as long as possible!

Ralf

 

[Mike Treseler]

Bigyellow wrote:

So I think is I use current_state as variable, I can read it
immediately in the clock process,
and if the current_state is a signal, after I assign it, I only can
read it in the next clock cycle, is it right?

You can do it either way.
I think variable descriptions are easier to read,
so I put state and output assignments in the same
process.

You can even put your entire design in
one process if you like, for example:

http://home.comcast.net/%7Emike_treseler/uart.vhd


-- Mike Treseler

 

[Mike Treseler]

charles.elias@wpafb.af.mil wrote:

I have designed many state machines and have never used a variable for
current_state or next_state.

A single variable or signal for state works fine
for a single process machine.

The concept of next_state is only needed
to define the combinational D side of the register
for the two process case.

-- Mike Treseler

 

[Benjamin Todd]

Hey Tomas,

I'm a bit confused by the code you posted... A couple of things..

Firstly, the sensitivity list of your FSM process only contains STATE_CLK,
that's a bit of a cheat... And i'm surprised it doesn't warn you about that
when you compile the file.
Secondly, State_CLK is never given a reset value... And then FS_RCV_ADD
state doesn't exist, my guess is that it's sending you to the Others state,
although i'm sure if that's what you intend?
Then of course, you've the isuue of your FSM hanging as it reaches the last
two of your states... It's never reassigned...

Have a fiddle, then repost some code!
Ben



"Tomas" <tom78@linuxmail.org> wrote in message
news:1115907337.245802.55440@f14g2000cwb.googlegroups.com...

Hi,

I'm having big problems simulating a very simple fsm in modelsim (I
write code in xilinx ISE). Problems arise as soon as try to simulate in
something different than behavioral model
(post-translate,post-map,post-place).

this is the FSM:

type STATE_TYPE is
(FS_IDLE,FS_RECV_INST,FS_RECV_ADDR,FS_SEND_DATA,FS_WRITE_DATA);
signal STATE, NEXTSTATE : STATE_TYPE;
signal STATECLK: bit;

begin
REG:
process (SCK,CS_N)
begin
if CS_N='1' then
-- reset
STATE<=FS_IDLE;
elsif (SCK'event and SCK='1') then
STATE<=NEXTSTATE;
STATECLK<=not STATECLK;
end if;
end process REG;

FSM_P:
process(STATECLK)
variable curr_indx:integer range 0 to 32;
begin
NEXTSTATE<=STATE;
case STATE is
when FS_IDLE => curr_indx:=0;
NEXTSTATE<=FS_RECV_INST;
TEST<="11111111";
when FS_RECV_INST => if curr_indx=4 then
NEXTSTATE<=FS_RECV_ADDR;
else
curr_indx:=curr_indx+1;
end if;

TEST<=conv_std_logic_vector(curr_indx,8);
when FS_SEND_DATA => TEST<="11000000";
when FS_WRITE_DATA => TEST<="10000000";
when others => TEST<="01000000";
end case;
end process FSM_P;
end Behavioral;

TEST is just a std_logic_vector(7 downto 0) I use for debug purposes.

If simulating behavioral model everything works as expected, curr_indx
increases until 4 then state is changed to FS_RECV_ADDR.

But when simulating post-translate model curr_indx is immediatly = 4,
instead of increasing at each change of of STATECLK. It is as if FSM_P
would be looped very fast instead of triggering to STATECLK changes.

Thanks in advance for help,
Tomas

 

[Tim Hubberstey]

Brad Smallridge wrote:

Hi folks,

How does one write this code cleanly?

if( segment_pointer_count="111111111" ) then
segment_pointer_count <= "000000001"; -- skip zero
else
segment_pointer_count <= segment_pointer_count+1;
end if;


That is, with something that is length independent.

Length independent _IF_ segment_pointer_count is 31 bits or less:

use numeric_std.all;
....
signal segment_pointer_count : unsigned(...);
....
if( segment_pointer_count=(2**segment_pointer_count'length)-1 ) then
segment_pointer_count <= 1; -- skip zero
else
segment_pointer_count <= segment_pointer_count+1;
end if;
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com