Clock Edge notation

[Jeff Cunningham]

Symon wrote:

In the past, I've kept the entity ports as slv, just using unsigned etc.
within the architecture. Partly because of reuse, easier for others to
understand on a multiple person team, etc. Now that numeric.std has been
standardised, I wonder if there's a reason to do this anymore?

If you have unsigned as primary IOs on your FPGA, xilinx tools will
replace them with slv on the gate level model and break your testbench.
-JCC

 

[Chuck McManis]

"Jeff Cunningham" <jcc@sover.net> wrote in message
news:hPeqc.2181$Hf.1277774@newshog.newsread.com...

Symon wrote:
In the past, I've kept the entity ports as slv, just using unsigned etc.
within the architecture. Partly because of reuse, easier for others to
understand on a multiple person team, etc. Now that numeric.std has been
standardised, I wonder if there's a reason to do this anymore?

If you have unsigned as primary IOs on your FPGA, xilinx tools will
replace them with slv on the gate level model and break your testbench.

This was part of my problem, one of the slv's was part of the input
specification to the pwm unit (8 bits of 'current count' data), comparing an
SLV to an unsigned gives an error message (something about 6 possible ways
to interpret the result), even unsigned(slv) gives that error, but
unsigned/unsigned compares work as do slv/slv compares. I was just curious
if the slv/slv compare was done by default as signed or unsigned.

--Chuck

 

[Martin Thompson]

"Chuck McManis" <devnull@mcmanis.com> writes:

"Jeff Cunningham" <jcc@sover.net> wrote in message
news:hPeqc.2181$Hf.1277774@newshog.newsread.com...
Symon wrote:
In the past, I've kept the entity ports as slv, just using unsigned etc.
within the architecture. Partly because of reuse, easier for others to
understand on a multiple person team, etc. Now that numeric.std has been
standardised, I wonder if there's a reason to do this anymore?

If you have unsigned as primary IOs on your FPGA, xilinx tools will
replace them with slv on the gate level model and break your testbench.

Yes - I tend to keep unsigned's for within module use, although I do use
them on certain entity's that won't go to the outside.

This was part of my problem, one of the slv's was part of the input
specification to the pwm unit (8 bits of 'current count' data), comparing an
SLV to an unsigned gives an error message (something about 6 possible ways
to interpret the result), even unsigned(slv) gives that error, but
unsigned/unsigned compares work as do slv/slv compares. I was just curious
if the slv/slv compare was done by default as signed or unsigned.

If you're using the synopsys std_logic_[un]signed or arith libraries
then it will get done however those libraries happen to do it - which
I've never been clear on, as I stick to numeric_std! If you're using
numeric_std, then I don't think slv/slv compares should work.

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

 

[Ralf Hildebrandt]

Chuck McManis wrote:

This was part of my problem, one of the slv's was part of the input
specification to the pwm unit (8 bits of 'current count' data), comparing an
SLV to an unsigned gives an error message (something about 6 possible ways
to interpret the result), even unsigned(slv) gives that error, but
unsigned/unsigned compares work as do slv/slv compares.

use IEEE.numeric_std.all;


if ((unsigned)some_slv = some_unsigned_vector) then
...


Just convert both vectors to the same type. It cost you a little time
for typing, but a well-defined behavior for unsigned / signed data.


Ralf

 

[Chuck McManis]

"Mike Treseler" <mike_treseler@comcast.net> wrote:

Take sdata_in out of the sensitivity list and
you have a synchronous process that will
sim and synth the same way.

Hmmm. Why are we making bytes in the first place?
-_______--______----____-------_

Don't we just want to preset a counter
while the data is high and count down
while it is low?

Well if we were doing one PWM channel perhaps. My goal is to have several
PWM channels.

Constraints on my design are that I want to be able to "clock in" the
various widths behind the running the circuit. Then, once I have the next
set of widths ready to go, to assert "load" and at the start of the next PWM
period, all PWM channels running at their new value.

As a roboticist, and a "hobby" one at that, one application of this
technique is to build a device for driving a number of R/C servos that can
be programmed with a serial bitstream, and then commanded to operate
synchronously. This level of control is essential in using R/C servos to
control articulated walking robots for example. (google on the term Robo-One
for examples)

I'd like to build it out of a CoolRunner CPLD. I am, perhap prematurely,
trying to be stingy on flip flops to save macrocells. If I create a single
"master counter" that is counting through its iterations, then I can create
a PWM output which consists of 'n' flip flops (equivalent to the counter
width) and some combinitorial logic that implements an n-bit compare. So if
my count width is 'n' then my macrocell count is (pwm_channels + 1) x 'n'.
This is because I can use the same macro cells for both the latch and the
comparator. The more channels I can get into the CPLD, the fewer CPLDs I'll
need. Many Robo-one robots have 27 degrees of freedom (that is a lot of PWM
channels .

The synchronous change facility is a "freebee" once I've isoloated the
serial shift register chain from the pwm generator channels (I end up
burning another n macro cells for each channel making it (2 * pwm_channels +
1) x 'n' macrocells.

There is some other magic with them being synchronous but not simultaneous
but I'm not close to needing that stuff yet.

--Chuck
http://www.mcmanis.com/chuck/robotics/

 

[Nicolas Matringe]

Przemo77 a écrit:

Urgently looking for working model - number 74194 series TTL in VDHL
language. I would really appreciated in anybody could help me find this
piece of software or point the place where I can find it on the Internet

Rule one: Google is your friend

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 

[Charles M. Elias]

"Przemo77" <pbar@tlen.pl> wrote in message news:<c9npuf$em2$1@news.dialog.net.pl>...

Urgently looking for working model - number 74194 series TTL in VDHL
language. I would really appreciated in anybody could help me find this
piece of software or point the place where I can find it on the Internet

You can get a data sheet for this device at the the Texas Instruments website:
http://www.ti.com/

Charles

 

[Just an Illusion]

Hi Przemo77,

This is a bidirectional shift register, and it's obsolete.
You can easily made a behavioral equivalent, or take any code of shift
register.

Do you need the functional model, or the VITAL once ?

Rgrds,
JaI



Przemo77 wrote:

Urgently looking for working model - number 74194 series TTL in VDHL
language. I would really appreciated in anybody could help me find this
piece of software or point the place where I can find it on the Internet

 

[roller]

"mx" <mx@mx.com> escribió en el mensaje
news:0V4Fc.84714$s25.47872@newssvr29.news.prodigy.com...
<snip>

(c) If the customer is acquired (purchased) by another company, the
EDA-software is non-transferrable.

and could somebody tell why's that? the furniture guys dont expect the new
owner of the company to pay them again for the furniture sitting in the
offices, why would we have to pay then to the software guys?

Thankfully within industry, the
standard practice is for the vendor to permit the ownership transfer, as
long as the new owner continues to pay the maintenance/support contract
obligations. This is cheaper for the new owner, because they don't
have to 're-purchase' the licenses (large one-time non-recurring
expense), rather merely pay the quarterly/yearly support-fee (smaller
recurring expense.)

that's more reasonable...

 

[Kai Harrekilde-Petersen]

"roller" <trash_nospam@hotmail.com> writes:

"mx" <mx@mx.com> escribió en el mensaje
news:0V4Fc.84714$s25.47872@newssvr29.news.prodigy.com...
snip
(c) If the customer is acquired (purchased) by another company, the
EDA-software is non-transferrable.

and could somebody tell why's that? the furniture guys dont expect the new
owner of the company to pay them again for the furniture sitting in the
offices, why would we have to pay then to the software guys?

You *buy* furniture, you *license* software. The devil is in the
lawyers^Wdetails.

Thankfully within industry, the
standard practice is for the vendor to permit the ownership transfer, as
long as the new owner continues to pay the maintenance/support contract
obligations. This is cheaper for the new owner, because they don't
have to 're-purchase' the licenses (large one-time non-recurring
expense), rather merely pay the quarterly/yearly support-fee (smaller
recurring expense.)

Yup, that's my experience as well.

Regards,


Kai

 

[roller]

"Kai Harrekilde-Petersen" <khp@harrekilde.dk> escribió en el mensaje
news:ulli1cvvf.fsf@harrekilde.dk...

"roller" <trash_nospam@hotmail.com> writes:

"mx" <mx@mx.com> escribió en el mensaje
news:0V4Fc.84714$s25.47872@newssvr29.news.prodigy.com...
snip
(c) If the customer is acquired (purchased) by another company, the
EDA-software is non-transferrable.

and could somebody tell why's that? the furniture guys dont expect the
new
owner of the company to pay them again for the furniture sitting in the
offices, why would we have to pay then to the software guys?

You *buy* furniture, you *license* software. The devil is in the
lawyers^Wdetails.

(i know it'd be proably off-topic, mostly naive and stupid question, but
i've never cared about licenses before so i dont know, i hope this will
enlight me)

yeah ok, but why it has to be that way? i mean, it's not even like if they
were giving you upgrades or anything!
besides, again, why cant we own software? who came up with the idea that
software, which is a "tool" has to be licensed instead of bought when i can
go to a hardware store and get any "tool" and do whatever i want with it. To
have a more related example, Intel doesnt care what i do with PCs.
It's like i buy a PC with WinXP preinstalled (which most of the time you
dont even get the chance to choose if you want it or not; and if they sell
it without, you dont even get a discount), and then if i sell it, i have to
sell it without the OS?
what's the deal with that? a phone has software inside, and if i sell it, i
sell it with the software, i wont go around erasing it do i?
i just dont understand why it has to be different.

Thankfully within industry, the
standard practice is for the vendor to permit the ownership transfer,
as
long as the new owner continues to pay the maintenance/support contract
obligations. This is cheaper for the new owner, because they don't
have to 're-purchase' the licenses (large one-time non-recurring
expense), rather merely pay the quarterly/yearly support-fee (smaller
recurring expense.)

Yup, that's my experience as well.

Regards,


Kai

 

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gppv84f

 

[Tom Verbeure]

what are scripts, what are theire applications in vlsi design and
verification?

Have a look here:
http://www.google.com/search?hl=en&lr=&ie=UTF-8&oi=defmore&q=define:Script

In the electronic design context, it's usually a text file with a
number a commands that a particular program/tool has to execute. And
example would be a synthesis script: it contains commands of the
synthesis tool that guide it on how to convert VHDL into gates. A lot
of tools provide a graphical interface to do this, but as people gain
experience with the tool, they find out it's usually quicker to specify
a number of settings in a file that can be copied etc.

Sometimes, scripts can evolve into larger full-blown programs. Most
electronic design tools that support scripting use TCL (Tool Command
Language) as the underlaying scripting language (which 1000 years from
now will be considered proof that Darwin's theory doesn't always get it
right, but that's another discussion altogether.)

There are a number of general purpose scripting languages that allow
one to automate a certain process (again, it's basically a program, but
much quicker to write than, say, C code). In verification, a typical
script would be a regression script: it goes through all the tests that
have been written for a certain design, run the simulation one after
the other and gather the results.
Popular scripting languages are Perl, Python and (grmmbl) TCL.

Tom

 

[anupam]

Hi Rajan,
Pl add the "sel" in sensitivity list and assign the value to
out_5,....,out_8 at sel = '1' and value to out_1,....,out_4 at sel = '0'

 

[valentin tihomirov]

Pl add the "sel" in sensitivity list and assign the value to
out_5,....,out_8 at sel = '1' and value to out_1,....,out_4 at sel = '0'

Is'nt it what he is doing now? It was mentioned that latches will be
incured.

 

[Klaus Falser]

In article <ch2j0j$1bc$1@reader08.wxs.nl>, rajan100000@hotmail.com
says...

Hi,

I want to ask you if the following code written is correct:

process (in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8)
begin
if (sel = '1') then
out_1 <= in_1;
out_2 <= in_2;
out_3 <= in_3;
out_4 <= in_4;
else
out_5 <= in_5;
out_6 <= in_6;
out_7 <= in_7;
out_8 <= in_8;
end if;
end process;

I would appreciate your help.

Thank you.

rajan

IMHO the simplest way to write a 2-way multiplexer for switching
between 2 signals is :

MuxedOut <= SignalA when sel= '1' else SignalB;

This is short and there is no need to worry about sensitivity
lists.

The second recommandation for you is to learn to use
vectors.
It is much more readable and less error prone if you
write

out(4 downto 1) <= input(4 downto 1);

instead of writing 4 single assignments.

Best regards

--
Klaus Falser
Durst Phototechnik AG
kfalser@IHATESPAMdurst.it

 

[valentin tihomirov]

IMHO the simplest way to write a 2-way multiplexer for switching
between 2 signals is :

MuxedOut <= SignalA when sel= '1' else SignalB;

This is short and there is no need to worry about sensitivity
lists.

Will these internal muxes be supported in VHDLXX

MuxedOut <= A when S1 else (B when S2 else C);


???

 

[Thomas Stanka]

"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote:

Will these internal muxes be supported in VHDLXX

MuxedOut <= A when S1 else (B when S2 else C);

Yes, at least if you remove the brackets.

You have two conccurent muxes with some different behavior. Both could
be used to build simple 2-to-1 Muxes.

1)
WITH Mux_selector SELECT
output<=A WHEN '0',
B WHEN '1';
2)
output<=A WHEN Cond1 ELSE
B WHEN Cond2 ELSE
C;

bye Thomas

 

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e_von_lintherzog goddamn matt parker alias erik von lint matt parker alias e_von_lindt_herzog matt parker alias eric von lint eastern european women his real name is matthew parker from cottage grove oregon and that is it http://tinyurl.com/4c2t5 matt parker alias sergi_smith matt parker alias erikvon lint herzog dildo matt parker alias ericvan linthout matt parker alias a_parker matt
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andyc matt parker was exposed as a liar at
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where he posts as jeff trueloves gerald michelle ccct and eric vanlint
shittings

cocksucks matt parker alias t dochenkova pissers matt parker alias gjones matt parker alias erikvan_lintherzog matt parker was born on 13 09 65 matt parker makes a living by selling underage female flesh to pornographers and whoremongers matt parker alias evan lint hout bitcher matt parker alias tanjadochenkova matt parker alias evan lindt hout nymphomania matt parker alias j jones
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parker alias erik_vonlindt_herzog all personals at trueloves.com are fake and the whole site sucks matt parker alias evan lindthout matt parker alias ericvon_lunsenhout the truth of this statement is proven by matt parker trying to delete or refute it matt parker alias erik vonlunsen herzog matt parker alias europeanguide.net matt parker alias ericvon_lindt_hout pen pals the scam site
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vanlint hout matt parker alias eric_von_lint_hout order a new identity at http://www.offshore-manual.com if personal data is captured by matt parker matt parker alias erik vanlunsen matt parker alias ericvon lindthout matt parker alias erik_von_lunsenherzog matt parker alias eric_von_lint matt parker alias phro_crew matt parker alias s machines matt parker alias date2000.net matt parker
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alias erik_vanlindt_herzog matt parker commits online impersonation
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ericvon lunsenhout matt parker alias evon_linthout matt parker alias erik_van_lint matt parker alias eric_von_lindt matt parker alias ericvan lindtherzog matt parker is guilty of illegal people trafficking and will be prosecuted matt parker alias erikvan lindt matt parker alias erik_vanlindt matt parker alias erik_van_lunsenhout matt parker alias erikparker mothafucka matt parker alias
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matt parker is a liar from leuven louvain belgium that lives in

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ericvon_lindt_herzog matt parker alias eric vonlunsen hout matt parker alias erik_van_lint_hout matt parker alias eriklunsen his mailbox is matt parker alias anna parker po box 1147 cottage grove 97424 oregon usa zoophilia matt parker alias evonlindtherzog matt parker alias e vonlindtherzog matt parker alias ericvan_lint_hout matt parker alias erikvanlindt herzog matt parker alias
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[Jim Lewis]

ALuPin,
First read Allan's post.

Bottom line, if Clk is doing a normal 0-1 transition,
these two are equivalent. Highlighting the differences:
rising_edge(Clk) finds 0-1, L-1, 0-H, L-H transitions of Clk
clk='1' and Clk'event finds all changes except 1-1.

If your problem only occurs at time 0, you have run into a
well known issue that is easy to avoid. See below.
If this happens at times other than time 0, the clock
net is misbehaving and it probably needs to be fixed.
I would not consider an X-1 transition of clock a valid
functional clock.

From a different point of view, how are you deciding
that your designs are different? If you mask out
things that occur before reset is applied, are they
the same?


Avoiding time 0 Problems
--------------------------
To avoid time 0 problems, I start clock at the inactive
edge and I initialize it:

signal Clk : std_logic := '0' ;
.. . .

Clk <= not Clk after tperiod_Clk/2 ;

-- or --

process begin
Clk <= '0' ;
wait for tperiod_Clk/2 ;
Clk <= '1' ;
wait for tperiod_Clk/2 ;
end process ;


Use the form that matches your current clock driving methodology.
Although I recommend the first form for new projects, I do
not recommend switching after you have built and run testbenches
because differences in execution of testbenches that can result.
To illuminate this, consider the code below (note Sel is driven
only so you can see the differences in the two clock setups).

Sel <= '0' after tpd ; -- where tpd << tperiod_Clk
wait for 10 * tperiod_Clk ; --
wait until Clk = '1' ; -- align with clock
Sel <= '1' after tpd ;

Simulation differences here are due to differences in
delta cycle setup time of the clocks above.

Long term, when using wait for that is a function of
your clock period, I using the following:

wait for 10*tperiod_Clk - tpd ;
wait until Clk = '1' ;


Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Hi,

I have a question concerning the following phenomenon:

I have a signal which is registered by the following way:


entity xy is
port (...
DQS : inout std_logic_vector(15 downto 0);
);
end xy;

architecture zy of xy is
signal l_input_cell : std_logic_vector(15 downto 0);
begin

process(Reset, Clk)
begin
if Reset='1' then
l_input_cell <= (others => '0');
elsif rising_edge(Clk) then
l_input_cell <= DQS;
end if;
end process;
end zy;

When I simulated the design (I had changed a different design to my
own
VHDL style) I got different simulation results (functional simulation
Modelsim) with respect to the signal "l_input_cell".

Then I changed "rising_edge(Clk)" back to "Clk'event and Clk='1'" and
I got the same result as in the original design.

So why is there a difference at all?
Does the use of an INOUT port play any role ?

I would appreciate your help.

Kind regards

André