Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
Yes, I am totally agree. I don't think this is going to work since youam.imak@gmail.com (Mohammed khader) wrote:
If you intend to do then use nested rising edge if statements as
follows..
if(clk=1 and clk'Event)then
if(p=1 and p'Event)then
Q <=Q+1 ;
end if ;
end if ;
I don't believe, that this piece of code will synthesis correctly.
Never use two clocks in one process for synthesisable code.
bye Thomas
A vhdl procedure is just an editing convenience.Is there any way to define a procedure in a package that sets a signal?
It stands to reason that you can't execute a script before tellingHi,
I have written a little .do-script with which
the VHDL files are compiled and the simulation is performed.
When I open Modelsim I have to go to
FILE --> CHANGE DIRECTORY and then I have to enter
the path of my simulation directory including my script.
How can I do this directory changing automatically at the beginning
of my script ? Is there any command ?
Instances will work, but consider using a FOR loop.For a very simple design I need to instantiate a lot of components. Only
two of the I/O signals of these components differ. Is there a smart way
to do this in VHDL or do I have to make a 100 copies to instatiate 100
components?
Cor,Cor van Loos wrote:
For a very simple design I need to instantiate a lot of components.
Only
two of the I/O signals of these components differ. Is there a smart
way
to do this in VHDL or do I have to make a 100 copies to instatiate
100
components?
Instances will work, but consider using a FOR loop.
-- Mike Treseler
Please read http://www.designabstraction.co.uk/HTML/articles.htm,I used multiplexer but its not working for me. Please Advice me some
other techniques
It is very hard to read, not only by the coding style. What editor didi am also attaching the code that What I did..
My guess: you're using 'event on two different signals (clock_100khz andI'm getting the following error:
Unsupported Feature Error: non-locally-static attributes names are not
supported
I'm using the Max Plus II student software version 10.2
and trying to compile the following code:
Synthesis will delete any logic not affectedWorks OK in simulation, but quartus synthesize
this as a simple OR on the next N1_max StopNextCells
positions which is not the intended behaviour.
Is this just a matter of convenience or does it really add somethingFolks,
The IEEE VHDL Working Group is considering a proposal to add vector types to
the package STANDARD in the next revision of the language. We would like
your feedback on the issue.
Currently, package STANDARD defines types STRING as a vector of CHARACTER
elements, and BIT_VECTOR as a vector of BIT elements. The proposal is to
define vector types for BOOLEAN, INTEGER, REAL and TIME. Users have
commented that these types would be useful for verification models, among
other applications.
Peter Ashenden wrote:
Folks,
The IEEE VHDL Working Group is considering a proposal to add vector
types to
the package STANDARD in the next revision of the language. We would
like
your feedback on the issue.
Currently, package STANDARD defines types STRING as a vector of
CHARACTER
elements, and BIT_VECTOR as a vector of BIT elements. The proposal is
to
define vector types for BOOLEAN, INTEGER, REAL and TIME. Users have
commented that these types would be useful for verification models,
among
other applications.
Is this just a matter of convenience or does it really add something
that whould not be possible without it? Is suppose an array (vector) of
an unconstrained type will still not be possible.
Paul.
I would expect it to be XXXX.I dont know where i went wrong in the following code,when i simulate the
code...i am getting RWD <= "UUUUUU"in the waveform results....
RWD is an inout, so in the testbench if you want to read a value fromUUT : SRAM port map(CADDR,RADDR,RWD,BNKSEL,RDCAS,WRCAS,DTRDY);
CADDR <= "0010010";
RADDR <= "0010";
RWD <= "0001000100010001";
BNKSEL <= '0','1' after 8 ns,'0' after 16 ns,'1' after 24 ns,'0' after 30
ns;
RDCAS <= '0','1' after 26 ns,'0' after 34 ns;
WRCAS <= '0','1' after 10 ns,'0' after 18 ns;
end tb;
is there any correction in my testbench???if so,can u plz rectify my
mistake....
For Synopsys you need to use the Presto VHDL compiler. This is anDavid,
I am working with the current FPHDL packages from the fast track in
synopsys. Do you still have a version specific for synopsys? (i.e.
with real functions commented out)
Thanks and Happy Holidays,
This sort of problem is best solved by simulation.But instead of getting this value I am getting garbage or other written
values. I am using
atmel prochip software so I do not have good simulator, so I am doing
alltesting on my hardware....