Clock Edge notation

[Colin Paul Gloster]

In news:uy7ma9wdw.fsf@trw.com timestamped Tue, 06 Mar 2007 16:20:27
+0000, Martin Thompson <martin.j.thompson@trw.com> posted:
"Colin Paul Gloster <Colin_Paul_Gloster@ACM.org> writes:

I am unhappy that electronic engineers are very eager to try
to transfer things which are unsuitable for software to hardware for
which they are also unsuitable, e.g. C++ and UML.

That sounds like one for the .sig file!"


Thank you, I aim to please!

Prof. Giovanni De Micheli said on April 2nd, 2007 while lecturing: "I
invented HardwareC a few years ago" and after he presented two slides
after that clause he said: "Java is a great language, I like it. It's
cleaner than C/C++, but that's life." He said that C has an advantage
over VHDL because code might initially be targeted to a processor but
be migrated to hardware elsewhere in the system if the attempt on the
processor does not perform well enough.

In contrast to what is quoted above which he used his voice to say, he
showed in writing more than one slide of his promoting the SystemC(R)
approach as being good. E.g. "Processes run concurrently". I asked
whether he had tried to convey that SystemC(R) code genuinely,
literally runs concurrently. He answered that he did mean that
literally, but he admitted that in practice SystemC(R) implementations
do not run concurrently. He clarified that he was convinced that the
SystemC(R) standard was written in terms of concurrency. During a
lunch break I challenged this again (this time by email: see below): I
did not receive a response from him yet but an organizer of the
lecture sent the response below.

Regards,
Colin Paul Gloster


On Mon, 2 Apr 2007, someone wrote with Subject field: "Re:
SystemC(R) concurrency, or lack thereof":

"Dear Colin Paul,

please try to address questions to Prof. De Micheli personally just
after the
lecture or during the break. This will avoid any form of
misunderstanding
without bothering Prof. De Micheli via email. Could you imagine if all
the
students would start sending questions to Prof. De Micheli via email
?

The presence of Prof. De Micheli is a great opportunity for all the
students
attending the course so please try to avoid asking too many questions
during the lecture in order for Professor De Micheli to have the
possibility to
address all the topics he originally planned for the course.

Thanks a lot for your understanding.

Best Regards, [..]


----- Original Message ----- From: "Colin Paul Gloster"
<Colin_Paul_Gloster@ACM.org>
To: <giovanni.demicheli[..]>
Cc: [.. some of the students who had been exposed to propaganda by the
lecturer, and also a carbon copy to the organizer]
Sent: Monday, April 02, 2007 2:05 PM
Subject: SystemC(R) concurrency, or lack thereof

Dear Professor Giovanni De Micheli,

You said on a number of occassions during one of the lectures today
that
SystemC(R) multiprogramming is concurrent. I asked you whether you
meant that
literally, to which you replied that you did literally mean that but
that
implementations might use interleaved serial code instead of
parallel code but
that you believed that the SystemC(R) definition is concurrent.

I completely reject your claim that the SystemC(R) library is
defined to be
concurrent. Please explain to me how I have misinterpreted the
definition of
the scheduling policy of the SystemC(R) standard's as described in
4.2.1 The
scheduling algorithm of the standard:
"The semantics of the scheduling algorithm are defined in the
following
subclauses.
[..]
An implementation may substitute an alternative scheme, provided the
scheduling
semantics given here are retained.
[..]
4.2.1.2 Evaluation phase
From the set of runnable processes, select a process instance and
trigger or
resume
its execution. Run the process instance immediately and without
interruption
up to
the point where it either returns or calls the function wait.
Since process instances execute without interruption, only a single
process
instance
can be running at any one time, and no other process instance can
execute
until the
currently executing process instance has yielded control to the
kernel. A
process shall
not pre-empt or interrupt the execution of another process. This is
known as
co-routine
semantics or co-operative multitasking.
[..]
A process may call the member function request update of a primitive
channel,
which will cause the member function update of that same primitive
channel to
be
called back during the very next update phase.
Repeat this step until the set of runnable processes is empty, then
go on to
the
update phase.
NOTE 1-The scheduler is not pre-emptive. An application can assume
that a
method process will execute in its entirety without interruption,
and a thread
or clocked
thread process will execute the code between two consecutive calls
to function
wait
without interruption.
[..]
NOTE 3-An implementation running on a machine that provides hardware
support
for concurrent processes may permit two or more processes to run
concurrently,
provided that the behavior appears identical to the co-routine
semantics
defined in
this subclause. In other words, the implementation would be obliged
to analyze
any
dependencies between processes and constrain their execution to
match the
co-routine
semantics."

Thanks,
Colin Paul Gloster

P.S. Other parts of the lecture were interesting."

 

[Eric Smith]

Weng Tianxiang wrote:

I have written an email to VHDL TSC to show my interest in pushing the
keyword "ORIF" into VHDL specification.

I respectfully suggest instead using the Ada shortcut logical operators
"or else" and "and then", since VHDL syntax was originally derived
from Ada. This avoids any need to introduce new reserved words.

Eric

 

[Andy]

On Apr 13, 11:03 pm, Eric Smith <e...@brouhaha.com> wrote:

Weng Tianxiang wrote:
I have written an email to VHDL TSC to show my interest in pushing the
keyword "ORIF" into VHDL specification.

I respectfully suggest instead using the Ada shortcut logical operators
"or else" and "and then", since VHDL syntax was originally derived
from Ada. This avoids any need to introduce new reserved words.

Eric

I strongly support the use of a standard expression in an assertion
statement to indicate that events are mutually exclusive, and that a
synthesis tool should treat them as such. Adding ORIF is less flexible
and harder to read/review. And how would a simulator verify ORIF?
Would it generate an assertion if the expressions were in fact not
mutually exclusive?

The use of "or else" in ada is not related to mutual exclusivity, but
is a short cut OPERATOR, useable only within a single expression, not
as part of the syntax of the if/then/elsif statement. It was designed
to enforce an order of execution on logical operators in the same
expression. Such different uses for the same syntax between ada and
vhdl would lead to much confusion.

Andy

 

[Gerhard Hoffmann]

On Sat, 28 Apr 2007 19:03:10 GMT, "mans" <(myname_here)_123456@yahoo.com> wrote:

I am new in VHDL and Emacs and I tried to use Emacs for editing VHDL
and attaching it to ISE. My experience is as follow:

I did the same with gvim. Works nicely. (please not another vi/emacs war!)

But one this is annoying: If I ask ISE for a syntax check etc, the first thing it does
is to kill all editor processes it has started. That's bad because some editors may
contain a changed file that is not yet written back or even may be editing something
completely unrelated in the meantime.

I usually have a lot of files open: the file with the entity, instantiation,
global constants, test bed...

Is there a switch I may have missed?

regards, Gerhard

 

[John Popelish]

Amit wrote:

On Apr 29, 12:01 pm, John Popelish <jpopel...@rica.net> wrote:
Anson.Stugg...@gmail.com wrote:
I'm designing a debounce filter using Finite State Machine. The FSM
behavior is it follows the inital input bit and thinks that's real
output until it receives 3 consecutive same bits and it changes output
to that 3 consecutive bit until next 3 consecutive bits are received.
A reset will set the FSM to output 1s until it receives the correct
input and ouput.
This is the test sequence with input and correct output.
1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input)
1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output)
The state diagram I came up has 6 states and it's named SEE1, SEE11,
SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in
the input. Because it just came from SEE1 and before SEE1, it came
from SEE000, so at SEE1 it can not change ouput to 1 which is what I
have specified that state's ouput to be.
Anyone knows how to solve this problem? Or maybe there's other better
ways to design the state diagram?
I'm not sure I understand your terminology, but I am
assuming that that state neames mean:

SEE1 = output = 0 after 1 has been input 1 times in a row.

SEE11 = output = 0 after 1 has been input 2 times in a row.

SEE111 = output = 1 after 1 has been input 3 times in a row
(or a 1 is input after 0 has been input less than 3
times in a row).

SEE0 = output = 1 after 0 has been input 1 times in a row.

SEE00 = output = 1 after 0 has been input 2 times in a row.

SEE000 = output = 0 after 0 has been input 3 times in a row
(or a 0 is input after 1 has been input less than 3
times in a row).

If this is the case, then the 12 transitions are:

before input after
SEE1 1 SEE11
SEE1 0 SEE000
SEE11 1 SEE111
SEE11 0 SEE000
SEE111 1 SEE111
SEE111 0 SEE0
SEE0 1 SEE111
SEE0 0 SEE00
SEE00 1 SEE111
SEE00 0 SEE000
SEE000 1 SEE1
SEE000 0 SEE000

Hi John,

It is not that I'm saying the table is wrong (since I'm new to this
and trying to learn) but how do you say: SEE1 with input 0 goes to
SEE11 state? because then our state must be SEE01!

The 6 states are defined above the transition table. There
is no SEE01 state, because there is no reason to keep track
of that sequence. If you are at SEE1 a single 1 input has
been seen since the output was decided to be zero), and a
zero arrives, you just go back to state SEE000 (the one
where the output was decided to be changed to zero) since
the required 3 1s in a row cannot occur till at least a
single 1 arrives. Any zero arriving before that triple 1 is
received just starts the count over.

 

[Amit]

On Apr 29, 5:45 pm, John Popelish <jpopel...@rica.net> wrote:

Amit wrote:
On Apr 29, 12:01 pm, John Popelish <jpopel...@rica.net> wrote:
Anson.Stugg...@gmail.com wrote:
I'm designing a debounce filter using Finite State Machine. The FSM
behavior is it follows the inital input bit and thinks that's real
output until it receives 3 consecutive same bits and it changes output
to that 3 consecutive bit until next 3 consecutive bits are received.
A reset will set the FSM to output 1s until it receives the correct
input and ouput.
This is the test sequence with input and correct output.
1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input)
1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output)
The state diagram I came up has 6 states and it's named SEE1, SEE11,
SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in
the input. Because it just came from SEE1 and before SEE1, it came
from SEE000, so at SEE1 it can not change ouput to 1 which is what I
have specified that state's ouput to be.
Anyone knows how to solve this problem? Or maybe there's other better
ways to design the state diagram?
I'm not sure I understand your terminology, but I am
assuming that that state neames mean:

SEE1 = output = 0 after 1 has been input 1 times in a row.

SEE11 = output = 0 after 1 has been input 2 times in a row.

SEE111 = output = 1 after 1 has been input 3 times in a row
(or a 1 is input after 0 has been input less than 3
times in a row).

SEE0 = output = 1 after 0 has been input 1 times in a row.

SEE00 = output = 1 after 0 has been input 2 times in a row.

SEE000 = output = 0 after 0 has been input 3 times in a row
(or a 0 is input after 1 has been input less than 3
times in a row).

If this is the case, then the 12 transitions are:

before input after
SEE1 1 SEE11
SEE1 0 SEE000
SEE11 1 SEE111
SEE11 0 SEE000
SEE111 1 SEE111
SEE111 0 SEE0
SEE0 1 SEE111
SEE0 0 SEE00
SEE00 1 SEE111
SEE00 0 SEE000
SEE000 1 SEE1
SEE000 0 SEE000

Hi John,

It is not that I'm saying the table is wrong (since I'm new to this
and trying to learn) but how do you say: SEE1 with input 0 goes to
SEE11 state? because then our state must be SEE01!

The 6 states are defined above the transition table. There
is no SEE01 state, because there is no reason to keep track
of that sequence. If you are at SEE1 a single 1 input has
been seen since the output was decided to be zero), and a
zero arrives, you just go back to state SEE000 (the one
where the output was decided to be changed to zero) since
the required 3 1s in a row cannot occur till at least a
single 1 arrives. Any zero arriving before that triple 1 is
received just starts the count over.

Thank you so much for your answer but before I complete the reading I
have a problem with this:

If you are at SEE1 a single 1 input has
been seen since the output was decided to be zero), and a

zero arrives

Question: let's say we are at SEE1 and input is 1. How should I know
the system expects 0? why not 1?

Regards,
amit

 

[petrus bitbyter]

"Default User" <defaultuserbr@yahoo.com> schreef in bericht
news:59nb7eF2i6v9uU1@mid.individual.net...

John Popelish wrote:

This is exactly the state diagram I drew before answering
the post. Nice work.

This has nothing to do with comp.lang.c. Please remove that newsgroup
from your distribution.




Brian

FAIK the OP was asking about the design of a finite state machine. Nothing
said about the implementation. C is a perfect language to build finite state
machines. The solution can for instance be implemented in a microcontroller
using C, most likely as a part of a larger design. (Although I'd prefer
assembler for small programs.) It can be implemented the same way in
programmable hardware using VHDL or Verilog. As a matter of fact, it is so
simple you can even implement it using old fashioned devices with flipflops
and gates. I can build all this possibilities plus some I did not mention.
Still complaints?

petrus bitbyter

 

[Edmond Coté]

On May 4, 12:47 am, Tom <tomahawk...@gmail.com> wrote:

Atom is a new high-level hardware description language embedded in
the functional language Haskell. Atom compiles circuit descriptions
in conditional term rewriting systems down to Verilog and VHDL
for IC simulation, verification, and synthesis.

I'll take a look...

Sounds a lot like Bluespec, what can you say about the differences
between the two?

Edmond

 

[Andy]

On May 14, 3:07 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:

Andy <jonesa...@comcast.net> writes:
I use xemacs with cua mode and it handles most of the windows
shortcuts (including C-c, C-x and C-v). I had to set another couple of
options to get it to treat the selected text as "pending delete" too.
I just wish there was a handy way to select a word or phrase in the
code and then search for other occurrences of it, with minimal
additional typing. There probably is, but I just don't know it yet!

Hi Andy,

Does C-s, M-y do what you want?

This calls up a search and pastes your previous copy into it. I have
C-s bound to isearch-forward, which may be non-default. C-s might be
a normal (non-incremental) search, in which case, C-s, C-y might do
the trick?

Alternatively, "M-x occur" is useful, it opens another window listing
which lines a particular phrase (well, regexp) occurs in. If you
like it, bind a key for that too

I also have a key bound to mark and copy the word/signalname/etc that
is under the cursor, all in one go. which is quite handy for these
sorts of things...

Cheers,
Martin

--
martin.j.thomp...@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html

None of the above worked. Highlighted text when you're typing in the i-
search pattern is a different color than text selected with the mouse
or shift-arrow keys.

Pasting does not seem to work in i-search (C-s).

I am pretty much a neophyte with emacs yet, so thanks for the hints!

Andy

 

[Ben Jones]

"Andy" <jonesandy@comcast.net> wrote in message
news:1179149348.293977.149420@h2g2000hsg.googlegroups.com...

None of the above worked. Highlighted text when you're typing in the i-
search pattern is a different color than text selected with the mouse
or shift-arrow keys.
Pasting does not seem to work in i-search (C-s).

Tsk. It's been said before and it'll be said again: "Emacs has just about
every feature you could possibly want from an operating system. Now all it
needs is a decent editor..."

-Ben-

 

On 14 Maj, 21:10, Mike Treseler <mike_trese...@comcast.net> wrote:

Andy wrote:
I was
looking for something that allows me to select an existing word,
usually a port or signal/variable name (with mouse or keyboard), and
search for other occurrences of that word. Typing the entire word gets
tedious when using long names with specific suffixes, which require
that virtually the entire name be re-typed.

I would just mark with the mouse then, C-s
and paste into the mini-buffer with
the center mouse key. Then C-s, C-s, ...

-- Mike Treseler

Try C-w (after doing C-s), it will increase the selection, word by
word,
following the point where you stand. I find it very useful.

Be careful, C-w is mapped to kill-region when you are not searching!
Undo (C-_) is your friend.

/Pontus

 

[Mike Treseler]

pontus.stenstrom@gmail.com wrote:

Try C-w (after doing C-s), it will increase the selection, word by
word,
following the point where you stand. I find it very useful.

Oh yes, and I see C-y marks to the end line.
Very useful indeed.

-- Mike Treseler

 

[Martin Thompson]

Andy <jonesandy@comcast.net> writes:
Hi Andy,

None of the above worked. Highlighted text when you're typing in the i-
search pattern is a different color than text selected with the mouse
or shift-arrow keys.

Yes, that's just isearch doing it's highlighty thing, compared to the
actual highlighting.

Pasting does not seem to work in i-search (C-s).

M-y ought to work for pasting into isearch. C-y does something
weird, like sucking everything to the end of the line into the buffer!

What does M-y do for you at the I-search: prompt?

I am pretty much a neophyte with emacs yet, so thanks for the hints!

I've been using it for 7 years now and I still feel like a neophyte!

Cheers,
Martin


--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

 

[Jim Granville]

Antti wrote:

yes I am sure silicon samples are available, I was more refereffing to
those
lattice evaluation kits that are "contact lattice" those are usually
not for sale,
but only to lease.. this is STUPID STUPID... i have tried to purchase
some
lattice boards, only to get offer to lease the board.

Maybe that's driven by some 3rd party SW license issue - seems a silly
idea for hardware, and it has to cost them more to admin that, than a
straight sale ?

-jg

 

[Antti]

Jim Granville schrieb:

Antti wrote:

yes I am sure silicon samples are available, I was more refereffing to
those
lattice evaluation kits that are "contact lattice" those are usually
not for sale,
but only to lease.. this is STUPID STUPID... i have tried to purchase
some
lattice boards, only to get offer to lease the board.

Maybe that's driven by some 3rd party SW license issue - seems a silly
idea for hardware, and it has to cost them more to admin that, than a
straight sale ?

-jg
nono

I think they only get very little yield on first batch of silicon so
they only make maybe 20 boards
- so those are not for sale only to lease...

Antti

 

[Mike Treseler]

Alfonso Acosta wrote:

I'm developing a System Description Language (which could be used as
an HDL in particular) called ForSyDe: http://www.ict.kth.se/info/FOFU/ForSyDe/

I'm planning to add a backend to my compiler wich generates a
graphical representation of the system.

I expect that not all 5 newsgroups would be interested
even if it were finished.

To my surprise, I havent found any tool which generates a schematic or
system graph given a HDL model. Does anyone know any of them?

This has been done.
Most synthesis tools have an RTL viewer which
generates schematics and state graphs from a netlist.
Google a bit.

Does any one know about a specific, open file format for schematics?
Common netlist formats are edif, verilog and vhdl.

My best options so far are GXL (http://www.gupro.de/GXL/) and GraphML
(http://graphml.graphdrawing.org/) but I coudn't find any free viewer
with automatic routing support.

Low cost backend tools are device specific.
Few are free.

-- Mike Treseler

 

[mk]

Hi,
I updated the GTKWave for Win32 port I am maintaining. It's at 3.0.29
now.

http://www.dspia.com/gtkwave.html

 

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[Wei Wang]

On Jul 27, 3:34 pm, Frank Buss <f...@frank-buss.de> wrote:

Nial Stewart wrote:
I ran a fairly quick FPGA build through Quartus to get a time for a
before and after comparison before I did the swap.

Did you changed the setting "use up to x number of CPUs" (don't remember
the exact name) somewhere in the project settings?

--
Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de

is there such a setting for xilinx ise as well?

thx, -wei

 

[Larry Pattis]

Please help me add verses to this little ditty for our paranoid
schizophrenic friend:


I've got those persecution blues,
The man keeps spyin' on me.
I can post to the internet, and complain, you see,
Because itšs all comin' down, and my radio is listenin' to me.

Whoa, I've got those persecution blues,
I can't keep all them eyes off of me.
They bug my computer, they bug my TV,
They bug my toilet, now that's really buggin' me.

Say, I've got those persecution blues,
And it's really got me seein' red.
I post all my nonsense, and I forget to take my meds,
They're chasin' after me, and you know what, it's all in my head.

So I've got those persecution blues,
It's their silence that has me convinced,
That they're about to bust in,
And have all my grey matter rinsed.

--
Larry Pattis
email: LP "at" LarryPattis "dot" com
http://www.LarryPattis.com