What is the problem with this ?

[Jim Thompson]

On Mon, 1 Dec 2008 13:45:26 -0600, krw <krw@att.zzzzzzzzz> wrote:

In article <k7c8j492pfa8ug98oa2cbrcg228jcgj0ae@4ax.com>, To-Email-
Use-The-Envelope-Icon@My-Web-Site.com says...
On Mon, 1 Dec 2008 12:37:56 -0600, krw <krw@att.zzzzzzzzz> wrote:

In article <4ripi4l5fq728f9011i1p8d1r79a549m4h@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...
On Tue, 25 Nov 2008 19:51:36 -0800, JosephKK <quiettechblue@yahoo.com
wrote:

On Mon, 24 Nov 2008 15:27:56 -0800, "Joel Koltner"
zapwireDASHgroups@yahoo.com> wrote:

"Vladimir Vassilevsky" <antispam_bogus@hotmail.com> wrote in message
news:6uGWk.4982$8_3.1230@flpi147.ffdc.sbc.com...
BTW, I have heard many times of the idea of asynchronous CPU. So the results
of operations are not synchronized to a clock, but propagate further at the
natural speed. The synchronization is done by delay matching at the critical
points. Ideally, that should work faster then the clocked logic; perhaps the
variance of the delays kills the idea.

Intel CPUs use some "chunks" of asynchronous logic for, e.g., instruction
decoders, but what I've heard the presenters of papers on this topic stress is
that their goal is usually power reduction much moreso than speed.

It seems that there should be a textbook of asynchronous logic design out
there by now... besides going over the usual discussion of how you avoid race
conditions with your min terms/max terms, it'd also discuss the various clever
schemes people have come up with to do handshaking between multiple
asynchronous modules, perhaps discuss various historical results (like the
Hennessy & Patterson book does... when I took a class using it in college
years ago, the professor was pretty darned good so typically there "meat" of
H&P was just review anyway -- and it's not like the math was hard --, but I
always looked forward to their end--of-chapter "real life examples"
discussions), etc.

---Joel


There is and there isn't. It is presumed covered in the combinatorial
logic and sequential logic courses. But, of course it isn't really
covered. Most state machine courses are trash as well.


ME: Use a transparent latch.

Aren't all latches transparent?

No. Some are edge-triggered, such as 74HC74.

That's a D-Type master-slave flip-flop, no matter what the mustard
bible says.

Of course, that's how "edge-triggered" is accomplished.

Xilinx Software: WARNING -- You are using a transparent latch!

Xilinx' rules/technoloy/software hates latches. Other's have
nothing but. When in Rome, do as the groundrules writers do.

...Jim Thompson

Brings back a question I've broached before. Any VHDL or VHDL-like
program that generates schematics?

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine Sometimes I even put it in the food

 

[krw]

In article <t4l8j4lm90quaqm4vmgm357s716hnf4h77@4ax.com>, To-Email-
Use-The-Envelope-Icon@My-Web-Site.com says...

On Mon, 1 Dec 2008 13:45:26 -0600, krw <krw@att.zzzzzzzzz> wrote:

In article <k7c8j492pfa8ug98oa2cbrcg228jcgj0ae@4ax.com>, To-Email-
Use-The-Envelope-Icon@My-Web-Site.com says...
On Mon, 1 Dec 2008 12:37:56 -0600, krw <krw@att.zzzzzzzzz> wrote:

In article <4ripi4l5fq728f9011i1p8d1r79a549m4h@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...
On Tue, 25 Nov 2008 19:51:36 -0800, JosephKK <quiettechblue@yahoo.com
wrote:

On Mon, 24 Nov 2008 15:27:56 -0800, "Joel Koltner"
zapwireDASHgroups@yahoo.com> wrote:

"Vladimir Vassilevsky" <antispam_bogus@hotmail.com> wrote in message
news:6uGWk.4982$8_3.1230@flpi147.ffdc.sbc.com...
BTW, I have heard many times of the idea of asynchronous CPU. So the results
of operations are not synchronized to a clock, but propagate further at the
natural speed. The synchronization is done by delay matching at the critical
points. Ideally, that should work faster then the clocked logic; perhaps the
variance of the delays kills the idea.

Intel CPUs use some "chunks" of asynchronous logic for, e.g., instruction
decoders, but what I've heard the presenters of papers on this topic stress is
that their goal is usually power reduction much moreso than speed.

It seems that there should be a textbook of asynchronous logic design out
there by now... besides going over the usual discussion of how you avoid race
conditions with your min terms/max terms, it'd also discuss the various clever
schemes people have come up with to do handshaking between multiple
asynchronous modules, perhaps discuss various historical results (like the
Hennessy & Patterson book does... when I took a class using it in college
years ago, the professor was pretty darned good so typically there "meat" of
H&P was just review anyway -- and it's not like the math was hard --, but I
always looked forward to their end--of-chapter "real life examples"
discussions), etc.

---Joel


There is and there isn't. It is presumed covered in the combinatorial
logic and sequential logic courses. But, of course it isn't really
covered. Most state machine courses are trash as well.


ME: Use a transparent latch.

Aren't all latches transparent?

No. Some are edge-triggered, such as 74HC74.

That's a D-Type master-slave flip-flop, no matter what the mustard
bible says.

Of course, that's how "edge-triggered" is accomplished.

The point is that it is not a latch.

Xilinx Software: WARNING -- You are using a transparent latch!

Xilinx' rules/technoloy/software hates latches. Other's have
nothing but. When in Rome, do as the groundrules writers do.

...Jim Thompson


Brings back a question I've broached before. Any VHDL or VHDL-like
program that generates schematics?

I don' know of any freebies, and the ones I've used aren't any good
for documentation (further than ports). They draw bug ugly
schematics. One alternative is to use schematic entry for top-level
and data flow, with VHDL for state machines. I find it easier to
just bite the bullet and go all VHDL for chips and schematics for
boards.

--
Keith

 

[Jim Thompson]

On Mon, 1 Dec 2008 19:20:02 -0600, krw <krw@att.bizzzzzzzzzz> wrote:

In article <t4l8j4lm90quaqm4vmgm357s716hnf4h77@4ax.com>, To-Email-
Use-The-Envelope-Icon@My-Web-Site.com says...

On Mon, 1 Dec 2008 13:45:26 -0600, krw <krw@att.zzzzzzzzz> wrote:

In article <k7c8j492pfa8ug98oa2cbrcg228jcgj0ae@4ax.com>, To-Email-
Use-The-Envelope-Icon@My-Web-Site.com says...
On Mon, 1 Dec 2008 12:37:56 -0600, krw <krw@att.zzzzzzzzz> wrote:

In article <4ripi4l5fq728f9011i1p8d1r79a549m4h@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...
On Tue, 25 Nov 2008 19:51:36 -0800, JosephKK <quiettechblue@yahoo.com
wrote:

On Mon, 24 Nov 2008 15:27:56 -0800, "Joel Koltner"
zapwireDASHgroups@yahoo.com> wrote:

"Vladimir Vassilevsky" <antispam_bogus@hotmail.com> wrote in message
news:6uGWk.4982$8_3.1230@flpi147.ffdc.sbc.com...
BTW, I have heard many times of the idea of asynchronous CPU. So the results
of operations are not synchronized to a clock, but propagate further at the
natural speed. The synchronization is done by delay matching at the critical
points. Ideally, that should work faster then the clocked logic; perhaps the
variance of the delays kills the idea.

Intel CPUs use some "chunks" of asynchronous logic for, e.g., instruction
decoders, but what I've heard the presenters of papers on this topic stress is
that their goal is usually power reduction much moreso than speed.

It seems that there should be a textbook of asynchronous logic design out
there by now... besides going over the usual discussion of how you avoid race
conditions with your min terms/max terms, it'd also discuss the various clever
schemes people have come up with to do handshaking between multiple
asynchronous modules, perhaps discuss various historical results (like the
Hennessy & Patterson book does... when I took a class using it in college
years ago, the professor was pretty darned good so typically there "meat" of
H&P was just review anyway -- and it's not like the math was hard --, but I
always looked forward to their end--of-chapter "real life examples"
discussions), etc.

---Joel


There is and there isn't. It is presumed covered in the combinatorial
logic and sequential logic courses. But, of course it isn't really
covered. Most state machine courses are trash as well.


ME: Use a transparent latch.

Aren't all latches transparent?

No. Some are edge-triggered, such as 74HC74.

That's a D-Type master-slave flip-flop, no matter what the mustard
bible says.

Of course, that's how "edge-triggered" is accomplished.

The point is that it is not a latch.

Xilinx Software: WARNING -- You are using a transparent latch!

Xilinx' rules/technoloy/software hates latches. Other's have
nothing but. When in Rome, do as the groundrules writers do.

...Jim Thompson


Brings back a question I've broached before. Any VHDL or VHDL-like
program that generates schematics?

I don' know of any freebies, and the ones I've used aren't any good
for documentation (further than ports). They draw bug ugly
schematics. One alternative is to use schematic entry for top-level
and data flow, with VHDL for state machines. I find it easier to
just bite the bullet and go all VHDL for chips and schematics for
boards.

What I'd like would be a program... feed it a clocked truth table and
have it spit out a gate-level schematic.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine Sometimes I even put it in the food

 

[John Larkin]

On Mon, 1 Dec 2008 12:37:56 -0600, krw <krw@att.zzzzzzzzz> wrote:

In article <4ripi4l5fq728f9011i1p8d1r79a549m4h@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...
On Tue, 25 Nov 2008 19:51:36 -0800, JosephKK <quiettechblue@yahoo.com
wrote:

On Mon, 24 Nov 2008 15:27:56 -0800, "Joel Koltner"
zapwireDASHgroups@yahoo.com> wrote:

"Vladimir Vassilevsky" <antispam_bogus@hotmail.com> wrote in message
news:6uGWk.4982$8_3.1230@flpi147.ffdc.sbc.com...
BTW, I have heard many times of the idea of asynchronous CPU. So the results
of operations are not synchronized to a clock, but propagate further at the
natural speed. The synchronization is done by delay matching at the critical
points. Ideally, that should work faster then the clocked logic; perhaps the
variance of the delays kills the idea.

Intel CPUs use some "chunks" of asynchronous logic for, e.g., instruction
decoders, but what I've heard the presenters of papers on this topic stress is
that their goal is usually power reduction much moreso than speed.

It seems that there should be a textbook of asynchronous logic design out
there by now... besides going over the usual discussion of how you avoid race
conditions with your min terms/max terms, it'd also discuss the various clever
schemes people have come up with to do handshaking between multiple
asynchronous modules, perhaps discuss various historical results (like the
Hennessy & Patterson book does... when I took a class using it in college
years ago, the professor was pretty darned good so typically there "meat" of
H&P was just review anyway -- and it's not like the math was hard --, but I
always looked forward to their end--of-chapter "real life examples"
discussions), etc.

---Joel


There is and there isn't. It is presumed covered in the combinatorial
logic and sequential logic courses. But, of course it isn't really
covered. Most state machine courses are trash as well.


ME: Use a transparent latch.

Aren't all latches transparent?

Unless they are edge-triggered.

Xilinx Software: WARNING -- You are using a transparent latch!

Xilinx' rules/technoloy/software hates latches. Other's have
nothing but. When in Rome, do as the groundrules writers do.

Sometimes a transparent latch can eliminate a full clock of pipeline
delay. They are also a handy way of crossing clock boundaries in some
situations. But they blaspheme The Church Of Synchronous Design.

We mostly ignore the Xilinx warnings. A good, tight design can throw a
thousand or so.

John

 

[John Larkin]

On Mon, 01 Dec 2008 14:20:02 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@My-Web-Site.com> wrote:

On Mon, 1 Dec 2008 13:45:26 -0600, krw <krw@att.zzzzzzzzz> wrote:

In article <k7c8j492pfa8ug98oa2cbrcg228jcgj0ae@4ax.com>, To-Email-
Use-The-Envelope-Icon@My-Web-Site.com says...
On Mon, 1 Dec 2008 12:37:56 -0600, krw <krw@att.zzzzzzzzz> wrote:

In article <4ripi4l5fq728f9011i1p8d1r79a549m4h@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...
On Tue, 25 Nov 2008 19:51:36 -0800, JosephKK <quiettechblue@yahoo.com
wrote:

On Mon, 24 Nov 2008 15:27:56 -0800, "Joel Koltner"
zapwireDASHgroups@yahoo.com> wrote:

"Vladimir Vassilevsky" <antispam_bogus@hotmail.com> wrote in message
news:6uGWk.4982$8_3.1230@flpi147.ffdc.sbc.com...
BTW, I have heard many times of the idea of asynchronous CPU. So the results
of operations are not synchronized to a clock, but propagate further at the
natural speed. The synchronization is done by delay matching at the critical
points. Ideally, that should work faster then the clocked logic; perhaps the
variance of the delays kills the idea.

Intel CPUs use some "chunks" of asynchronous logic for, e.g., instruction
decoders, but what I've heard the presenters of papers on this topic stress is
that their goal is usually power reduction much moreso than speed.

It seems that there should be a textbook of asynchronous logic design out
there by now... besides going over the usual discussion of how you avoid race
conditions with your min terms/max terms, it'd also discuss the various clever
schemes people have come up with to do handshaking between multiple
asynchronous modules, perhaps discuss various historical results (like the
Hennessy & Patterson book does... when I took a class using it in college
years ago, the professor was pretty darned good so typically there "meat" of
H&P was just review anyway -- and it's not like the math was hard --, but I
always looked forward to their end--of-chapter "real life examples"
discussions), etc.

---Joel


There is and there isn't. It is presumed covered in the combinatorial
logic and sequential logic courses. But, of course it isn't really
covered. Most state machine courses are trash as well.


ME: Use a transparent latch.

Aren't all latches transparent?

No. Some are edge-triggered, such as 74HC74.

That's a D-Type master-slave flip-flop, no matter what the mustard
bible says.

Of course, that's how "edge-triggered" is accomplished.



Xilinx Software: WARNING -- You are using a transparent latch!

Xilinx' rules/technoloy/software hates latches. Other's have
nothing but. When in Rome, do as the groundrules writers do.

...Jim Thompson


Brings back a question I've broached before. Any VHDL or VHDL-like
program that generates schematics?

...Jim Thompson

There is expensive software that will take VHDL and create a
schematic, apparently for people who aren't sure what they have
designed. The output I've seen looks like something one of my cats
would cough up.

It's tragic that there is not an industry-standard ascii format to
express schematics, like the LT Spice thing.

John

 

[krw]

In article <j699j4lcumibvnnboacfihks09o7l7cltp@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...

On Mon, 1 Dec 2008 12:37:56 -0600, krw <krw@att.zzzzzzzzz> wrote:

In article <4ripi4l5fq728f9011i1p8d1r79a549m4h@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...
On Tue, 25 Nov 2008 19:51:36 -0800, JosephKK <quiettechblue@yahoo.com
wrote:

On Mon, 24 Nov 2008 15:27:56 -0800, "Joel Koltner"
zapwireDASHgroups@yahoo.com> wrote:

"Vladimir Vassilevsky" <antispam_bogus@hotmail.com> wrote in message
news:6uGWk.4982$8_3.1230@flpi147.ffdc.sbc.com...
BTW, I have heard many times of the idea of asynchronous CPU. So the results
of operations are not synchronized to a clock, but propagate further at the
natural speed. The synchronization is done by delay matching at the critical
points. Ideally, that should work faster then the clocked logic; perhaps the
variance of the delays kills the idea.

Intel CPUs use some "chunks" of asynchronous logic for, e.g., instruction
decoders, but what I've heard the presenters of papers on this topic stress is
that their goal is usually power reduction much moreso than speed.

It seems that there should be a textbook of asynchronous logic design out
there by now... besides going over the usual discussion of how you avoid race
conditions with your min terms/max terms, it'd also discuss the various clever
schemes people have come up with to do handshaking between multiple
asynchronous modules, perhaps discuss various historical results (like the
Hennessy & Patterson book does... when I took a class using it in college
years ago, the professor was pretty darned good so typically there "meat" of
H&P was just review anyway -- and it's not like the math was hard --, but I
always looked forward to their end--of-chapter "real life examples"
discussions), etc.

---Joel


There is and there isn't. It is presumed covered in the combinatorial
logic and sequential logic courses. But, of course it isn't really
covered. Most state machine courses are trash as well.


ME: Use a transparent latch.

Aren't all latches transparent?

Unless they are edge-triggered.

Then they're flip-flops. ;-)

Xilinx Software: WARNING -- You are using a transparent latch!

Xilinx' rules/technoloy/software hates latches. Other's have
nothing but. When in Rome, do as the groundrules writers do.

Sometimes a transparent latch can eliminate a full clock of pipeline
delay. They are also a handy way of crossing clock boundaries in some
situations. But they blaspheme The Church Of Synchronous Design.

No, only if the groundrules specify edge-triggered FFs. All IBM
(bipolar) mainframes used latch pairs or PHs ("latches" and
"triggers") as their register elements, and most is strictly
synchronous. Even the CMOS versions use latches, though they're
better hidden. ;-)

We mostly ignore the Xilinx warnings. A good, tight design can throw a
thousand or so.

I guess maybe! They throw so many it's impossible to ferret through
them to find the ones that will bite, and there are many. Decent
software would have the warning messages switchable by class, type,
and instance to allow the dangerous ones shine through the fog.

--
Keith

 

[krw]

In article <q369j4l3lq8bdj8fecbk0f5ppi2l0m44jj@4ax.com>, To-Email-
Use-The-Envelope-Icon@My-Web-Site.com says...

On Mon, 1 Dec 2008 19:20:02 -0600, krw <krw@att.bizzzzzzzzzz> wrote:

In article <t4l8j4lm90quaqm4vmgm357s716hnf4h77@4ax.com>, To-Email-
Use-The-Envelope-Icon@My-Web-Site.com says...

On Mon, 1 Dec 2008 13:45:26 -0600, krw <krw@att.zzzzzzzzz> wrote:

In article <k7c8j492pfa8ug98oa2cbrcg228jcgj0ae@4ax.com>, To-Email-
Use-The-Envelope-Icon@My-Web-Site.com says...
On Mon, 1 Dec 2008 12:37:56 -0600, krw <krw@att.zzzzzzzzz> wrote:

In article <4ripi4l5fq728f9011i1p8d1r79a549m4h@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...
On Tue, 25 Nov 2008 19:51:36 -0800, JosephKK <quiettechblue@yahoo.com
wrote:

On Mon, 24 Nov 2008 15:27:56 -0800, "Joel Koltner"
zapwireDASHgroups@yahoo.com> wrote:

"Vladimir Vassilevsky" <antispam_bogus@hotmail.com> wrote in message
news:6uGWk.4982$8_3.1230@flpi147.ffdc.sbc.com...
BTW, I have heard many times of the idea of asynchronous CPU. So the results
of operations are not synchronized to a clock, but propagate further at the
natural speed. The synchronization is done by delay matching at the critical
points. Ideally, that should work faster then the clocked logic; perhaps the
variance of the delays kills the idea.

Intel CPUs use some "chunks" of asynchronous logic for, e.g., instruction
decoders, but what I've heard the presenters of papers on this topic stress is
that their goal is usually power reduction much moreso than speed.

It seems that there should be a textbook of asynchronous logic design out
there by now... besides going over the usual discussion of how you avoid race
conditions with your min terms/max terms, it'd also discuss the various clever
schemes people have come up with to do handshaking between multiple
asynchronous modules, perhaps discuss various historical results (like the
Hennessy & Patterson book does... when I took a class using it in college
years ago, the professor was pretty darned good so typically there "meat" of
H&P was just review anyway -- and it's not like the math was hard --, but I
always looked forward to their end--of-chapter "real life examples"
discussions), etc.

---Joel


There is and there isn't. It is presumed covered in the combinatorial
logic and sequential logic courses. But, of course it isn't really
covered. Most state machine courses are trash as well.


ME: Use a transparent latch.

Aren't all latches transparent?

No. Some are edge-triggered, such as 74HC74.

That's a D-Type master-slave flip-flop, no matter what the mustard
bible says.

Of course, that's how "edge-triggered" is accomplished.

The point is that it is not a latch.

Xilinx Software: WARNING -- You are using a transparent latch!

Xilinx' rules/technoloy/software hates latches. Other's have
nothing but. When in Rome, do as the groundrules writers do.

...Jim Thompson


Brings back a question I've broached before. Any VHDL or VHDL-like
program that generates schematics?

I don' know of any freebies, and the ones I've used aren't any good
for documentation (further than ports). They draw bug ugly
schematics. One alternative is to use schematic entry for top-level
and data flow, with VHDL for state machines. I find it easier to
just bite the bullet and go all VHDL for chips and schematics for
boards.

What I'd like would be a program... feed it a clocked truth table and
have it spit out a gate-level schematic.

I've used such things[*] but never found one that was useful for
anything more than very small bits of logic. Synplicity had one a
decade ago that would show either logical or technology views. Both
were very useful to learn what language constructs produced what
sorts of logic, but totally useless for anything more.

[*] A truth table can simply be expressed as a CASE so the tool can
do its thing.

--
Keith

 

[krw]

In article <sd99j4t3prabk2febcvitgv40tp42j1j9o@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...

On Mon, 01 Dec 2008 14:20:02 -0700, Jim Thompson
To-Email-Use-The-Envelope-Icon@My-Web-Site.com> wrote:


On Mon, 1 Dec 2008 13:45:26 -0600, krw <krw@att.zzzzzzzzz> wrote:

In article <k7c8j492pfa8ug98oa2cbrcg228jcgj0ae@4ax.com>, To-Email-
Use-The-Envelope-Icon@My-Web-Site.com says...
On Mon, 1 Dec 2008 12:37:56 -0600, krw <krw@att.zzzzzzzzz> wrote:

In article <4ripi4l5fq728f9011i1p8d1r79a549m4h@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...
On Tue, 25 Nov 2008 19:51:36 -0800, JosephKK <quiettechblue@yahoo.com
wrote:

On Mon, 24 Nov 2008 15:27:56 -0800, "Joel Koltner"
zapwireDASHgroups@yahoo.com> wrote:

"Vladimir Vassilevsky" <antispam_bogus@hotmail.com> wrote in message
news:6uGWk.4982$8_3.1230@flpi147.ffdc.sbc.com...
BTW, I have heard many times of the idea of asynchronous CPU. So the results
of operations are not synchronized to a clock, but propagate further at the
natural speed. The synchronization is done by delay matching at the critical
points. Ideally, that should work faster then the clocked logic; perhaps the
variance of the delays kills the idea.

Intel CPUs use some "chunks" of asynchronous logic for, e.g., instruction
decoders, but what I've heard the presenters of papers on this topic stress is
that their goal is usually power reduction much moreso than speed.

It seems that there should be a textbook of asynchronous logic design out
there by now... besides going over the usual discussion of how you avoid race
conditions with your min terms/max terms, it'd also discuss the various clever
schemes people have come up with to do handshaking between multiple
asynchronous modules, perhaps discuss various historical results (like the
Hennessy & Patterson book does... when I took a class using it in college
years ago, the professor was pretty darned good so typically there "meat" of
H&P was just review anyway -- and it's not like the math was hard --, but I
always looked forward to their end--of-chapter "real life examples"
discussions), etc.

---Joel


There is and there isn't. It is presumed covered in the combinatorial
logic and sequential logic courses. But, of course it isn't really
covered. Most state machine courses are trash as well.


ME: Use a transparent latch.

Aren't all latches transparent?

No. Some are edge-triggered, such as 74HC74.

That's a D-Type master-slave flip-flop, no matter what the mustard
bible says.

Of course, that's how "edge-triggered" is accomplished.



Xilinx Software: WARNING -- You are using a transparent latch!

Xilinx' rules/technoloy/software hates latches. Other's have
nothing but. When in Rome, do as the groundrules writers do.

...Jim Thompson


Brings back a question I've broached before. Any VHDL or VHDL-like
program that generates schematics?

...Jim Thompson

There is expensive software that will take VHDL and create a
schematic, apparently for people who aren't sure what they have
designed. The output I've seen looks like something one of my cats
would cough up.

You should swat your cats. One of ours has a "sensitive stomach"
and spits up its food regularly but has never made a mess like that.

Until you can see what synthesis produces these tools are important
in learning how to herd the cats.

It's tragic that there is not an industry-standard ascii format to
express schematics, like the LT Spice thing.

VHDL is pretty standard. ;-)

--
Keith

 

[John Larkin]

On Mon, 1 Dec 2008 22:00:57 -0600, krw <krw@att.bizzzzzzzzzz> wrote:

In article <j699j4lcumibvnnboacfihks09o7l7cltp@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...
On Mon, 1 Dec 2008 12:37:56 -0600, krw <krw@att.zzzzzzzzz> wrote:

In article <4ripi4l5fq728f9011i1p8d1r79a549m4h@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...
On Tue, 25 Nov 2008 19:51:36 -0800, JosephKK <quiettechblue@yahoo.com
wrote:

On Mon, 24 Nov 2008 15:27:56 -0800, "Joel Koltner"
zapwireDASHgroups@yahoo.com> wrote:

"Vladimir Vassilevsky" <antispam_bogus@hotmail.com> wrote in message
news:6uGWk.4982$8_3.1230@flpi147.ffdc.sbc.com...
BTW, I have heard many times of the idea of asynchronous CPU. So the results
of operations are not synchronized to a clock, but propagate further at the
natural speed. The synchronization is done by delay matching at the critical
points. Ideally, that should work faster then the clocked logic; perhaps the
variance of the delays kills the idea.

Intel CPUs use some "chunks" of asynchronous logic for, e.g., instruction
decoders, but what I've heard the presenters of papers on this topic stress is
that their goal is usually power reduction much moreso than speed.

It seems that there should be a textbook of asynchronous logic design out
there by now... besides going over the usual discussion of how you avoid race
conditions with your min terms/max terms, it'd also discuss the various clever
schemes people have come up with to do handshaking between multiple
asynchronous modules, perhaps discuss various historical results (like the
Hennessy & Patterson book does... when I took a class using it in college
years ago, the professor was pretty darned good so typically there "meat" of
H&P was just review anyway -- and it's not like the math was hard --, but I
always looked forward to their end--of-chapter "real life examples"
discussions), etc.

---Joel


There is and there isn't. It is presumed covered in the combinatorial
logic and sequential logic courses. But, of course it isn't really
covered. Most state machine courses are trash as well.


ME: Use a transparent latch.

Aren't all latches transparent?

Unless they are edge-triggered.

Then they're flip-flops. ;-)

Xilinx Software: WARNING -- You are using a transparent latch!

Xilinx' rules/technoloy/software hates latches. Other's have
nothing but. When in Rome, do as the groundrules writers do.

Sometimes a transparent latch can eliminate a full clock of pipeline
delay. They are also a handy way of crossing clock boundaries in some
situations. But they blaspheme The Church Of Synchronous Design.

No, only if the groundrules specify edge-triggered FFs. All IBM
(bipolar) mainframes used latch pairs or PHs ("latches" and
"triggers") as their register elements, and most is strictly
synchronous. Even the CMOS versions use latches, though they're
better hidden. ;-)

We mostly ignore the Xilinx warnings. A good, tight design can throw a
thousand or so.

I guess maybe! They throw so many it's impossible to ferret through
them to find the ones that will bite, and there are many. Decent
software would have the warning messages switchable by class, type,
and instance to allow the dangerous ones shine through the fog.

Those are called "fatal errors."

John

 

[krw]

In article <1jd9j4l97mqd1b3a7jc1hhfsvn55j15o6u@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...>

On Mon, 1 Dec 2008 22:00:57 -0600, krw <krw@att.bizzzzzzzzzz> wrote:

In article <j699j4lcumibvnnboacfihks09o7l7cltp@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...
On Mon, 1 Dec 2008 12:37:56 -0600, krw <krw@att.zzzzzzzzz> wrote:

In article <4ripi4l5fq728f9011i1p8d1r79a549m4h@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...
On Tue, 25 Nov 2008 19:51:36 -0800, JosephKK <quiettechblue@yahoo.com
wrote:

On Mon, 24 Nov 2008 15:27:56 -0800, "Joel Koltner"
zapwireDASHgroups@yahoo.com> wrote:

"Vladimir Vassilevsky" <antispam_bogus@hotmail.com> wrote in message
news:6uGWk.4982$8_3.1230@flpi147.ffdc.sbc.com...
BTW, I have heard many times of the idea of asynchronous CPU. So the results
of operations are not synchronized to a clock, but propagate further at the
natural speed. The synchronization is done by delay matching at the critical
points. Ideally, that should work faster then the clocked logic; perhaps the
variance of the delays kills the idea.

Intel CPUs use some "chunks" of asynchronous logic for, e.g., instruction
decoders, but what I've heard the presenters of papers on this topic stress is
that their goal is usually power reduction much moreso than speed.

It seems that there should be a textbook of asynchronous logic design out
there by now... besides going over the usual discussion of how you avoid race
conditions with your min terms/max terms, it'd also discuss the various clever
schemes people have come up with to do handshaking between multiple
asynchronous modules, perhaps discuss various historical results (like the
Hennessy & Patterson book does... when I took a class using it in college
years ago, the professor was pretty darned good so typically there "meat" of
H&P was just review anyway -- and it's not like the math was hard --, but I
always looked forward to their end--of-chapter "real life examples"
discussions), etc.

---Joel


There is and there isn't. It is presumed covered in the combinatorial
logic and sequential logic courses. But, of course it isn't really
covered. Most state machine courses are trash as well.


ME: Use a transparent latch.

Aren't all latches transparent?

Unless they are edge-triggered.

Then they're flip-flops. ;-)

Xilinx Software: WARNING -- You are using a transparent latch!

Xilinx' rules/technoloy/software hates latches. Other's have
nothing but. When in Rome, do as the groundrules writers do.

Sometimes a transparent latch can eliminate a full clock of pipeline
delay. They are also a handy way of crossing clock boundaries in some
situations. But they blaspheme The Church Of Synchronous Design.

No, only if the groundrules specify edge-triggered FFs. All IBM
(bipolar) mainframes used latch pairs or PHs ("latches" and
"triggers") as their register elements, and most is strictly
synchronous. Even the CMOS versions use latches, though they're
better hidden. ;-)

We mostly ignore the Xilinx warnings. A good, tight design can throw a
thousand or so.

I guess maybe! They throw so many it's impossible to ferret through
them to find the ones that will bite, and there are many. Decent
software would have the warning messages switchable by class, type,
and instance to allow the dangerous ones shine through the fog.

Those are called "fatal errors."

No, "fatal errors" are those that will prevent synthesis. Many
"warnings" will tell you that you are producing trash, but
producing it nonetheless. Ignoring warnings is dumb, but hardly
criminal given that one important needle may be lurking among a
large pile of useless hay. I always pick through all warning
messages at least once before a design review (it should be a
requirement of said design review).

 

[JosephKK]

On Mon, 01 Dec 2008 19:03:45 -0800, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Mon, 1 Dec 2008 12:37:56 -0600, krw <krw@att.zzzzzzzzz> wrote:

In article <4ripi4l5fq728f9011i1p8d1r79a549m4h@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...
On Tue, 25 Nov 2008 19:51:36 -0800, JosephKK <quiettechblue@yahoo.com
wrote:

On Mon, 24 Nov 2008 15:27:56 -0800, "Joel Koltner"
zapwireDASHgroups@yahoo.com> wrote:

"Vladimir Vassilevsky" <antispam_bogus@hotmail.com> wrote in message
news:6uGWk.4982$8_3.1230@flpi147.ffdc.sbc.com...
BTW, I have heard many times of the idea of asynchronous CPU. So the results
of operations are not synchronized to a clock, but propagate further at the
natural speed. The synchronization is done by delay matching at the critical
points. Ideally, that should work faster then the clocked logic; perhaps the
variance of the delays kills the idea.

Intel CPUs use some "chunks" of asynchronous logic for, e.g., instruction
decoders, but what I've heard the presenters of papers on this topic stress is
that their goal is usually power reduction much moreso than speed.

It seems that there should be a textbook of asynchronous logic design out
there by now... besides going over the usual discussion of how you avoid race
conditions with your min terms/max terms, it'd also discuss the various clever
schemes people have come up with to do handshaking between multiple
asynchronous modules, perhaps discuss various historical results (like the
Hennessy & Patterson book does... when I took a class using it in college
years ago, the professor was pretty darned good so typically there "meat" of
H&P was just review anyway -- and it's not like the math was hard --, but I
always looked forward to their end--of-chapter "real life examples"
discussions), etc.

---Joel


There is and there isn't. It is presumed covered in the combinatorial
logic and sequential logic courses. But, of course it isn't really
covered. Most state machine courses are trash as well.


ME: Use a transparent latch.

Aren't all latches transparent?

Unless they are edge-triggered.


Xilinx Software: WARNING -- You are using a transparent latch!

Xilinx' rules/technoloy/software hates latches. Other's have
nothing but. When in Rome, do as the groundrules writers do.

Sometimes a transparent latch can eliminate a full clock of pipeline
delay. They are also a handy way of crossing clock boundaries in some
situations. But they blaspheme The Church Of Synchronous Design.

We mostly ignore the Xilinx warnings. A good, tight design can throw a
thousand or so.

John

Way back in the late 1960's i remember seeing the equivalent circuits
for ttl master slave flip flops and edge triggered flip flops. The
circuits were very different and the described action was very
different as well.
In particular if you had a longish clock input on the master slave it
would not change the output until the clock went back to the rest
state; whereas the edge triggered would always change within some x
number of nanoseconds regardless of the level on the clock input.
(Assuming setup and hold conditions were met.)