Virtex-E Select-RAM refresh rate

[Stefan Tillich]

Hello,

I have a custom-made FPGA-board with a Xilinx Virtex-E (XCV-300E)
FPGA. I'm trying to measure the FPGA's power consumption over a sensor
resistor betwenn the FGPA's ground pins and the board's ground.

The trace of the current has peaks, which occur at a rate of
approximately 700 kHz (independent whether the FPGA is configured or
not). I was wondering if those peaks may result from the refreshing
of the FPGA's BlockRAM cells.

Is that possible and if the BlockRAM cells' refreshing is causing the
current peaks, is there a way to deactivate refreshing (as I'm not
using the RAM's) with the Xilinx WebPack (ISE 5)?

Best regards,
Stefan Tillich

 

[Steve Casselman]

There is not refreash rate for the ram. It is static ram and does not need
to be refreashed. Your 700K Hz could be lots of stuff. But I would suspect
your design.

Steve


"Stefan Tillich" <stefanti@gmx.at> wrote in message
news:fca6d5eb.0309010503.1d26bfe@posting.google.com...

Hello,

I have a custom-made FPGA-board with a Xilinx Virtex-E (XCV-300E)
FPGA. I'm trying to measure the FPGA's power consumption over a sensor
resistor betwenn the FGPA's ground pins and the board's ground.

The trace of the current has peaks, which occur at a rate of
approximately 700 kHz (independent whether the FPGA is configured or
not). I was wondering if those peaks may result from the refreshing
of the FPGA's BlockRAM cells.

Is that possible and if the BlockRAM cells' refreshing is causing the
current peaks, is there a way to deactivate refreshing (as I'm not
using the RAM's) with the Xilinx WebPack (ISE 5)?

Best regards,
Stefan Tillich