M
Matt
Guest
Greetings, <p> I am having a strage time with some code I recently wrote to implement a UART - the code is working fine now, but a problem cropped up that is baffling me. This design is being synthesized in Xilinx ISE 5 and implemented into a Spartan-II XD2S50 device. I'm on something of a learning curve with things right now so please go easy on me! 
<p> when 10 => -- Stop Bit <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;BitPos := 11; -- next is holding pattern for breaks <BR>
if(FIFOhead = 3) then <BR>
FIFOhead := 0; -- wrap around <BR>
else <BR>
FIFOhead := FIFOhead + 1; <BR>
end if; <p> FIFO(FIFOhead)(8) <= RxD; -- stash the break bit <BR>
FIFO(FIFOhead)(7 downto 0) <= RReg; -- stash the received data <p> The two FIFO array assignment statements at the bottom are the predominant problem.... The object is to assign the break bit to the 9th bit of the array of 9-bit words (indexed by the process variable 'FIFOhead'), and then assign the databyte to the lower part. As written and synthesized, the above writes ONLY the received byte and NOT the break bit. If the statements are exchanged, the opposite happens. In short, only the SECOND assignment appears to be executing properly. If a 'dummy' statement is inserted, so the code looks like: <p> ............ <BR>
end if; <BR>
FIFO(FIFOhead)(7 downto 0) <= RReg; -- stash the received data <BR>
FIFO(FIFOhead)(8) <= RxD; -- stash the break bit <BR>
FIFO(FIFOhead)(7 downto 0) <= RReg; -- stash the received data <p> then both assignments work properly. There appears to be some amount of latency inherent in updating the variable before it can be used as an index, but why? And what is the proper way to detect or circumvent this problem? This fix works temporarily just fine, but I fear this problem may explain similarly strange behavior in other sections of code. If this IS a latency problem, how should I go about detecting these sort of things in my design to ensure all code is relatively bulletproof? All of the VHDL texts I have here really only cover language theory and simulation synthesis, not the perils of things like proper floorplanning of the design. What's the best way to work on filling in the learning gaps? Thanks in advance for any insight! <p>-- Matt
<p> when 10 => -- Stop Bit <BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;BitPos := 11; -- next is holding pattern for breaks <BR>
if(FIFOhead = 3) then <BR>
FIFOhead := 0; -- wrap around <BR>
else <BR>
FIFOhead := FIFOhead + 1; <BR>
end if; <p> FIFO(FIFOhead)(8) <= RxD; -- stash the break bit <BR>
FIFO(FIFOhead)(7 downto 0) <= RReg; -- stash the received data <p> The two FIFO array assignment statements at the bottom are the predominant problem.... The object is to assign the break bit to the 9th bit of the array of 9-bit words (indexed by the process variable 'FIFOhead'), and then assign the databyte to the lower part. As written and synthesized, the above writes ONLY the received byte and NOT the break bit. If the statements are exchanged, the opposite happens. In short, only the SECOND assignment appears to be executing properly. If a 'dummy' statement is inserted, so the code looks like: <p> ............ <BR>
end if; <BR>
FIFO(FIFOhead)(7 downto 0) <= RReg; -- stash the received data <BR>
FIFO(FIFOhead)(8) <= RxD; -- stash the break bit <BR>
FIFO(FIFOhead)(7 downto 0) <= RReg; -- stash the received data <p> then both assignments work properly. There appears to be some amount of latency inherent in updating the variable before it can be used as an index, but why? And what is the proper way to detect or circumvent this problem? This fix works temporarily just fine, but I fear this problem may explain similarly strange behavior in other sections of code. If this IS a latency problem, how should I go about detecting these sort of things in my design to ensure all code is relatively bulletproof? All of the VHDL texts I have here really only cover language theory and simulation synthesis, not the perils of things like proper floorplanning of the design. What's the best way to work on filling in the learning gaps? Thanks in advance for any insight! <p>-- Matt