R
Rick C
Guest
Another day, another syntax issue...
In my project library file.
constant LED_Data_Max : natural := 23;
subtype LED_Data_Type is unsigned (LED_Data_Max downto 0);
type LED_RED_rng is range 23 downto 16;
type LED_GRN_rng is range 15 downto 8;
type LED_BLU_rng is range 7 downto 0;
In the entity...
procedure CommonAssert (
LED_addr : natural;
RGB : LED_Data_Type;
Color_Ref : LED_Data_Type
) is
begin
assert (RGB = Color_Ref)
report \" LED \" & integer\'image(LED_addr) &
\" error, time = \" & time\'image(now) &
\", Red = \" & to_hstring(RGB(LED_RED_rng)) & ...
The error complains about LED_RED_rng
\"Type of discrete range is different from the corresponding index\"
I just don\'t get what I am doing wrong. What would the discrete range \"type\" be??? Is this the same sort of problem I had previously where a non-constant can\'t be used to select a bit from a vector? Or is it so restrictive that I can\'t even use a fixed range of bits that aren\'t the entire vector?
I would say I\'m ready to use Verilog but I think that might be even more clumsy when trying to do things like this particular detail.
--
Rick C.
- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209
In my project library file.
constant LED_Data_Max : natural := 23;
subtype LED_Data_Type is unsigned (LED_Data_Max downto 0);
type LED_RED_rng is range 23 downto 16;
type LED_GRN_rng is range 15 downto 8;
type LED_BLU_rng is range 7 downto 0;
In the entity...
procedure CommonAssert (
LED_addr : natural;
RGB : LED_Data_Type;
Color_Ref : LED_Data_Type
) is
begin
assert (RGB = Color_Ref)
report \" LED \" & integer\'image(LED_addr) &
\" error, time = \" & time\'image(now) &
\", Red = \" & to_hstring(RGB(LED_RED_rng)) & ...
The error complains about LED_RED_rng
\"Type of discrete range is different from the corresponding index\"
I just don\'t get what I am doing wrong. What would the discrete range \"type\" be??? Is this the same sort of problem I had previously where a non-constant can\'t be used to select a bit from a vector? Or is it so restrictive that I can\'t even use a fixed range of bits that aren\'t the entire vector?
I would say I\'m ready to use Verilog but I think that might be even more clumsy when trying to do things like this particular detail.
--
Rick C.
- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209