verilog syntax check

[Yang Luo]

I'm using modelsim se 10.1c. I find that modelsim for syntax checking is not strict.
There are some examples:
1) I use default settings to build a project. There is no error or warning whenn compiling but I used an undefined variable, only when simulating the signal is red line.
Example code:
input [D_SIZE: 0] i_a;
wire signed [D_SIZE: 0] w_a;
assign w_ia = i_a;
2) When using unassigned variable , the same situation with above.
Example code:
wire signed [D_SIZE: 0] w_ib;
wire signed [D_SIZE: 0] w_id;
wire signed [D_SIZE: 0] w_bd;
assign w_bd = w_ib - w_id;
Question:
How should I do to get more strict syntax checking in modelsim? If modelsim cannot get strict checking, is there other software can do?
Another question:
Modelsim rebuilding and cleanup project, how to operate? how to operate that I can know the compilation is all recompiled?

 

[KJ]

On Monday, June 8, 2015 at 8:54:31 AM UTC-4, Yang Luo wrote:

Question:
How should I do to get more strict syntax checking in modelsim? If modelsim cannot get strict checking, is there other software can do?

If your code is intended to be synthesized at some point, then a relatively easy to catch unconnected inputs like you have in your code is simply to run it through synthesis (i.e. Quartus if targeting Altera). An unconnected input during synthesis will cause a warning to be reported. Peruse the list of warnings and go from there.

Kevin Jennings

 

[rickman]

On 6/8/2015 8:54 AM, Yang Luo wrote:

I'm using modelsim se 10.1c. I find that modelsim for syntax checking is not strict.
There are some examples:
1) I use default settings to build a project. There is no error or warning whenn compiling but I used an undefined variable, only when simulating the signal is red line.
Example code:
input [D_SIZE: 0] i_a;
wire signed [D_SIZE: 0] w_a;
assign w_ia = i_a;
2) When using unassigned variable , the same situation with above.
Example code:
wire signed [D_SIZE: 0] w_ib;
wire signed [D_SIZE: 0] w_id;
wire signed [D_SIZE: 0] w_bd;
assign w_bd = w_ib - w_id;
Question:
How should I do to get more strict syntax checking in modelsim? If modelsim cannot get strict checking, is there other software can do?
Another question:
Modelsim rebuilding and cleanup project, how to operate? how to operate that I can know the compilation is all recompiled?

I see you posted this to the verilog and VHDL groups. You might try
posting to the FPGA group instead of VHDL.

--

Rick