B
Ben Gerblich
Guest
Hi,
From a CLKDLL, how do I gate the CLKDV signal with LOCKED without
getting the following warning when implementing:
WARNING:NgdBuild:477 - clock net 'buffered10m' has non-clock
connections. These problematic connections include: pin i0 on block
u4_u1_clkout1 with type LUT2
I want to gate all the startup/synchronising clocks from the CLKDV
signal until locked is achieved. My aim is to block the
startup/synchronising waveform from getting to an external IC until the
locked is achieved. The startup/synchronising takes about 24usec, during
which time about 240x 10mhz clock edges are received by the external IC.
Id like to only provide the external IC with 10mhz when the locked
signal is achieved. Am I worrying about nothing? The IC (KAC1310) does
not have an enable.
I understand I can use the LOCKED signal as a nRESET to sub-modules,
therefore this startup/synchronising waveform does not affect
sub-modules.
ISE 5.02.2i, SPARTAN-II, KAC1310.
Thanks, Ben.
From a CLKDLL, how do I gate the CLKDV signal with LOCKED without
getting the following warning when implementing:
WARNING:NgdBuild:477 - clock net 'buffered10m' has non-clock
connections. These problematic connections include: pin i0 on block
u4_u1_clkout1 with type LUT2
I want to gate all the startup/synchronising clocks from the CLKDV
signal until locked is achieved. My aim is to block the
startup/synchronising waveform from getting to an external IC until the
locked is achieved. The startup/synchronising takes about 24usec, during
which time about 240x 10mhz clock edges are received by the external IC.
Id like to only provide the external IC with 10mhz when the locked
signal is achieved. Am I worrying about nothing? The IC (KAC1310) does
not have an enable.
I understand I can use the LOCKED signal as a nRESET to sub-modules,
therefore this startup/synchronising waveform does not affect
sub-modules.
ISE 5.02.2i, SPARTAN-II, KAC1310.
Thanks, Ben.